src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 /* This union is used to avoid warnings/miscompilation
  17    with float to uint32_t casts due to strict-aliasing */
  18 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  19
  20 struct radeon_context;
  21 typedef struct radeon_context radeonContextRec;
  22 typedef struct radeon_context *radeonContextPtr;
  23
  24
  25 #define TEX_0   0x1
  26 #define TEX_1   0x2
  27 #define TEX_2   0x4
  28 #define TEX_3   0x8
  29 #define TEX_4   0x10
  30 #define TEX_5   0x20
  31
  32 /* Rasterizing fallbacks */
  33 /* See correponding strings in r200_swtcl.c */
  34 #define RADEON_FALLBACK_TEXTURE         0x0001
  35 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  36 #define RADEON_FALLBACK_STENCIL         0x0004
  37 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  38 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  39 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  40 #define RADEON_FALLBACK_DISABLE         0x0040
  41 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  42
  43 #define R200_FALLBACK_TEXTURE           0x01
  44 #define R200_FALLBACK_DRAW_BUFFER       0x02
  45 #define R200_FALLBACK_STENCIL           0x04
  46 #define R200_FALLBACK_RENDER_MODE       0x08
  47 #define R200_FALLBACK_DISABLE           0x10
  48 #define R200_FALLBACK_BORDER_MODE       0x20
  49
  50 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  51 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  52 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  53 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  54 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  55 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  56 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  57 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  58 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  59
  60 /* The blit width for texture uploads
  61  */
  62 #define BLIT_WIDTH_BYTES 1024
  63
  64 /* Use the templated vertex format:
  65  */
  66 #define COLOR_IS_RGBA
  67 #define TAG(x) radeon##x
  68 #include "tnl_dd/t_dd_vertex.h"
  69 #undef TAG
  70
  71 struct radeon_colorbuffer_state {
  72         GLuint clear;
  73         int roundEnable;
  74         struct radeon_renderbuffer *rrb;
  75 };
  76
  77 struct radeon_depthbuffer_state {
  78         GLuint clear;
  79         GLfloat scale;
  80         struct radeon_renderbuffer *rrb;
  81 };
  82
  83 struct radeon_scissor_state {
  84         drm_clip_rect_t rect;
  85         GLboolean enabled;
  86
  87         GLuint numClipRects;    /* Cliprects active */
  88         GLuint numAllocedClipRects;     /* Cliprects available */
  89         drm_clip_rect_t *pClipRects;
  90 };
  91
  92 struct radeon_stencilbuffer_state {
  93         GLboolean hwBuffer;
  94         GLuint clear;           /* rb3d_stencilrefmask value */
  95 };
  96
  97 struct radeon_stipple_state {
  98         GLuint mask[32];
  99 };
 100
 101 struct radeon_state_atom {
 102         struct radeon_state_atom *next, *prev;
 103         const char *name;       /* for debug */
 104         int cmd_size;           /* size in bytes */
 105         GLuint idx;
 106         GLuint is_tcl;
 107         GLuint *cmd;            /* one or more cmd's */
 108         GLuint *lastcmd;                /* one or more cmd's */
 109         GLboolean dirty;        /* dirty-mark in emit_state_list */
 110         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 111         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 112 };
 113
 114 struct radeon_hw_state {
 115         /* Head of the linked list of state atoms. */
 116         struct radeon_state_atom atomlist;
 117         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 118         GLboolean is_dirty, all_dirty;
 119 };
 120
 121
 122 /* Texture related */
 123 typedef struct _radeon_texture_image radeon_texture_image;
 124
 125 struct _radeon_texture_image {
 126         struct gl_texture_image base;
 127
 128         /**
 129          * If mt != 0, the image is stored in hardware format in the
 130          * given mipmap tree. In this case, base.Data may point into the
 131          * mapping of the buffer object that contains the mipmap tree.
 132          *
 133          * If mt == 0, the image is stored in normal memory pointed to
 134          * by base.Data.
 135          */
 136         struct _radeon_mipmap_tree *mt;
 137         struct radeon_bo *bo;
 138
 139         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 140         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 141 };
 142
 143
 144 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 145 {
 146         return (radeon_texture_image*)image;
 147 }
 148
 149
 150 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 151
 152 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 153
 154 /* Texture object in locally shared texture space.
 155  */
 156 struct radeon_tex_obj {
 157   //    driTextureObject base;
 158         struct gl_texture_object base;
 159         struct _radeon_mipmap_tree *mt;
 160
 161         /**
 162          * This is true if we've verified that the mipmap tree above is complete
 163          * and so on.
 164          */
 165         GLboolean validated;
 166
 167         GLuint override_offset;
 168         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 169         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 170         struct radeon_bo *bo;
 171
 172         GLuint bufAddr;         /* Offset to start of locally
 173                                    shared texture block */
 174
 175         GLuint dirty_state;     /* Flags (1 per texunit) for
 176                                    whether or not this texobj
 177                                    has dirty hardware state
 178                                    (pp_*) that needs to be
 179                                    brought into the
 180                                    texunit. */
 181
 182         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 183         /* Six, for the cube faces */
 184
 185
 186
 187         GLuint pp_txfilter;     /* hardware register values */
 188         GLuint pp_txformat;
 189         GLuint pp_txformat_x;
 190         GLuint pp_txoffset;     /* Image location in texmem.
 191                                    All cube faces follow. */
 192         GLuint pp_txsize;       /* npot only */
 193         GLuint pp_txpitch;      /* npot only */
 194         GLuint pp_border_color;
 195         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 196
 197         GLuint pp_txfilter_1;   /*  r300 */
 198
 199         GLboolean border_fallback;
 200
 201
 202 };
 203
 204 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 205 {
 206         return (radeonTexObj*)texObj;
 207 }
 208
 209 /* Need refcounting on dma buffers:
 210  */
 211 struct radeon_dma_buffer {
 212         int refcount;           /* the number of retained regions in buf */
 213         drmBufPtr buf;
 214 };
 215
 216 struct radeon_aos {
 217         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 218         int offset; /** Offset into buffer object, in bytes */
 219         int components; /** Number of components per vertex */
 220         int stride; /** Stride in dwords (may be 0 for repeating) */
 221         int count; /** Number of vertices */
 222 };
 223
 224 struct radeon_dma {
 225         /* Active dma region.  Allocations for vertices and retained
 226          * regions come from here.  Also used for emitting random vertices,
 227          * these may be flushed by calling flush_current();
 228          */
 229         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 230         int current_used; /** Number of bytes allocated and forgotten about */
 231         int current_vertexptr; /** End of active vertex region */
 232
 233         /**
 234          * If current_vertexptr != current_used then flush must be non-zero.
 235          * flush must be called before non-active vertex allocations can be
 236          * performed.
 237          */
 238         void (*flush) (GLcontext *);
 239
 240         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 241          * for which a DISCARD command is currently queued in the command buffer
 242 .
 243          */
 244         GLuint nr_released_bufs;
 245 };
 246
 247 /* radeon_swtcl.c
 248  */
 249 struct radeon_swtcl_info {
 250
 251         GLuint RenderIndex;
 252         GLuint vertex_size;
 253         GLubyte *verts;
 254
 255         /* Fallback rasterization functions
 256          */
 257         GLuint hw_primitive;
 258         GLenum render_primitive;
 259         GLuint numverts;
 260
 261         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 262         GLuint vertex_attr_count;
 263
 264 };
 265
 266 struct radeon_ioctl {
 267         GLuint vertex_offset;
 268         struct radeon_bo *bo;
 269         GLuint vertex_size;
 270 };
 271
 272 #define RADEON_MAX_PRIMS 64
 273
 274 struct radeon_prim {
 275         GLuint start;
 276         GLuint end;
 277         GLuint prim;
 278 };
 279
 280 static INLINE GLuint radeonPackColor(GLuint cpp,
 281                                      GLubyte r, GLubyte g,
 282                                      GLubyte b, GLubyte a)
 283 {
 284         switch (cpp) {
 285         case 2:
 286                 return PACK_COLOR_565(r, g, b);
 287         case 4:
 288                 return PACK_COLOR_8888(a, r, g, b);
 289         default:
 290                 return 0;
 291         }
 292 }
 293
 294 #define MAX_CMD_BUF_SZ (16*1024)
 295
 296 #define MAX_DMA_BUF_SZ (64*1024)
 297
 298 struct radeon_store {
 299         GLuint statenr;
 300         GLuint primnr;
 301         char cmd_buf[MAX_CMD_BUF_SZ];
 302         int cmd_used;
 303         int elts_start;
 304 };
 305
 306 struct radeon_dri_mirror {
 307         __DRIcontextPrivate *context;   /* DRI context */
 308         __DRIscreenPrivate *screen;     /* DRI screen */
 309
 310    /**
 311     * DRI drawable bound to this context for drawing.
 312     */
 313         __DRIdrawablePrivate *drawable;
 314
 315    /**
 316     * DRI drawable bound to this context for reading.
 317     */
 318         __DRIdrawablePrivate *readable;
 319
 320         drm_context_t hwContext;
 321         drm_hw_lock_t *hwLock;
 322         int fd;
 323         int drmMinor;
 324 };
 325
 326 #define DEBUG_TEXTURE   0x001
 327 #define DEBUG_STATE     0x002
 328 #define DEBUG_IOCTL     0x004
 329 #define DEBUG_PRIMS     0x008
 330 #define DEBUG_VERTS     0x010
 331 #define DEBUG_FALLBACKS 0x020
 332 #define DEBUG_VFMT      0x040
 333 #define DEBUG_CODEGEN   0x080
 334 #define DEBUG_VERBOSE   0x100
 335 #define DEBUG_DRI       0x200
 336 #define DEBUG_DMA       0x400
 337 #define DEBUG_SANITY    0x800
 338 #define DEBUG_SYNC      0x1000
 339 #define DEBUG_PIXEL     0x2000
 340 #define DEBUG_MEMORY    0x4000
 341
 342
 343
 344 typedef void (*radeon_tri_func) (radeonContextPtr,
 345                                  radeonVertex *,
 346                                  radeonVertex *, radeonVertex *);
 347
 348 typedef void (*radeon_line_func) (radeonContextPtr,
 349                                   radeonVertex *, radeonVertex *);
 350
 351 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 352
 353 struct radeon_state {
 354         struct radeon_colorbuffer_state color;
 355         struct radeon_depthbuffer_state depth;
 356         struct radeon_scissor_state scissor;
 357         struct radeon_stencilbuffer_state stencil;
 358 };
 359
 360 /**
 361  * This structure holds the command buffer while it is being constructed.
 362  *
 363  * The first batch of commands in the buffer is always the state that needs
 364  * to be re-emitted when the context is lost. This batch can be skipped
 365  * otherwise.
 366  */
 367 struct radeon_cmdbuf {
 368         struct radeon_cs_manager    *csm;
 369         struct radeon_cs            *cs;
 370         int size; /** # of dwords total */
 371         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 372 };
 373
 374 struct radeon_context {
 375    GLcontext *glCtx;
 376    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 377
 378    /* Texture object bookkeeping
 379     */
 380    unsigned              nr_heaps;
 381    driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
 382    driTextureObject      swapped;
 383    int                   texture_depth;
 384    float                 initialMaxAnisotropy;
 385
 386   struct radeon_dma dma;
 387   struct radeon_hw_state hw;
 388    /* Rasterization and vertex state:
 389     */
 390    GLuint TclFallback;
 391    GLuint Fallback;
 392    GLuint NewGLState;
 393    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 394
 395    /* Page flipping */
 396    GLuint doPageFlip;
 397
 398    /* Drawable, cliprect and scissor information */
 399    GLuint numClipRects; /* Cliprects for the draw buffer */
 400    drm_clip_rect_t *pClipRects;
 401    unsigned int lastStamp;
 402    GLboolean lost_context;
 403    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 404
 405    /* Mirrors of some DRI state */
 406    struct radeon_dri_mirror dri;
 407
 408    /* Busy waiting */
 409    GLuint do_usleeps;
 410    GLuint do_irqs;
 411    GLuint irqsEmitted;
 412    drm_radeon_irq_wait_t iw;
 413
 414    /* buffer swap */
 415    int64_t swap_ust;
 416    int64_t swap_missed_ust;
 417
 418    GLuint swap_count;
 419    GLuint swap_missed_count;
 420
 421    /* Derived state - for r300 only */
 422    struct radeon_state state;
 423
 424    struct radeon_swtcl_info swtcl;
 425    /* Configuration cache
 426     */
 427    driOptionCache optionCache;
 428
 429    struct radeon_cmdbuf cmdbuf;
 430
 431    struct {
 432            void (*get_lock)(radeonContextPtr radeon);
 433            void (*update_viewport_offset)(GLcontext *ctx);
 434            void (*update_draw_buffer)(GLcontext *ctx);
 435            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 436            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 437            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 438            void (*pre_emit_state)(radeonContextPtr rmesa);
 439    } vtbl;
 440 };
 441
 442 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 443
 444 /**
 445  * This function takes a float and packs it into a uint32_t
 446  */
 447 static INLINE uint32_t radeonPackFloat32(float fl)
 448 {
 449         union {
 450                 float fl;
 451                 uint32_t u;
 452         } u;
 453
 454         u.fl = fl;
 455         return u.u;
 456 }
 457
 458 /* This is probably wrong for some values, I need to test this
 459  * some more.  Range checking would be a good idea also..
 460  *
 461  * But it works for most things.  I'll fix it later if someone
 462  * else with a better clue doesn't
 463  */
 464 static INLINE uint32_t radeonPackFloat24(float f)
 465 {
 466         float mantissa;
 467         int exponent;
 468         uint32_t float24 = 0;
 469
 470         if (f == 0.0)
 471                 return 0;
 472
 473         mantissa = frexpf(f, &exponent);
 474
 475         /* Handle -ve */
 476         if (mantissa < 0) {
 477                 float24 |= (1 << 23);
 478                 mantissa = mantissa * -1.0;
 479         }
 480         /* Handle exponent, bias of 63 */
 481         exponent += 62;
 482         float24 |= (exponent << 16);
 483         /* Kill 7 LSB of mantissa */
 484         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 485
 486         return float24;
 487 }
 488
 489 GLboolean radeonInitContext(radeonContextPtr radeon,
 490                             struct dd_function_table* functions,
 491                             const __GLcontextModes * glVisual,
 492                             __DRIcontextPrivate * driContextPriv,
 493                             void *sharedContextPrivate);
 494
 495 void radeonCleanupContext(radeonContextPtr radeon);
 496 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 497 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 498 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 499                             __DRIdrawablePrivate * driDrawPriv,
 500                             __DRIdrawablePrivate * driReadPriv);
 501
 502 /* ================================================================
 503  * Debugging:
 504  */
 505 #define DO_DEBUG                1
 506
 507 #if DO_DEBUG
 508 extern int RADEON_DEBUG;
 509 #else
 510 #define RADEON_DEBUG            0
 511 #endif
 512
 513 #endif