2 #ifndef COMMON_CONTEXT_H
3 #define COMMON_CONTEXT_H
5 #include "math/m_vector.h"
6 #include "tnl/t_context.h"
7 #include "main/colormac.h"
9 #include "radeon_screen.h"
10 #include "radeon_debug.h"
11 #include "radeon_drm.h"
13 #include "tnl/t_vertex.h"
14 #include "swrast/s_context.h"
16 struct radeon_context
;
18 #include "radeon_bo_gem.h"
19 #include "radeon_cs_gem.h"
21 /* This union is used to avoid warnings/miscompilation
22 with float to uint32_t casts due to strict-aliasing */
23 typedef union { GLfloat f
; uint32_t ui32
; } float_ui32_type
;
25 struct radeon_context
;
26 typedef struct radeon_context radeonContextRec
;
27 typedef struct radeon_context
*radeonContextPtr
;
37 /* Rasterizing fallbacks */
38 /* See correponding strings in r200_swtcl.c */
39 #define RADEON_FALLBACK_TEXTURE 0x0001
40 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
41 #define RADEON_FALLBACK_STENCIL 0x0004
42 #define RADEON_FALLBACK_RENDER_MODE 0x0008
43 #define RADEON_FALLBACK_BLEND_EQ 0x0010
44 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
45 #define RADEON_FALLBACK_DISABLE 0x0040
46 #define RADEON_FALLBACK_BORDER_MODE 0x0080
47 #define RADEON_FALLBACK_DEPTH_BUFFER 0x0100
48 #define RADEON_FALLBACK_STENCIL_BUFFER 0x0200
50 #define R200_FALLBACK_TEXTURE 0x01
51 #define R200_FALLBACK_DRAW_BUFFER 0x02
52 #define R200_FALLBACK_STENCIL 0x04
53 #define R200_FALLBACK_RENDER_MODE 0x08
54 #define R200_FALLBACK_DISABLE 0x10
55 #define R200_FALLBACK_BORDER_MODE 0x20
57 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
58 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
59 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
60 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
61 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
62 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
63 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
64 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
65 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
67 /* The blit width for texture uploads
69 #define BLIT_WIDTH_BYTES 1024
71 /* Use the templated vertex format:
74 #define TAG(x) radeon##x
75 #include "tnl_dd/t_dd_vertex.h"
78 #define RADEON_RB_CLASS 0xdeadbeef
80 struct radeon_renderbuffer
82 struct swrast_renderbuffer base
;
86 /* unsigned int offset; */
89 struct radeon_bo
*map_bo
;
91 int map_x
, map_y
, map_w
, map_h
;
95 uint32_t draw_offset
; /* FBO */
96 /* boo Xorg 6.8.2 compat */
99 GLuint pf_pending
; /**< sequence number of pending flip */
100 __DRIdrawable
*dPriv
;
103 struct radeon_framebuffer
105 struct gl_framebuffer base
;
107 struct radeon_renderbuffer
*color_rb
[2];
111 struct radeon_colorbuffer_state
{
113 struct gl_renderbuffer
*rb
;
114 uint32_t draw_offset
; /* offset into color renderbuffer - FBOs */
117 struct radeon_depthbuffer_state
{
118 struct gl_renderbuffer
*rb
;
121 struct radeon_scissor_state
{
122 drm_clip_rect_t rect
;
126 struct radeon_state_atom
{
127 struct radeon_state_atom
*next
, *prev
;
128 const char *name
; /* for debug */
129 int cmd_size
; /* size in bytes */
132 GLuint
*cmd
; /* one or more cmd's */
133 GLuint
*lastcmd
; /* one or more cmd's */
134 GLboolean dirty
; /* dirty-mark in emit_state_list */
135 int (*check
) (struct gl_context
*, struct radeon_state_atom
*atom
); /* is this state active? */
136 void (*emit
) (struct gl_context
*, struct radeon_state_atom
*atom
);
139 struct radeon_hw_state
{
140 /* Head of the linked list of state atoms. */
141 struct radeon_state_atom atomlist
;
142 int max_state_size
; /* Number of bytes necessary for a full state emit. */
143 int max_post_flush_size
; /* Number of bytes necessary for post flushing emits */
144 GLboolean is_dirty
, all_dirty
;
148 /* Texture related */
149 typedef struct _radeon_texture_image radeon_texture_image
;
153 * This is a subclass of swrast_texture_image since we use swrast
154 * for software fallback rendering.
156 struct _radeon_texture_image
{
157 struct swrast_texture_image base
;
160 * If mt != 0, the image is stored in hardware format in the
161 * given mipmap tree. In this case, base.Data may point into the
162 * mapping of the buffer object that contains the mipmap tree.
164 * If mt == 0, the image is stored in normal memory pointed to
167 struct _radeon_mipmap_tree
*mt
;
168 struct radeon_bo
*bo
;
169 GLboolean used_as_render_target
;
173 static inline radeon_texture_image
*get_radeon_texture_image(struct gl_texture_image
*image
)
175 return (radeon_texture_image
*)image
;
179 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
181 #define RADEON_TXO_MICRO_TILE (1 << 3)
183 /* Texture object in locally shared texture space.
185 struct radeon_tex_obj
{
186 struct gl_texture_object base
;
187 struct _radeon_mipmap_tree
*mt
;
190 * This is true if we've verified that the mipmap tree above is complete
194 /* Minimum LOD to be used during rendering */
196 /* Miximum LOD to be used during rendering */
199 GLuint override_offset
;
200 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
201 GLuint tile_bits
; /* hw texture tile bits used on this texture */
202 struct radeon_bo
*bo
;
204 GLuint pp_txfilter
; /* hardware register values */
206 GLuint pp_txformat_x
;
207 GLuint pp_txsize
; /* npot only */
208 GLuint pp_txpitch
; /* npot only */
209 GLuint pp_border_color
;
210 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
212 GLboolean border_fallback
;
215 static inline radeonTexObj
* radeon_tex_obj(struct gl_texture_object
*texObj
)
217 return (radeonTexObj
*)texObj
;
220 /* occlusion query */
221 struct radeon_query_object
{
222 struct gl_query_object Base
;
223 struct radeon_bo
*bo
;
225 GLboolean emitted_begin
;
227 /* Double linked list of not flushed query objects */
228 struct radeon_query_object
*prev
, *next
;
231 /* Need refcounting on dma buffers:
233 struct radeon_dma_buffer
{
234 int refcount
; /* the number of retained regions in buf */
239 struct radeon_bo
*bo
; /** Buffer object where vertex data is stored */
240 int offset
; /** Offset into buffer object, in bytes */
241 int components
; /** Number of components per vertex */
242 int stride
; /** Stride in dwords (may be 0 for repeating) */
243 int count
; /** Number of vertices */
246 #define DMA_BO_FREE_TIME 100
248 struct radeon_dma_bo
{
249 struct radeon_dma_bo
*next
, *prev
;
250 struct radeon_bo
*bo
;
255 /* Active dma region. Allocations for vertices and retained
256 * regions come from here. Also used for emitting random vertices,
257 * these may be flushed by calling flush_current();
259 struct radeon_dma_bo free
;
260 struct radeon_dma_bo wait
;
261 struct radeon_dma_bo reserved
;
262 size_t current_used
; /** Number of bytes allocated and forgotten about */
263 size_t current_vertexptr
; /** End of active vertex region */
267 * If current_vertexptr != current_used then flush must be non-zero.
268 * flush must be called before non-active vertex allocations can be
271 void (*flush
) (struct gl_context
*);
276 struct radeon_swtcl_info
{
282 /* Fallback rasterization functions
285 GLenum render_primitive
;
288 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
289 GLuint vertex_attr_count
;
291 GLuint emit_prediction
;
292 struct radeon_bo
*bo
;
295 #define RADEON_MAX_AOS_ARRAYS 16
296 struct radeon_tcl_info
{
297 struct radeon_aos aos
[RADEON_MAX_AOS_ARRAYS
];
299 struct radeon_bo
*elt_dma_bo
; /** Buffer object that contains element indices */
300 int elt_dma_offset
; /** Offset into this buffer object, in bytes */
303 struct radeon_ioctl
{
304 GLuint vertex_offset
;
306 struct radeon_bo
*bo
;
310 #define RADEON_MAX_PRIMS 64
318 static inline GLuint
radeonPackColor(GLuint cpp
,
319 GLubyte r
, GLubyte g
,
320 GLubyte b
, GLubyte a
)
324 return PACK_COLOR_565(r
, g
, b
);
326 return PACK_COLOR_8888(a
, r
, g
, b
);
332 #define MAX_CMD_BUF_SZ (16*1024)
334 #define MAX_DMA_BUF_SZ (64*1024)
336 struct radeon_store
{
339 char cmd_buf
[MAX_CMD_BUF_SZ
];
344 typedef void (*radeon_tri_func
) (radeonContextPtr
,
346 radeonVertex
*, radeonVertex
*);
348 typedef void (*radeon_line_func
) (radeonContextPtr
,
349 radeonVertex
*, radeonVertex
*);
351 typedef void (*radeon_point_func
) (radeonContextPtr
, radeonVertex
*);
353 #define RADEON_MAX_BOS 32
354 struct radeon_state
{
355 struct radeon_colorbuffer_state color
;
356 struct radeon_depthbuffer_state depth
;
357 struct radeon_scissor_state scissor
;
361 * This structure holds the command buffer while it is being constructed.
363 * The first batch of commands in the buffer is always the state that needs
364 * to be re-emitted when the context is lost. This batch can be skipped
367 struct radeon_cmdbuf
{
368 struct radeon_cs_manager
*csm
;
369 struct radeon_cs
*cs
;
370 int size
; /** # of dwords total */
371 unsigned int flushing
:1; /** whether we're currently in FlushCmdBufLocked */
374 struct radeon_context
{
375 struct gl_context glCtx
; /**< base class, must be first */
376 __DRIcontext
*driContext
; /* DRI context */
377 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
379 /* Texture object bookkeeping
382 float initialMaxAnisotropy
;
383 uint32_t texture_row_align
;
384 uint32_t texture_rect_row_align
;
385 uint32_t texture_compressed_row_align
;
387 struct radeon_dma dma
;
388 struct radeon_hw_state hw
;
389 /* Rasterization and vertex state:
394 GLbitfield64 tnl_index_bitset
; /* index of bits for last tnl_install_attrs */
396 /* Drawable information */
397 unsigned int lastStamp
;
403 drm_radeon_irq_wait_t iw
;
405 /* Derived state - for r300 only */
406 struct radeon_state state
;
408 struct radeon_swtcl_info swtcl
;
409 struct radeon_tcl_info tcl
;
410 /* Configuration cache
412 driOptionCache optionCache
;
414 struct radeon_cmdbuf cmdbuf
;
416 struct radeon_debug debug
;
418 drm_clip_rect_t fboRect
;
419 GLboolean front_cliprects
;
422 * Set if rendering has occurred to the drawable's front buffer.
424 * This is used in the DRI2 case to detect that glFlush should also copy
425 * the contents of the fake front buffer to the real front buffer.
427 GLboolean front_buffer_dirty
;
430 struct radeon_query_object
*current
;
431 struct radeon_state_atom queryobj
;
435 void (*swtcl_flush
)(struct gl_context
*ctx
, uint32_t offset
);
436 void (*pre_emit_state
)(radeonContextPtr rmesa
);
437 void (*fallback
)(struct gl_context
*ctx
, GLuint bit
, GLboolean mode
);
438 void (*free_context
)(struct gl_context
*ctx
);
439 void (*emit_query_finish
)(radeonContextPtr radeon
);
440 void (*update_scissor
)(struct gl_context
*ctx
);
441 unsigned (*check_blit
)(mesa_format mesa_format
, uint32_t dst_pitch
);
442 unsigned (*blit
)(struct gl_context
*ctx
,
443 struct radeon_bo
*src_bo
,
445 mesa_format src_mesaformat
,
449 unsigned src_x_offset
,
450 unsigned src_y_offset
,
451 struct radeon_bo
*dst_bo
,
453 mesa_format dst_mesaformat
,
457 unsigned dst_x_offset
,
458 unsigned dst_y_offset
,
462 unsigned (*is_format_renderable
)(mesa_format mesa_format
);
463 GLboolean (*revalidate_all_buffers
)(struct gl_context
*ctx
);
467 static inline radeonContextPtr
RADEON_CONTEXT(struct gl_context
*ctx
)
469 return (radeonContextPtr
) ctx
;
472 static inline __DRIdrawable
* radeon_get_drawable(radeonContextPtr radeon
)
474 return radeon
->driContext
->driDrawablePriv
;
477 static inline __DRIdrawable
* radeon_get_readable(radeonContextPtr radeon
)
479 return radeon
->driContext
->driReadablePriv
;
482 extern const char *const radeonVendorString
;
484 const char *radeonGetRendererString(radeonScreenPtr radeonScreen
);
486 GLboolean
radeonInitContext(radeonContextPtr radeon
,
488 struct dd_function_table
* functions
,
489 const struct gl_config
* glVisual
,
490 __DRIcontext
* driContextPriv
,
491 void *sharedContextPrivate
);
493 void radeonCleanupContext(radeonContextPtr radeon
);
494 GLboolean
radeonUnbindContext(__DRIcontext
* driContextPriv
);
495 void radeon_update_renderbuffers(__DRIcontext
*context
, __DRIdrawable
*drawable
,
496 GLboolean front_only
);
497 GLboolean
radeonMakeCurrent(__DRIcontext
* driContextPriv
,
498 __DRIdrawable
* driDrawPriv
,
499 __DRIdrawable
* driReadPriv
);
500 extern void radeonDestroyContext(__DRIcontext
* driContextPriv
);
501 void radeon_prepare_render(radeonContextPtr radeon
);