src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 /* This union is used to avoid warnings/miscompilation
  17    with float to uint32_t casts due to strict-aliasing */
  18 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  19
  20 struct radeon_context;
  21 typedef struct radeon_context radeonContextRec;
  22 typedef struct radeon_context *radeonContextPtr;
  23
  24
  25 #define TEX_0   0x1
  26 #define TEX_1   0x2
  27 #define TEX_2   0x4
  28 #define TEX_3   0x8
  29 #define TEX_4   0x10
  30 #define TEX_5   0x20
  31
  32 /* Rasterizing fallbacks */
  33 /* See correponding strings in r200_swtcl.c */
  34 #define RADEON_FALLBACK_TEXTURE         0x0001
  35 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  36 #define RADEON_FALLBACK_STENCIL         0x0004
  37 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  38 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  39 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  40 #define RADEON_FALLBACK_DISABLE         0x0040
  41 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  42
  43 #define R200_FALLBACK_TEXTURE           0x01
  44 #define R200_FALLBACK_DRAW_BUFFER       0x02
  45 #define R200_FALLBACK_STENCIL           0x04
  46 #define R200_FALLBACK_RENDER_MODE       0x08
  47 #define R200_FALLBACK_DISABLE           0x10
  48 #define R200_FALLBACK_BORDER_MODE       0x20
  49
  50 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  51 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  52 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  53 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  54 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  55 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  56 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  57 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  58 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  59
  60 /* The blit width for texture uploads
  61  */
  62 #define BLIT_WIDTH_BYTES 1024
  63
  64 /* Use the templated vertex format:
  65  */
  66 #define COLOR_IS_RGBA
  67 #define TAG(x) radeon##x
  68 #include "tnl_dd/t_dd_vertex.h"
  69 #undef TAG
  70
  71 struct radeon_renderbuffer
  72 {
  73         struct gl_renderbuffer base;
  74         struct radeon_bo *bo;
  75         unsigned int cpp;
  76         /* unsigned int offset; */
  77         unsigned int pitch;
  78         unsigned int width;
  79         unsigned int height;
  80
  81         /* boo Xorg 6.8.2 compat */
  82         int has_surface;
  83
  84         __DRIdrawablePrivate *dPriv;
  85 };
  86
  87 struct radeon_colorbuffer_state {
  88         GLuint clear;
  89         int roundEnable;
  90         struct radeon_renderbuffer *rrb;
  91 };
  92
  93 struct radeon_depthbuffer_state {
  94         GLuint clear;
  95         GLfloat scale;
  96         struct radeon_renderbuffer *rrb;
  97 };
  98
  99 struct radeon_scissor_state {
 100         drm_clip_rect_t rect;
 101         GLboolean enabled;
 102
 103         GLuint numClipRects;    /* Cliprects active */
 104         GLuint numAllocedClipRects;     /* Cliprects available */
 105         drm_clip_rect_t *pClipRects;
 106 };
 107
 108 struct radeon_stencilbuffer_state {
 109         GLboolean hwBuffer;
 110         GLuint clear;           /* rb3d_stencilrefmask value */
 111 };
 112
 113 struct radeon_stipple_state {
 114         GLuint mask[32];
 115 };
 116
 117 struct radeon_state_atom {
 118         struct radeon_state_atom *next, *prev;
 119         const char *name;       /* for debug */
 120         int cmd_size;           /* size in bytes */
 121         GLuint idx;
 122         GLuint is_tcl;
 123         GLuint *cmd;            /* one or more cmd's */
 124         GLuint *lastcmd;                /* one or more cmd's */
 125         GLboolean dirty;        /* dirty-mark in emit_state_list */
 126         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 127         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 128 };
 129
 130 struct radeon_hw_state {
 131         /* Head of the linked list of state atoms. */
 132         struct radeon_state_atom atomlist;
 133         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 134         GLboolean is_dirty, all_dirty;
 135 };
 136
 137
 138 /* Texture related */
 139 typedef struct _radeon_texture_image radeon_texture_image;
 140
 141 struct _radeon_texture_image {
 142         struct gl_texture_image base;
 143
 144         /**
 145          * If mt != 0, the image is stored in hardware format in the
 146          * given mipmap tree. In this case, base.Data may point into the
 147          * mapping of the buffer object that contains the mipmap tree.
 148          *
 149          * If mt == 0, the image is stored in normal memory pointed to
 150          * by base.Data.
 151          */
 152         struct _radeon_mipmap_tree *mt;
 153         struct radeon_bo *bo;
 154
 155         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 156         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 157 };
 158
 159
 160 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 161 {
 162         return (radeon_texture_image*)image;
 163 }
 164
 165
 166 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 167
 168 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 169
 170 /* Texture object in locally shared texture space.
 171  */
 172 struct radeon_tex_obj {
 173   //    driTextureObject base;
 174         struct gl_texture_object base;
 175         struct _radeon_mipmap_tree *mt;
 176
 177         /**
 178          * This is true if we've verified that the mipmap tree above is complete
 179          * and so on.
 180          */
 181         GLboolean validated;
 182
 183         GLuint override_offset;
 184         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 185         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 186         struct radeon_bo *bo;
 187
 188         GLuint bufAddr;         /* Offset to start of locally
 189                                    shared texture block */
 190
 191         GLuint dirty_state;     /* Flags (1 per texunit) for
 192                                    whether or not this texobj
 193                                    has dirty hardware state
 194                                    (pp_*) that needs to be
 195                                    brought into the
 196                                    texunit. */
 197
 198         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 199         /* Six, for the cube faces */
 200
 201
 202
 203         GLuint pp_txfilter;     /* hardware register values */
 204         GLuint pp_txformat;
 205         GLuint pp_txformat_x;
 206         GLuint pp_txoffset;     /* Image location in texmem.
 207                                    All cube faces follow. */
 208         GLuint pp_txsize;       /* npot only */
 209         GLuint pp_txpitch;      /* npot only */
 210         GLuint pp_border_color;
 211         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 212
 213         GLuint pp_txfilter_1;   /*  r300 */
 214
 215         GLboolean border_fallback;
 216
 217
 218 };
 219
 220 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 221 {
 222         return (radeonTexObj*)texObj;
 223 }
 224
 225 /* Need refcounting on dma buffers:
 226  */
 227 struct radeon_dma_buffer {
 228         int refcount;           /* the number of retained regions in buf */
 229         drmBufPtr buf;
 230 };
 231
 232 struct radeon_aos {
 233         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 234         int offset; /** Offset into buffer object, in bytes */
 235         int components; /** Number of components per vertex */
 236         int stride; /** Stride in dwords (may be 0 for repeating) */
 237         int count; /** Number of vertices */
 238 };
 239
 240 struct radeon_dma {
 241         /* Active dma region.  Allocations for vertices and retained
 242          * regions come from here.  Also used for emitting random vertices,
 243          * these may be flushed by calling flush_current();
 244          */
 245         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 246         int current_used; /** Number of bytes allocated and forgotten about */
 247         int current_vertexptr; /** End of active vertex region */
 248
 249         /**
 250          * If current_vertexptr != current_used then flush must be non-zero.
 251          * flush must be called before non-active vertex allocations can be
 252          * performed.
 253          */
 254         void (*flush) (GLcontext *);
 255
 256         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 257          * for which a DISCARD command is currently queued in the command buffer
 258 .
 259          */
 260         GLuint nr_released_bufs;
 261 };
 262
 263 /* radeon_swtcl.c
 264  */
 265 struct radeon_swtcl_info {
 266
 267         GLuint RenderIndex;
 268         GLuint vertex_size;
 269         GLubyte *verts;
 270
 271         /* Fallback rasterization functions
 272          */
 273         GLuint hw_primitive;
 274         GLenum render_primitive;
 275         GLuint numverts;
 276
 277         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 278         GLuint vertex_attr_count;
 279
 280 };
 281
 282 struct radeon_ioctl {
 283         GLuint vertex_offset;
 284         struct radeon_bo *bo;
 285         GLuint vertex_size;
 286 };
 287
 288 #define RADEON_MAX_PRIMS 64
 289
 290 struct radeon_prim {
 291         GLuint start;
 292         GLuint end;
 293         GLuint prim;
 294 };
 295
 296 static INLINE GLuint radeonPackColor(GLuint cpp,
 297                                      GLubyte r, GLubyte g,
 298                                      GLubyte b, GLubyte a)
 299 {
 300         switch (cpp) {
 301         case 2:
 302                 return PACK_COLOR_565(r, g, b);
 303         case 4:
 304                 return PACK_COLOR_8888(a, r, g, b);
 305         default:
 306                 return 0;
 307         }
 308 }
 309
 310 #define MAX_CMD_BUF_SZ (16*1024)
 311
 312 #define MAX_DMA_BUF_SZ (64*1024)
 313
 314 struct radeon_store {
 315         GLuint statenr;
 316         GLuint primnr;
 317         char cmd_buf[MAX_CMD_BUF_SZ];
 318         int cmd_used;
 319         int elts_start;
 320 };
 321
 322 struct radeon_dri_mirror {
 323         __DRIcontextPrivate *context;   /* DRI context */
 324         __DRIscreenPrivate *screen;     /* DRI screen */
 325
 326    /**
 327     * DRI drawable bound to this context for drawing.
 328     */
 329         __DRIdrawablePrivate *drawable;
 330
 331    /**
 332     * DRI drawable bound to this context for reading.
 333     */
 334         __DRIdrawablePrivate *readable;
 335
 336         drm_context_t hwContext;
 337         drm_hw_lock_t *hwLock;
 338         int fd;
 339         int drmMinor;
 340 };
 341
 342 #define DEBUG_TEXTURE   0x001
 343 #define DEBUG_STATE     0x002
 344 #define DEBUG_IOCTL     0x004
 345 #define DEBUG_PRIMS     0x008
 346 #define DEBUG_VERTS     0x010
 347 #define DEBUG_FALLBACKS 0x020
 348 #define DEBUG_VFMT      0x040
 349 #define DEBUG_CODEGEN   0x080
 350 #define DEBUG_VERBOSE   0x100
 351 #define DEBUG_DRI       0x200
 352 #define DEBUG_DMA       0x400
 353 #define DEBUG_SANITY    0x800
 354 #define DEBUG_SYNC      0x1000
 355 #define DEBUG_PIXEL     0x2000
 356 #define DEBUG_MEMORY    0x4000
 357
 358
 359
 360 typedef void (*radeon_tri_func) (radeonContextPtr,
 361                                  radeonVertex *,
 362                                  radeonVertex *, radeonVertex *);
 363
 364 typedef void (*radeon_line_func) (radeonContextPtr,
 365                                   radeonVertex *, radeonVertex *);
 366
 367 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 368
 369 struct radeon_state {
 370         struct radeon_colorbuffer_state color;
 371         struct radeon_depthbuffer_state depth;
 372         struct radeon_scissor_state scissor;
 373         struct radeon_stencilbuffer_state stencil;
 374 };
 375
 376 /**
 377  * This structure holds the command buffer while it is being constructed.
 378  *
 379  * The first batch of commands in the buffer is always the state that needs
 380  * to be re-emitted when the context is lost. This batch can be skipped
 381  * otherwise.
 382  */
 383 struct radeon_cmdbuf {
 384         struct radeon_cs_manager    *csm;
 385         struct radeon_cs            *cs;
 386         int size; /** # of dwords total */
 387         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 388 };
 389
 390 struct radeon_context {
 391    GLcontext *glCtx;
 392    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 393
 394    /* Texture object bookkeeping
 395     */
 396    unsigned              nr_heaps;
 397    driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
 398    driTextureObject      swapped;
 399    int                   texture_depth;
 400    float                 initialMaxAnisotropy;
 401
 402   struct radeon_dma dma;
 403   struct radeon_hw_state hw;
 404    /* Rasterization and vertex state:
 405     */
 406    GLuint TclFallback;
 407    GLuint Fallback;
 408    GLuint NewGLState;
 409    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 410
 411    /* Page flipping */
 412    GLuint doPageFlip;
 413
 414    /* Drawable, cliprect and scissor information */
 415    GLuint numClipRects; /* Cliprects for the draw buffer */
 416    drm_clip_rect_t *pClipRects;
 417    unsigned int lastStamp;
 418    GLboolean lost_context;
 419    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 420
 421    /* Mirrors of some DRI state */
 422    struct radeon_dri_mirror dri;
 423
 424    /* Busy waiting */
 425    GLuint do_usleeps;
 426    GLuint do_irqs;
 427    GLuint irqsEmitted;
 428    drm_radeon_irq_wait_t iw;
 429
 430    /* buffer swap */
 431    int64_t swap_ust;
 432    int64_t swap_missed_ust;
 433
 434    GLuint swap_count;
 435    GLuint swap_missed_count;
 436
 437    /* Derived state - for r300 only */
 438    struct radeon_state state;
 439
 440    struct radeon_swtcl_info swtcl;
 441    /* Configuration cache
 442     */
 443    driOptionCache optionCache;
 444
 445    struct radeon_cmdbuf cmdbuf;
 446
 447    struct {
 448            void (*get_lock)(radeonContextPtr radeon);
 449            void (*update_viewport_offset)(GLcontext *ctx);
 450            void (*update_draw_buffer)(GLcontext *ctx);
 451            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 452            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 453            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 454            void (*pre_emit_state)(radeonContextPtr rmesa);
 455    } vtbl;
 456 };
 457
 458 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 459
 460 /**
 461  * This function takes a float and packs it into a uint32_t
 462  */
 463 static INLINE uint32_t radeonPackFloat32(float fl)
 464 {
 465         union {
 466                 float fl;
 467                 uint32_t u;
 468         } u;
 469
 470         u.fl = fl;
 471         return u.u;
 472 }
 473
 474 /* This is probably wrong for some values, I need to test this
 475  * some more.  Range checking would be a good idea also..
 476  *
 477  * But it works for most things.  I'll fix it later if someone
 478  * else with a better clue doesn't
 479  */
 480 static INLINE uint32_t radeonPackFloat24(float f)
 481 {
 482         float mantissa;
 483         int exponent;
 484         uint32_t float24 = 0;
 485
 486         if (f == 0.0)
 487                 return 0;
 488
 489         mantissa = frexpf(f, &exponent);
 490
 491         /* Handle -ve */
 492         if (mantissa < 0) {
 493                 float24 |= (1 << 23);
 494                 mantissa = mantissa * -1.0;
 495         }
 496         /* Handle exponent, bias of 63 */
 497         exponent += 62;
 498         float24 |= (exponent << 16);
 499         /* Kill 7 LSB of mantissa */
 500         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 501
 502         return float24;
 503 }
 504
 505 GLboolean radeonInitContext(radeonContextPtr radeon,
 506                             struct dd_function_table* functions,
 507                             const __GLcontextModes * glVisual,
 508                             __DRIcontextPrivate * driContextPriv,
 509                             void *sharedContextPrivate);
 510
 511 void radeonCleanupContext(radeonContextPtr radeon);
 512 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 513 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 514 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 515                             __DRIdrawablePrivate * driDrawPriv,
 516                             __DRIdrawablePrivate * driReadPriv);
 517
 518 /* ================================================================
 519  * Debugging:
 520  */
 521 #define DO_DEBUG                1
 522
 523 #if DO_DEBUG
 524 extern int RADEON_DEBUG;
 525 #else
 526 #define RADEON_DEBUG            0
 527 #endif
 528
 529 #endif