src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 /* This union is used to avoid warnings/miscompilation
  17    with float to uint32_t casts due to strict-aliasing */
  18 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  19
  20 struct radeon_context;
  21 typedef struct radeon_context radeonContextRec;
  22 typedef struct radeon_context *radeonContextPtr;
  23
  24
  25 #define TEX_0   0x1
  26 #define TEX_1   0x2
  27 #define TEX_2   0x4
  28 #define TEX_3   0x8
  29 #define TEX_4   0x10
  30 #define TEX_5   0x20
  31
  32 /* Rasterizing fallbacks */
  33 /* See correponding strings in r200_swtcl.c */
  34 #define RADEON_FALLBACK_TEXTURE         0x0001
  35 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  36 #define RADEON_FALLBACK_STENCIL         0x0004
  37 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  38 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  39 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  40 #define RADEON_FALLBACK_DISABLE         0x0040
  41 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  42 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  43 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  44
  45 #define R200_FALLBACK_TEXTURE           0x01
  46 #define R200_FALLBACK_DRAW_BUFFER       0x02
  47 #define R200_FALLBACK_STENCIL           0x04
  48 #define R200_FALLBACK_RENDER_MODE       0x08
  49 #define R200_FALLBACK_DISABLE           0x10
  50 #define R200_FALLBACK_BORDER_MODE       0x20
  51
  52 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  53 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  54 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  55 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  56 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  57 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  58 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  59 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  60 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  61
  62 /* The blit width for texture uploads
  63  */
  64 #define BLIT_WIDTH_BYTES 1024
  65
  66 /* Use the templated vertex format:
  67  */
  68 #define COLOR_IS_RGBA
  69 #define TAG(x) radeon##x
  70 #include "tnl_dd/t_dd_vertex.h"
  71 #undef TAG
  72
  73 #define RADEON_RB_CLASS 0xdeadbeef
  74
  75 struct radeon_renderbuffer
  76 {
  77         struct gl_renderbuffer base;
  78         struct radeon_bo *bo;
  79         unsigned int cpp;
  80         /* unsigned int offset; */
  81         unsigned int pitch;
  82         unsigned int width;
  83         unsigned int height;
  84
  85         /* boo Xorg 6.8.2 compat */
  86         int has_surface;
  87
  88         GLuint pf_pending;  /**< sequence number of pending flip */
  89         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  90         __DRIdrawablePrivate *dPriv;
  91 };
  92
  93 struct radeon_framebuffer
  94 {
  95         struct gl_framebuffer base;
  96
  97         struct radeon_renderbuffer *color_rb[2];
  98
  99         GLuint vbl_waited;
 100
 101         /* buffer swap */
 102         int64_t swap_ust;
 103         int64_t swap_missed_ust;
 104
 105         GLuint swap_count;
 106         GLuint swap_missed_count;
 107
 108         /* Drawable page flipping state */
 109         GLboolean pf_active;
 110         GLint pf_current_page;
 111         GLint pf_num_pages;
 112
 113 };
 114
 115
 116 struct radeon_colorbuffer_state {
 117         GLuint clear;
 118         int roundEnable;
 119         struct radeon_renderbuffer *rrb;
 120 };
 121
 122 struct radeon_depthbuffer_state {
 123         GLuint clear;
 124         GLfloat scale;
 125         struct radeon_renderbuffer *rrb;
 126 };
 127
 128 struct radeon_scissor_state {
 129         drm_clip_rect_t rect;
 130         GLboolean enabled;
 131
 132         GLuint numClipRects;    /* Cliprects active */
 133         GLuint numAllocedClipRects;     /* Cliprects available */
 134         drm_clip_rect_t *pClipRects;
 135 };
 136
 137 struct radeon_stencilbuffer_state {
 138         GLboolean hwBuffer;
 139         GLuint clear;           /* rb3d_stencilrefmask value */
 140 };
 141
 142 struct radeon_stipple_state {
 143         GLuint mask[32];
 144 };
 145
 146 struct radeon_state_atom {
 147         struct radeon_state_atom *next, *prev;
 148         const char *name;       /* for debug */
 149         int cmd_size;           /* size in bytes */
 150         GLuint idx;
 151         GLuint is_tcl;
 152         GLuint *cmd;            /* one or more cmd's */
 153         GLuint *lastcmd;                /* one or more cmd's */
 154         GLboolean dirty;        /* dirty-mark in emit_state_list */
 155         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 156         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 157 };
 158
 159 struct radeon_hw_state {
 160         /* Head of the linked list of state atoms. */
 161         struct radeon_state_atom atomlist;
 162         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 163         GLboolean is_dirty, all_dirty;
 164 };
 165
 166
 167 /* Texture related */
 168 typedef struct _radeon_texture_image radeon_texture_image;
 169
 170 struct _radeon_texture_image {
 171         struct gl_texture_image base;
 172
 173         /**
 174          * If mt != 0, the image is stored in hardware format in the
 175          * given mipmap tree. In this case, base.Data may point into the
 176          * mapping of the buffer object that contains the mipmap tree.
 177          *
 178          * If mt == 0, the image is stored in normal memory pointed to
 179          * by base.Data.
 180          */
 181         struct _radeon_mipmap_tree *mt;
 182         struct radeon_bo *bo;
 183
 184         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 185         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 186 };
 187
 188
 189 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 190 {
 191         return (radeon_texture_image*)image;
 192 }
 193
 194
 195 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 196
 197 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 198
 199 /* Texture object in locally shared texture space.
 200  */
 201 struct radeon_tex_obj {
 202         struct gl_texture_object base;
 203         struct _radeon_mipmap_tree *mt;
 204
 205         /**
 206          * This is true if we've verified that the mipmap tree above is complete
 207          * and so on.
 208          */
 209         GLboolean validated;
 210
 211         GLuint override_offset;
 212         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 213         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 214         struct radeon_bo *bo;
 215
 216         GLuint pp_txfilter;     /* hardware register values */
 217         GLuint pp_txformat;
 218         GLuint pp_txformat_x;
 219         GLuint pp_txsize;       /* npot only */
 220         GLuint pp_txpitch;      /* npot only */
 221         GLuint pp_border_color;
 222         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 223
 224         GLuint pp_txfilter_1;   /*  r300 */
 225
 226         GLboolean border_fallback;
 227
 228
 229 };
 230
 231 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 232 {
 233         return (radeonTexObj*)texObj;
 234 }
 235
 236 /* Need refcounting on dma buffers:
 237  */
 238 struct radeon_dma_buffer {
 239         int refcount;           /* the number of retained regions in buf */
 240         drmBufPtr buf;
 241 };
 242
 243 struct radeon_aos {
 244         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 245         int offset; /** Offset into buffer object, in bytes */
 246         int components; /** Number of components per vertex */
 247         int stride; /** Stride in dwords (may be 0 for repeating) */
 248         int count; /** Number of vertices */
 249 };
 250
 251 struct radeon_dma {
 252         /* Active dma region.  Allocations for vertices and retained
 253          * regions come from here.  Also used for emitting random vertices,
 254          * these may be flushed by calling flush_current();
 255          */
 256         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 257         int current_used; /** Number of bytes allocated and forgotten about */
 258         int current_vertexptr; /** End of active vertex region */
 259
 260         /**
 261          * If current_vertexptr != current_used then flush must be non-zero.
 262          * flush must be called before non-active vertex allocations can be
 263          * performed.
 264          */
 265         void (*flush) (GLcontext *);
 266
 267         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 268          * for which a DISCARD command is currently queued in the command buffer
 269 .
 270          */
 271         GLuint nr_released_bufs;
 272 };
 273
 274 /* radeon_swtcl.c
 275  */
 276 struct radeon_swtcl_info {
 277
 278         GLuint RenderIndex;
 279         GLuint vertex_size;
 280         GLubyte *verts;
 281
 282         /* Fallback rasterization functions
 283          */
 284         GLuint hw_primitive;
 285         GLenum render_primitive;
 286         GLuint numverts;
 287
 288         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 289         GLuint vertex_attr_count;
 290
 291 };
 292
 293 struct radeon_ioctl {
 294         GLuint vertex_offset;
 295         struct radeon_bo *bo;
 296         GLuint vertex_size;
 297 };
 298
 299 #define RADEON_MAX_PRIMS 64
 300
 301 struct radeon_prim {
 302         GLuint start;
 303         GLuint end;
 304         GLuint prim;
 305 };
 306
 307 static INLINE GLuint radeonPackColor(GLuint cpp,
 308                                      GLubyte r, GLubyte g,
 309                                      GLubyte b, GLubyte a)
 310 {
 311         switch (cpp) {
 312         case 2:
 313                 return PACK_COLOR_565(r, g, b);
 314         case 4:
 315                 return PACK_COLOR_8888(a, r, g, b);
 316         default:
 317                 return 0;
 318         }
 319 }
 320
 321 #define MAX_CMD_BUF_SZ (16*1024)
 322
 323 #define MAX_DMA_BUF_SZ (64*1024)
 324
 325 struct radeon_store {
 326         GLuint statenr;
 327         GLuint primnr;
 328         char cmd_buf[MAX_CMD_BUF_SZ];
 329         int cmd_used;
 330         int elts_start;
 331 };
 332
 333 struct radeon_dri_mirror {
 334         __DRIcontextPrivate *context;   /* DRI context */
 335         __DRIscreenPrivate *screen;     /* DRI screen */
 336
 337    /**
 338     * DRI drawable bound to this context for drawing.
 339     */
 340         __DRIdrawablePrivate *drawable;
 341
 342    /**
 343     * DRI drawable bound to this context for reading.
 344     */
 345         __DRIdrawablePrivate *readable;
 346
 347         drm_context_t hwContext;
 348         drm_hw_lock_t *hwLock;
 349         int fd;
 350         int drmMinor;
 351 };
 352
 353 #define DEBUG_TEXTURE   0x001
 354 #define DEBUG_STATE     0x002
 355 #define DEBUG_IOCTL     0x004
 356 #define DEBUG_PRIMS     0x008
 357 #define DEBUG_VERTS     0x010
 358 #define DEBUG_FALLBACKS 0x020
 359 #define DEBUG_VFMT      0x040
 360 #define DEBUG_CODEGEN   0x080
 361 #define DEBUG_VERBOSE   0x100
 362 #define DEBUG_DRI       0x200
 363 #define DEBUG_DMA       0x400
 364 #define DEBUG_SANITY    0x800
 365 #define DEBUG_SYNC      0x1000
 366 #define DEBUG_PIXEL     0x2000
 367 #define DEBUG_MEMORY    0x4000
 368
 369
 370
 371 typedef void (*radeon_tri_func) (radeonContextPtr,
 372                                  radeonVertex *,
 373                                  radeonVertex *, radeonVertex *);
 374
 375 typedef void (*radeon_line_func) (radeonContextPtr,
 376                                   radeonVertex *, radeonVertex *);
 377
 378 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 379
 380 struct radeon_state {
 381         struct radeon_colorbuffer_state color;
 382         struct radeon_depthbuffer_state depth;
 383         struct radeon_scissor_state scissor;
 384         struct radeon_stencilbuffer_state stencil;
 385 };
 386
 387 /**
 388  * This structure holds the command buffer while it is being constructed.
 389  *
 390  * The first batch of commands in the buffer is always the state that needs
 391  * to be re-emitted when the context is lost. This batch can be skipped
 392  * otherwise.
 393  */
 394 struct radeon_cmdbuf {
 395         struct radeon_cs_manager    *csm;
 396         struct radeon_cs            *cs;
 397         int size; /** # of dwords total */
 398         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 399 };
 400
 401 struct radeon_context {
 402    GLcontext *glCtx;
 403    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 404
 405    /* Texture object bookkeeping
 406     */
 407    int                   texture_depth;
 408    float                 initialMaxAnisotropy;
 409
 410   struct radeon_dma dma;
 411   struct radeon_hw_state hw;
 412    /* Rasterization and vertex state:
 413     */
 414    GLuint TclFallback;
 415    GLuint Fallback;
 416    GLuint NewGLState;
 417    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 418
 419    /* Drawable, cliprect and scissor information */
 420    GLuint numClipRects; /* Cliprects for the draw buffer */
 421    drm_clip_rect_t *pClipRects;
 422    unsigned int lastStamp;
 423    GLboolean lost_context;
 424    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 425
 426    /* Mirrors of some DRI state */
 427    struct radeon_dri_mirror dri;
 428
 429    /* Busy waiting */
 430    GLuint do_usleeps;
 431    GLuint do_irqs;
 432    GLuint irqsEmitted;
 433    drm_radeon_irq_wait_t iw;
 434
 435    /* Derived state - for r300 only */
 436    struct radeon_state state;
 437
 438    struct radeon_swtcl_info swtcl;
 439    /* Configuration cache
 440     */
 441    driOptionCache optionCache;
 442
 443    struct radeon_cmdbuf cmdbuf;
 444
 445         drm_clip_rect_t fboRect;
 446         GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 447         GLboolean front_cliprects;
 448
 449    struct {
 450            void (*get_lock)(radeonContextPtr radeon);
 451            void (*update_viewport_offset)(GLcontext *ctx);
 452            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 453            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 454            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 455            void (*pre_emit_state)(radeonContextPtr rmesa);
 456            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 457    } vtbl;
 458 };
 459
 460 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 461
 462 /**
 463  * This function takes a float and packs it into a uint32_t
 464  */
 465 static INLINE uint32_t radeonPackFloat32(float fl)
 466 {
 467         union {
 468                 float fl;
 469                 uint32_t u;
 470         } u;
 471
 472         u.fl = fl;
 473         return u.u;
 474 }
 475
 476 /* This is probably wrong for some values, I need to test this
 477  * some more.  Range checking would be a good idea also..
 478  *
 479  * But it works for most things.  I'll fix it later if someone
 480  * else with a better clue doesn't
 481  */
 482 static INLINE uint32_t radeonPackFloat24(float f)
 483 {
 484         float mantissa;
 485         int exponent;
 486         uint32_t float24 = 0;
 487
 488         if (f == 0.0)
 489                 return 0;
 490
 491         mantissa = frexpf(f, &exponent);
 492
 493         /* Handle -ve */
 494         if (mantissa < 0) {
 495                 float24 |= (1 << 23);
 496                 mantissa = mantissa * -1.0;
 497         }
 498         /* Handle exponent, bias of 63 */
 499         exponent += 62;
 500         float24 |= (exponent << 16);
 501         /* Kill 7 LSB of mantissa */
 502         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 503
 504         return float24;
 505 }
 506
 507 GLboolean radeonInitContext(radeonContextPtr radeon,
 508                             struct dd_function_table* functions,
 509                             const __GLcontextModes * glVisual,
 510                             __DRIcontextPrivate * driContextPriv,
 511                             void *sharedContextPrivate);
 512
 513 void radeonCleanupContext(radeonContextPtr radeon);
 514 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 515 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 516 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 517                             __DRIdrawablePrivate * driDrawPriv,
 518                             __DRIdrawablePrivate * driReadPriv);
 519
 520 /* ================================================================
 521  * Debugging:
 522  */
 523 #define DO_DEBUG                1
 524
 525 #if DO_DEBUG
 526 extern int RADEON_DEBUG;
 527 #else
 528 #define RADEON_DEBUG            0
 529 #endif
 530
 531 #endif