src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_debug.h"
  12 #include "radeon_screen.h"
  13 #include "radeon_drm.h"
  14 #include "dri_util.h"
  15 #include "tnl/t_vertex.h"
  16
  17 #include "dri_metaops.h"
  18 struct radeon_context;
  19
  20 #include "radeon_bocs_wrapper.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct gl_renderbuffer base;
  84         struct radeon_bo *bo;
  85         unsigned int cpp;
  86         /* unsigned int offset; */
  87         unsigned int pitch;
  88
  89         uint32_t draw_offset; /* FBO */
  90         /* boo Xorg 6.8.2 compat */
  91         int has_surface;
  92
  93         GLuint pf_pending;  /**< sequence number of pending flip */
  94         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  95         __DRIdrawable *dPriv;
  96
  97         /* r6xx+ tiling */
  98         GLuint tile_config;
  99         GLint group_bytes;
 100         GLint num_channels;
 101         GLint num_banks;
 102         GLint r7xx_bank_op;
 103 };
 104
 105 struct radeon_framebuffer
 106 {
 107         struct gl_framebuffer base;
 108
 109         struct radeon_renderbuffer *color_rb[2];
 110
 111         GLuint vbl_waited;
 112
 113         /* buffer swap */
 114         int64_t swap_ust;
 115         int64_t swap_missed_ust;
 116
 117         GLuint swap_count;
 118         GLuint swap_missed_count;
 119
 120         /* Drawable page flipping state */
 121         GLboolean pf_active;
 122         GLint pf_current_page;
 123         GLint pf_num_pages;
 124
 125 };
 126
 127
 128 struct radeon_colorbuffer_state {
 129         GLuint clear;
 130         int roundEnable;
 131         struct gl_renderbuffer *rb;
 132         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 133 };
 134
 135 struct radeon_depthbuffer_state {
 136         GLuint clear;
 137         struct gl_renderbuffer *rb;
 138 };
 139
 140 struct radeon_scissor_state {
 141         drm_clip_rect_t rect;
 142         GLboolean enabled;
 143
 144         GLuint numClipRects;    /* Cliprects active */
 145         GLuint numAllocedClipRects;     /* Cliprects available */
 146         drm_clip_rect_t *pClipRects;
 147 };
 148
 149 struct radeon_stencilbuffer_state {
 150         GLuint clear;           /* rb3d_stencilrefmask value */
 151 };
 152
 153 struct radeon_state_atom {
 154         struct radeon_state_atom *next, *prev;
 155         const char *name;       /* for debug */
 156         int cmd_size;           /* size in bytes */
 157         GLuint idx;
 158         GLuint is_tcl;
 159         GLuint *cmd;            /* one or more cmd's */
 160         GLuint *lastcmd;                /* one or more cmd's */
 161         GLboolean dirty;        /* dirty-mark in emit_state_list */
 162         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 163         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 164 };
 165
 166 struct radeon_hw_state {
 167         /* Head of the linked list of state atoms. */
 168         struct radeon_state_atom atomlist;
 169         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 170         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 171         GLboolean is_dirty, all_dirty;
 172 };
 173
 174
 175 /* Texture related */
 176 typedef struct _radeon_texture_image radeon_texture_image;
 177
 178 struct _radeon_texture_image {
 179         struct gl_texture_image base;
 180
 181         /**
 182          * If mt != 0, the image is stored in hardware format in the
 183          * given mipmap tree. In this case, base.Data may point into the
 184          * mapping of the buffer object that contains the mipmap tree.
 185          *
 186          * If mt == 0, the image is stored in normal memory pointed to
 187          * by base.Data.
 188          */
 189         struct _radeon_mipmap_tree *mt;
 190         struct radeon_bo *bo;
 191
 192         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 193         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 194 };
 195
 196
 197 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 198 {
 199         return (radeon_texture_image*)image;
 200 }
 201
 202
 203 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 204
 205 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 206
 207 /* Texture object in locally shared texture space.
 208  */
 209 struct radeon_tex_obj {
 210         struct gl_texture_object base;
 211         struct _radeon_mipmap_tree *mt;
 212
 213         /**
 214          * This is true if we've verified that the mipmap tree above is complete
 215          * and so on.
 216          */
 217         GLboolean validated;
 218         /* Minimum LOD to be used during rendering */
 219         unsigned minLod;
 220         /* Miximum LOD to be used during rendering */
 221         unsigned maxLod;
 222
 223         GLuint override_offset;
 224         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 225         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 226         struct radeon_bo *bo;
 227
 228         GLuint pp_txfilter;     /* hardware register values */
 229         GLuint pp_txformat;
 230         GLuint pp_txformat_x;
 231         GLuint pp_txsize;       /* npot only */
 232         GLuint pp_txpitch;      /* npot only */
 233         GLuint pp_border_color;
 234         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 235
 236         GLuint pp_txfilter_1;   /*  r300 */
 237
 238         /* r700 texture states */
 239         GLuint SQ_TEX_RESOURCE0;
 240         GLuint SQ_TEX_RESOURCE1;
 241         GLuint SQ_TEX_RESOURCE2;
 242         GLuint SQ_TEX_RESOURCE3;
 243         GLuint SQ_TEX_RESOURCE4;
 244         GLuint SQ_TEX_RESOURCE5;
 245         GLuint SQ_TEX_RESOURCE6;
 246
 247         GLuint SQ_TEX_SAMPLER0;
 248         GLuint SQ_TEX_SAMPLER1;
 249         GLuint SQ_TEX_SAMPLER2;
 250
 251         GLuint TD_PS_SAMPLER0_BORDER_RED;
 252         GLuint TD_PS_SAMPLER0_BORDER_GREEN;
 253         GLuint TD_PS_SAMPLER0_BORDER_BLUE;
 254         GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
 255
 256         GLboolean border_fallback;
 257
 258
 259 };
 260
 261 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 262 {
 263         return (radeonTexObj*)texObj;
 264 }
 265
 266 /* occlusion query */
 267 struct radeon_query_object {
 268         struct gl_query_object Base;
 269         struct radeon_bo *bo;
 270         int curr_offset;
 271         GLboolean emitted_begin;
 272
 273         /* Double linked list of not flushed query objects */
 274         struct radeon_query_object *prev, *next;
 275 };
 276
 277 /* Need refcounting on dma buffers:
 278  */
 279 struct radeon_dma_buffer {
 280         int refcount;           /* the number of retained regions in buf */
 281         drmBufPtr buf;
 282 };
 283
 284 struct radeon_aos {
 285         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 286         int offset; /** Offset into buffer object, in bytes */
 287         int components; /** Number of components per vertex */
 288         int stride; /** Stride in dwords (may be 0 for repeating) */
 289         int count; /** Number of vertices */
 290 };
 291
 292 #define DMA_BO_FREE_TIME 100
 293
 294 struct radeon_dma_bo {
 295   struct radeon_dma_bo *next, *prev;
 296   struct radeon_bo *bo;
 297   int expire_counter;
 298 };
 299
 300 struct radeon_dma {
 301         /* Active dma region.  Allocations for vertices and retained
 302          * regions come from here.  Also used for emitting random vertices,
 303          * these may be flushed by calling flush_current();
 304          */
 305         struct radeon_dma_bo free;
 306         struct radeon_dma_bo wait;
 307         struct radeon_dma_bo reserved;
 308         size_t current_used; /** Number of bytes allocated and forgotten about */
 309         size_t current_vertexptr; /** End of active vertex region */
 310         size_t minimum_size;
 311
 312         /**
 313          * If current_vertexptr != current_used then flush must be non-zero.
 314          * flush must be called before non-active vertex allocations can be
 315          * performed.
 316          */
 317         void (*flush) (GLcontext *);
 318 };
 319
 320 /* radeon_swtcl.c
 321  */
 322 struct radeon_swtcl_info {
 323
 324         GLuint RenderIndex;
 325         GLuint vertex_size;
 326         GLubyte *verts;
 327
 328         /* Fallback rasterization functions
 329          */
 330         GLuint hw_primitive;
 331         GLenum render_primitive;
 332         GLuint numverts;
 333
 334         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 335         GLuint vertex_attr_count;
 336
 337         GLuint emit_prediction;
 338         struct radeon_bo *bo;
 339 };
 340
 341 #define RADEON_MAX_AOS_ARRAYS           16
 342 struct radeon_tcl_info {
 343         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 344         GLuint aos_count;
 345         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 346         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 347 };
 348
 349 struct radeon_ioctl {
 350         GLuint vertex_offset;
 351         GLuint vertex_max;
 352         struct radeon_bo *bo;
 353         GLuint vertex_size;
 354 };
 355
 356 #define RADEON_MAX_PRIMS 64
 357
 358 struct radeon_prim {
 359         GLuint start;
 360         GLuint end;
 361         GLuint prim;
 362 };
 363
 364 static INLINE GLuint radeonPackColor(GLuint cpp,
 365                                      GLubyte r, GLubyte g,
 366                                      GLubyte b, GLubyte a)
 367 {
 368         switch (cpp) {
 369         case 2:
 370                 return PACK_COLOR_565(r, g, b);
 371         case 4:
 372                 return PACK_COLOR_8888(a, r, g, b);
 373         default:
 374                 return 0;
 375         }
 376 }
 377
 378 #define MAX_CMD_BUF_SZ (16*1024)
 379
 380 #define MAX_DMA_BUF_SZ (64*1024)
 381
 382 struct radeon_store {
 383         GLuint statenr;
 384         GLuint primnr;
 385         char cmd_buf[MAX_CMD_BUF_SZ];
 386         int cmd_used;
 387         int elts_start;
 388 };
 389
 390 struct radeon_dri_mirror {
 391         __DRIcontext *context;  /* DRI context */
 392         __DRIscreen *screen;    /* DRI screen */
 393
 394         drm_context_t hwContext;
 395         drm_hw_lock_t *hwLock;
 396         int hwLockCount;
 397         int fd;
 398         int drmMinor;
 399 };
 400
 401 typedef void (*radeon_tri_func) (radeonContextPtr,
 402                                  radeonVertex *,
 403                                  radeonVertex *, radeonVertex *);
 404
 405 typedef void (*radeon_line_func) (radeonContextPtr,
 406                                   radeonVertex *, radeonVertex *);
 407
 408 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 409
 410 #define RADEON_MAX_BOS 32
 411 struct radeon_state {
 412         struct radeon_colorbuffer_state color;
 413         struct radeon_depthbuffer_state depth;
 414         struct radeon_scissor_state scissor;
 415         struct radeon_stencilbuffer_state stencil;
 416 };
 417
 418 /**
 419  * This structure holds the command buffer while it is being constructed.
 420  *
 421  * The first batch of commands in the buffer is always the state that needs
 422  * to be re-emitted when the context is lost. This batch can be skipped
 423  * otherwise.
 424  */
 425 struct radeon_cmdbuf {
 426         struct radeon_cs_manager    *csm;
 427         struct radeon_cs            *cs;
 428         int size; /** # of dwords total */
 429         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 430 };
 431
 432 struct radeon_context {
 433    GLcontext *glCtx;
 434    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 435
 436    /* Texture object bookkeeping
 437     */
 438    int                   texture_depth;
 439    float                 initialMaxAnisotropy;
 440    uint32_t              texture_row_align;
 441    uint32_t              texture_rect_row_align;
 442    uint32_t              texture_compressed_row_align;
 443
 444   struct radeon_dma dma;
 445   struct radeon_hw_state hw;
 446    /* Rasterization and vertex state:
 447     */
 448    GLuint TclFallback;
 449    GLuint Fallback;
 450    GLuint NewGLState;
 451    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 452
 453    /* Drawable, cliprect and scissor information */
 454    GLuint numClipRects; /* Cliprects for the draw buffer */
 455    drm_clip_rect_t *pClipRects;
 456    unsigned int lastStamp;
 457    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 458
 459    /* Mirrors of some DRI state */
 460    struct radeon_dri_mirror dri;
 461
 462    /* Busy waiting */
 463    GLuint do_usleeps;
 464    GLuint do_irqs;
 465    GLuint irqsEmitted;
 466    drm_radeon_irq_wait_t iw;
 467
 468    /* Derived state - for r300 only */
 469    struct radeon_state state;
 470
 471    struct radeon_swtcl_info swtcl;
 472    struct radeon_tcl_info tcl;
 473    /* Configuration cache
 474     */
 475    driOptionCache optionCache;
 476
 477    struct radeon_cmdbuf cmdbuf;
 478
 479    struct radeon_debug debug;
 480
 481   drm_clip_rect_t fboRect;
 482   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 483   GLboolean front_cliprects;
 484
 485    /**
 486     * Set if rendering has occured to the drawable's front buffer.
 487     *
 488     * This is used in the DRI2 case to detect that glFlush should also copy
 489     * the contents of the fake front buffer to the real front buffer.
 490     */
 491    GLboolean front_buffer_dirty;
 492
 493    /**
 494     * Track whether front-buffer rendering is currently enabled
 495     *
 496     * A separate flag is used to track this in order to support MRT more
 497     * easily.
 498     */
 499    GLboolean is_front_buffer_rendering;
 500
 501    /**
 502     * Track whether front-buffer is the current read target.
 503     *
 504     * This is closely associated with is_front_buffer_rendering, but may
 505     * be set separately.  The DRI2 fake front buffer must be referenced
 506     * either way.
 507     */
 508    GLboolean is_front_buffer_reading;
 509
 510    struct dri_metaops meta;
 511
 512    struct {
 513         struct radeon_query_object *current;
 514         struct radeon_state_atom queryobj;
 515    } query;
 516
 517    struct {
 518            void (*get_lock)(radeonContextPtr radeon);
 519            void (*update_viewport_offset)(GLcontext *ctx);
 520            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 521            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 522            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 523            void (*pre_emit_state)(radeonContextPtr rmesa);
 524            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 525            void (*free_context)(GLcontext *ctx);
 526            void (*emit_query_finish)(radeonContextPtr radeon);
 527            void (*update_scissor)(GLcontext *ctx);
 528            unsigned (*check_blit)(gl_format mesa_format);
 529            unsigned (*blit)(GLcontext *ctx,
 530                         struct radeon_bo *src_bo,
 531                         intptr_t src_offset,
 532                         gl_format src_mesaformat,
 533                         unsigned src_pitch,
 534                         unsigned src_width,
 535                         unsigned src_height,
 536                         unsigned src_x_offset,
 537                         unsigned src_y_offset,
 538                         struct radeon_bo *dst_bo,
 539                         intptr_t dst_offset,
 540                         gl_format dst_mesaformat,
 541                         unsigned dst_pitch,
 542                         unsigned dst_width,
 543                         unsigned dst_height,
 544                         unsigned dst_x_offset,
 545                         unsigned dst_y_offset,
 546                         unsigned reg_width,
 547                         unsigned reg_height,
 548                         unsigned flip_y);
 549            unsigned (*is_format_renderable)(gl_format mesa_format);
 550    } vtbl;
 551 };
 552
 553 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 554
 555 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 556 {
 557         return radeon->dri.context->driDrawablePriv;
 558 }
 559
 560 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 561 {
 562         return radeon->dri.context->driReadablePriv;
 563 }
 564
 565 /**
 566  * This function takes a float and packs it into a uint32_t
 567  */
 568 static INLINE uint32_t radeonPackFloat32(float fl)
 569 {
 570         union {
 571                 float fl;
 572                 uint32_t u;
 573         } u;
 574
 575         u.fl = fl;
 576         return u.u;
 577 }
 578
 579 /* This is probably wrong for some values, I need to test this
 580  * some more.  Range checking would be a good idea also..
 581  *
 582  * But it works for most things.  I'll fix it later if someone
 583  * else with a better clue doesn't
 584  */
 585 static INLINE uint32_t radeonPackFloat24(float f)
 586 {
 587         float mantissa;
 588         int exponent;
 589         uint32_t float24 = 0;
 590
 591         if (f == 0.0)
 592                 return 0;
 593
 594         mantissa = frexpf(f, &exponent);
 595
 596         /* Handle -ve */
 597         if (mantissa < 0) {
 598                 float24 |= (1 << 23);
 599                 mantissa = mantissa * -1.0;
 600         }
 601         /* Handle exponent, bias of 63 */
 602         exponent += 62;
 603         float24 |= (exponent << 16);
 604         /* Kill 7 LSB of mantissa */
 605         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 606
 607         return float24;
 608 }
 609
 610 GLboolean radeonInitContext(radeonContextPtr radeon,
 611                             struct dd_function_table* functions,
 612                             const __GLcontextModes * glVisual,
 613                             __DRIcontext * driContextPriv,
 614                             void *sharedContextPrivate);
 615
 616 void radeonCleanupContext(radeonContextPtr radeon);
 617 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 618 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 619                                  GLboolean front_only);
 620 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 621                             __DRIdrawable * driDrawPriv,
 622                             __DRIdrawable * driReadPriv);
 623 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 624 void radeon_prepare_render(radeonContextPtr radeon);
 625
 626 #endif