src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "tnl/t_context.h"
   8 #include "main/colormac.h"
   9
  10 #include "radeon_debug.h"
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15 #include "swrast/s_context.h"
  16
  17 struct radeon_context;
  18
  19 #include "radeon_bo_gem.h"
  20 #include "radeon_cs_gem.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct gl_renderbuffer base;
  84         struct radeon_bo *bo;
  85         unsigned int cpp;
  86         /* unsigned int offset; */
  87         unsigned int pitch;
  88
  89         struct radeon_bo *map_bo;
  90         GLbitfield map_mode;
  91         int map_x, map_y, map_w, map_h;
  92
  93         uint32_t draw_offset; /* FBO */
  94         /* boo Xorg 6.8.2 compat */
  95         int has_surface;
  96
  97         GLuint pf_pending;  /**< sequence number of pending flip */
  98         __DRIdrawable *dPriv;
  99 };
 100
 101 struct radeon_framebuffer
 102 {
 103         struct gl_framebuffer base;
 104
 105         struct radeon_renderbuffer *color_rb[2];
 106 };
 107
 108
 109 struct radeon_colorbuffer_state {
 110         GLuint clear;
 111         int roundEnable;
 112         struct gl_renderbuffer *rb;
 113         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 114 };
 115
 116 struct radeon_depthbuffer_state {
 117         GLuint clear;
 118         struct gl_renderbuffer *rb;
 119 };
 120
 121 struct radeon_scissor_state {
 122         drm_clip_rect_t rect;
 123         GLboolean enabled;
 124
 125         GLuint numClipRects;    /* Cliprects active */
 126         GLuint numAllocedClipRects;     /* Cliprects available */
 127         drm_clip_rect_t *pClipRects;
 128 };
 129
 130 struct radeon_stencilbuffer_state {
 131         GLuint clear;           /* rb3d_stencilrefmask value */
 132 };
 133
 134 struct radeon_state_atom {
 135         struct radeon_state_atom *next, *prev;
 136         const char *name;       /* for debug */
 137         int cmd_size;           /* size in bytes */
 138         GLuint idx;
 139         GLuint is_tcl;
 140         GLuint *cmd;            /* one or more cmd's */
 141         GLuint *lastcmd;                /* one or more cmd's */
 142         GLboolean dirty;        /* dirty-mark in emit_state_list */
 143         int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */
 144         void (*emit) (struct gl_context *, struct radeon_state_atom *atom);
 145 };
 146
 147 struct radeon_hw_state {
 148         /* Head of the linked list of state atoms. */
 149         struct radeon_state_atom atomlist;
 150         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 151         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 152         GLboolean is_dirty, all_dirty;
 153 };
 154
 155
 156 /* Texture related */
 157 typedef struct _radeon_texture_image radeon_texture_image;
 158
 159
 160 /**
 161  * This is a subclass of swrast_texture_image since we use swrast
 162  * for software fallback rendering.
 163  */
 164 struct _radeon_texture_image {
 165         struct swrast_texture_image base;
 166
 167         /**
 168          * If mt != 0, the image is stored in hardware format in the
 169          * given mipmap tree. In this case, base.Data may point into the
 170          * mapping of the buffer object that contains the mipmap tree.
 171          *
 172          * If mt == 0, the image is stored in normal memory pointed to
 173          * by base.Data.
 174          */
 175         struct _radeon_mipmap_tree *mt;
 176         struct radeon_bo *bo;
 177 };
 178
 179
 180 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 181 {
 182         return (radeon_texture_image*)image;
 183 }
 184
 185
 186 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 187
 188 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 189
 190 /* Texture object in locally shared texture space.
 191  */
 192 struct radeon_tex_obj {
 193         struct gl_texture_object base;
 194         struct _radeon_mipmap_tree *mt;
 195
 196         /**
 197          * This is true if we've verified that the mipmap tree above is complete
 198          * and so on.
 199          */
 200         GLboolean validated;
 201         /* Minimum LOD to be used during rendering */
 202         unsigned minLod;
 203         /* Miximum LOD to be used during rendering */
 204         unsigned maxLod;
 205
 206         GLuint override_offset;
 207         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 208         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 209         struct radeon_bo *bo;
 210
 211         GLuint pp_txfilter;     /* hardware register values */
 212         GLuint pp_txformat;
 213         GLuint pp_txformat_x;
 214         GLuint pp_txsize;       /* npot only */
 215         GLuint pp_txpitch;      /* npot only */
 216         GLuint pp_border_color;
 217         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 218
 219         GLboolean border_fallback;
 220 };
 221
 222 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 223 {
 224         return (radeonTexObj*)texObj;
 225 }
 226
 227 /* occlusion query */
 228 struct radeon_query_object {
 229         struct gl_query_object Base;
 230         struct radeon_bo *bo;
 231         int curr_offset;
 232         GLboolean emitted_begin;
 233
 234         /* Double linked list of not flushed query objects */
 235         struct radeon_query_object *prev, *next;
 236 };
 237
 238 /* Need refcounting on dma buffers:
 239  */
 240 struct radeon_dma_buffer {
 241         int refcount;           /* the number of retained regions in buf */
 242         drmBufPtr buf;
 243 };
 244
 245 struct radeon_aos {
 246         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 247         int offset; /** Offset into buffer object, in bytes */
 248         int components; /** Number of components per vertex */
 249         int stride; /** Stride in dwords (may be 0 for repeating) */
 250         int count; /** Number of vertices */
 251 };
 252
 253 #define DMA_BO_FREE_TIME 100
 254
 255 struct radeon_dma_bo {
 256   struct radeon_dma_bo *next, *prev;
 257   struct radeon_bo *bo;
 258   int expire_counter;
 259 };
 260
 261 struct radeon_dma {
 262         /* Active dma region.  Allocations for vertices and retained
 263          * regions come from here.  Also used for emitting random vertices,
 264          * these may be flushed by calling flush_current();
 265          */
 266         struct radeon_dma_bo free;
 267         struct radeon_dma_bo wait;
 268         struct radeon_dma_bo reserved;
 269         size_t current_used; /** Number of bytes allocated and forgotten about */
 270         size_t current_vertexptr; /** End of active vertex region */
 271         size_t minimum_size;
 272
 273         /**
 274          * If current_vertexptr != current_used then flush must be non-zero.
 275          * flush must be called before non-active vertex allocations can be
 276          * performed.
 277          */
 278         void (*flush) (struct gl_context *);
 279 };
 280
 281 /* radeon_swtcl.c
 282  */
 283 struct radeon_swtcl_info {
 284
 285         GLuint RenderIndex;
 286         GLuint vertex_size;
 287         GLubyte *verts;
 288
 289         /* Fallback rasterization functions
 290          */
 291         GLuint hw_primitive;
 292         GLenum render_primitive;
 293         GLuint numverts;
 294
 295         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 296         GLuint vertex_attr_count;
 297
 298         GLuint emit_prediction;
 299         struct radeon_bo *bo;
 300 };
 301
 302 #define RADEON_MAX_AOS_ARRAYS           16
 303 struct radeon_tcl_info {
 304         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 305         GLuint aos_count;
 306         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 307         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 308 };
 309
 310 struct radeon_ioctl {
 311         GLuint vertex_offset;
 312         GLuint vertex_max;
 313         struct radeon_bo *bo;
 314         GLuint vertex_size;
 315 };
 316
 317 #define RADEON_MAX_PRIMS 64
 318
 319 struct radeon_prim {
 320         GLuint start;
 321         GLuint end;
 322         GLuint prim;
 323 };
 324
 325 static INLINE GLuint radeonPackColor(GLuint cpp,
 326                                      GLubyte r, GLubyte g,
 327                                      GLubyte b, GLubyte a)
 328 {
 329         switch (cpp) {
 330         case 2:
 331                 return PACK_COLOR_565(r, g, b);
 332         case 4:
 333                 return PACK_COLOR_8888(a, r, g, b);
 334         default:
 335                 return 0;
 336         }
 337 }
 338
 339 #define MAX_CMD_BUF_SZ (16*1024)
 340
 341 #define MAX_DMA_BUF_SZ (64*1024)
 342
 343 struct radeon_store {
 344         GLuint statenr;
 345         GLuint primnr;
 346         char cmd_buf[MAX_CMD_BUF_SZ];
 347         int cmd_used;
 348         int elts_start;
 349 };
 350
 351 struct radeon_dri_mirror {
 352         __DRIcontext *context;  /* DRI context */
 353         __DRIscreen *screen;    /* DRI screen */
 354
 355         drm_context_t hwContext;
 356         drm_hw_lock_t *hwLock;
 357         int hwLockCount;
 358         int fd;
 359         int drmMinor;
 360 };
 361
 362 typedef void (*radeon_tri_func) (radeonContextPtr,
 363                                  radeonVertex *,
 364                                  radeonVertex *, radeonVertex *);
 365
 366 typedef void (*radeon_line_func) (radeonContextPtr,
 367                                   radeonVertex *, radeonVertex *);
 368
 369 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 370
 371 #define RADEON_MAX_BOS 32
 372 struct radeon_state {
 373         struct radeon_colorbuffer_state color;
 374         struct radeon_depthbuffer_state depth;
 375         struct radeon_scissor_state scissor;
 376         struct radeon_stencilbuffer_state stencil;
 377 };
 378
 379 /**
 380  * This structure holds the command buffer while it is being constructed.
 381  *
 382  * The first batch of commands in the buffer is always the state that needs
 383  * to be re-emitted when the context is lost. This batch can be skipped
 384  * otherwise.
 385  */
 386 struct radeon_cmdbuf {
 387         struct radeon_cs_manager    *csm;
 388         struct radeon_cs            *cs;
 389         int size; /** # of dwords total */
 390         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 391 };
 392
 393 struct radeon_context {
 394    struct gl_context *glCtx;
 395    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 396
 397    /* Texture object bookkeeping
 398     */
 399    int                   texture_depth;
 400    float                 initialMaxAnisotropy;
 401    uint32_t              texture_row_align;
 402    uint32_t              texture_rect_row_align;
 403    uint32_t              texture_compressed_row_align;
 404
 405   struct radeon_dma dma;
 406   struct radeon_hw_state hw;
 407    /* Rasterization and vertex state:
 408     */
 409    GLuint TclFallback;
 410    GLuint Fallback;
 411    GLuint NewGLState;
 412    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 413
 414    /* Drawable information */
 415    unsigned int lastStamp;
 416    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 417
 418    /* Mirrors of some DRI state */
 419    struct radeon_dri_mirror dri;
 420
 421    /* Busy waiting */
 422    GLuint do_usleeps;
 423    GLuint do_irqs;
 424    GLuint irqsEmitted;
 425    drm_radeon_irq_wait_t iw;
 426
 427    /* Derived state - for r300 only */
 428    struct radeon_state state;
 429
 430    struct radeon_swtcl_info swtcl;
 431    struct radeon_tcl_info tcl;
 432    /* Configuration cache
 433     */
 434    driOptionCache optionCache;
 435
 436    struct radeon_cmdbuf cmdbuf;
 437
 438    struct radeon_debug debug;
 439
 440   drm_clip_rect_t fboRect;
 441   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 442   GLboolean front_cliprects;
 443
 444    /**
 445     * Set if rendering has occured to the drawable's front buffer.
 446     *
 447     * This is used in the DRI2 case to detect that glFlush should also copy
 448     * the contents of the fake front buffer to the real front buffer.
 449     */
 450    GLboolean front_buffer_dirty;
 451
 452    /**
 453     * Track whether front-buffer rendering is currently enabled
 454     *
 455     * A separate flag is used to track this in order to support MRT more
 456     * easily.
 457     */
 458    GLboolean is_front_buffer_rendering;
 459
 460    /**
 461     * Track whether front-buffer is the current read target.
 462     *
 463     * This is closely associated with is_front_buffer_rendering, but may
 464     * be set separately.  The DRI2 fake front buffer must be referenced
 465     * either way.
 466     */
 467    GLboolean is_front_buffer_reading;
 468
 469    struct {
 470         struct radeon_query_object *current;
 471         struct radeon_state_atom queryobj;
 472    } query;
 473
 474    struct {
 475            void (*get_lock)(radeonContextPtr radeon);
 476            void (*update_viewport_offset)(struct gl_context *ctx);
 477            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 478            void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);
 479            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 480            void (*pre_emit_state)(radeonContextPtr rmesa);
 481            void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);
 482            void (*free_context)(struct gl_context *ctx);
 483            void (*emit_query_finish)(radeonContextPtr radeon);
 484            void (*update_scissor)(struct gl_context *ctx);
 485            unsigned (*check_blit)(gl_format mesa_format);
 486            unsigned (*blit)(struct gl_context *ctx,
 487                         struct radeon_bo *src_bo,
 488                         intptr_t src_offset,
 489                         gl_format src_mesaformat,
 490                         unsigned src_pitch,
 491                         unsigned src_width,
 492                         unsigned src_height,
 493                         unsigned src_x_offset,
 494                         unsigned src_y_offset,
 495                         struct radeon_bo *dst_bo,
 496                         intptr_t dst_offset,
 497                         gl_format dst_mesaformat,
 498                         unsigned dst_pitch,
 499                         unsigned dst_width,
 500                         unsigned dst_height,
 501                         unsigned dst_x_offset,
 502                         unsigned dst_y_offset,
 503                         unsigned reg_width,
 504                         unsigned reg_height,
 505                         unsigned flip_y);
 506            unsigned (*is_format_renderable)(gl_format mesa_format);
 507    } vtbl;
 508 };
 509
 510 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 511
 512 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 513 {
 514         return radeon->dri.context->driDrawablePriv;
 515 }
 516
 517 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 518 {
 519         return radeon->dri.context->driReadablePriv;
 520 }
 521
 522 GLboolean radeonInitContext(radeonContextPtr radeon,
 523                             struct dd_function_table* functions,
 524                             const struct gl_config * glVisual,
 525                             __DRIcontext * driContextPriv,
 526                             void *sharedContextPrivate);
 527
 528 void radeonCleanupContext(radeonContextPtr radeon);
 529 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 530 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 531                                  GLboolean front_only);
 532 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 533                             __DRIdrawable * driDrawPriv,
 534                             __DRIdrawable * driReadPriv);
 535 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 536 void radeon_prepare_render(radeonContextPtr radeon);
 537
 538 #endif