src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 /* This union is used to avoid warnings/miscompilation
  17    with float to uint32_t casts due to strict-aliasing */
  18 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  19
  20 struct radeon_context;
  21 typedef struct radeon_context radeonContextRec;
  22 typedef struct radeon_context *radeonContextPtr;
  23
  24
  25 #define TEX_0   0x1
  26 #define TEX_1   0x2
  27 #define TEX_2   0x4
  28 #define TEX_3   0x8
  29 #define TEX_4   0x10
  30 #define TEX_5   0x20
  31
  32 /* Rasterizing fallbacks */
  33 /* See correponding strings in r200_swtcl.c */
  34 #define RADEON_FALLBACK_TEXTURE         0x0001
  35 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  36 #define RADEON_FALLBACK_STENCIL         0x0004
  37 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  38 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  39 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  40 #define RADEON_FALLBACK_DISABLE         0x0040
  41 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  42 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  43 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  44
  45 #define R200_FALLBACK_TEXTURE           0x01
  46 #define R200_FALLBACK_DRAW_BUFFER       0x02
  47 #define R200_FALLBACK_STENCIL           0x04
  48 #define R200_FALLBACK_RENDER_MODE       0x08
  49 #define R200_FALLBACK_DISABLE           0x10
  50 #define R200_FALLBACK_BORDER_MODE       0x20
  51
  52 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  53 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  54 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  55 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  56 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  57 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  58 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  59 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  60 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  61
  62 /* The blit width for texture uploads
  63  */
  64 #define BLIT_WIDTH_BYTES 1024
  65
  66 /* Use the templated vertex format:
  67  */
  68 #define COLOR_IS_RGBA
  69 #define TAG(x) radeon##x
  70 #include "tnl_dd/t_dd_vertex.h"
  71 #undef TAG
  72
  73 struct radeon_renderbuffer
  74 {
  75         struct gl_renderbuffer base;
  76         struct radeon_bo *bo;
  77         unsigned int cpp;
  78         /* unsigned int offset; */
  79         unsigned int pitch;
  80         unsigned int width;
  81         unsigned int height;
  82
  83         /* boo Xorg 6.8.2 compat */
  84         int has_surface;
  85
  86         GLuint pf_pending;  /**< sequence number of pending flip */
  87         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  88         __DRIdrawablePrivate *dPriv;
  89 };
  90
  91 struct radeon_framebuffer
  92 {
  93         struct gl_framebuffer base;
  94
  95         struct radeon_renderbuffer *color_rb[2];
  96
  97         GLuint vbl_waited;
  98
  99         /* buffer swap */
 100         int64_t swap_ust;
 101         int64_t swap_missed_ust;
 102
 103         GLuint swap_count;
 104         GLuint swap_missed_count;
 105
 106         /* Drawable page flipping state */
 107         GLboolean pf_active;
 108         GLint pf_current_page;
 109         GLint pf_num_pages;
 110
 111 };
 112
 113
 114 struct radeon_colorbuffer_state {
 115         GLuint clear;
 116         int roundEnable;
 117         struct radeon_renderbuffer *rrb;
 118 };
 119
 120 struct radeon_depthbuffer_state {
 121         GLuint clear;
 122         GLfloat scale;
 123         struct radeon_renderbuffer *rrb;
 124 };
 125
 126 struct radeon_scissor_state {
 127         drm_clip_rect_t rect;
 128         GLboolean enabled;
 129
 130         GLuint numClipRects;    /* Cliprects active */
 131         GLuint numAllocedClipRects;     /* Cliprects available */
 132         drm_clip_rect_t *pClipRects;
 133 };
 134
 135 struct radeon_stencilbuffer_state {
 136         GLboolean hwBuffer;
 137         GLuint clear;           /* rb3d_stencilrefmask value */
 138 };
 139
 140 struct radeon_stipple_state {
 141         GLuint mask[32];
 142 };
 143
 144 struct radeon_state_atom {
 145         struct radeon_state_atom *next, *prev;
 146         const char *name;       /* for debug */
 147         int cmd_size;           /* size in bytes */
 148         GLuint idx;
 149         GLuint is_tcl;
 150         GLuint *cmd;            /* one or more cmd's */
 151         GLuint *lastcmd;                /* one or more cmd's */
 152         GLboolean dirty;        /* dirty-mark in emit_state_list */
 153         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 154         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 155 };
 156
 157 struct radeon_hw_state {
 158         /* Head of the linked list of state atoms. */
 159         struct radeon_state_atom atomlist;
 160         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 161         GLboolean is_dirty, all_dirty;
 162 };
 163
 164
 165 /* Texture related */
 166 typedef struct _radeon_texture_image radeon_texture_image;
 167
 168 struct _radeon_texture_image {
 169         struct gl_texture_image base;
 170
 171         /**
 172          * If mt != 0, the image is stored in hardware format in the
 173          * given mipmap tree. In this case, base.Data may point into the
 174          * mapping of the buffer object that contains the mipmap tree.
 175          *
 176          * If mt == 0, the image is stored in normal memory pointed to
 177          * by base.Data.
 178          */
 179         struct _radeon_mipmap_tree *mt;
 180         struct radeon_bo *bo;
 181
 182         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 183         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 184 };
 185
 186
 187 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 188 {
 189         return (radeon_texture_image*)image;
 190 }
 191
 192
 193 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 194
 195 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 196
 197 /* Texture object in locally shared texture space.
 198  */
 199 struct radeon_tex_obj {
 200         struct gl_texture_object base;
 201         struct _radeon_mipmap_tree *mt;
 202
 203         /**
 204          * This is true if we've verified that the mipmap tree above is complete
 205          * and so on.
 206          */
 207         GLboolean validated;
 208
 209         GLuint override_offset;
 210         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 211         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 212         struct radeon_bo *bo;
 213
 214         GLuint pp_txfilter;     /* hardware register values */
 215         GLuint pp_txformat;
 216         GLuint pp_txformat_x;
 217         GLuint pp_txsize;       /* npot only */
 218         GLuint pp_txpitch;      /* npot only */
 219         GLuint pp_border_color;
 220         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 221
 222         GLuint pp_txfilter_1;   /*  r300 */
 223
 224         GLboolean border_fallback;
 225
 226
 227 };
 228
 229 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 230 {
 231         return (radeonTexObj*)texObj;
 232 }
 233
 234 /* Need refcounting on dma buffers:
 235  */
 236 struct radeon_dma_buffer {
 237         int refcount;           /* the number of retained regions in buf */
 238         drmBufPtr buf;
 239 };
 240
 241 struct radeon_aos {
 242         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 243         int offset; /** Offset into buffer object, in bytes */
 244         int components; /** Number of components per vertex */
 245         int stride; /** Stride in dwords (may be 0 for repeating) */
 246         int count; /** Number of vertices */
 247 };
 248
 249 struct radeon_dma {
 250         /* Active dma region.  Allocations for vertices and retained
 251          * regions come from here.  Also used for emitting random vertices,
 252          * these may be flushed by calling flush_current();
 253          */
 254         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 255         int current_used; /** Number of bytes allocated and forgotten about */
 256         int current_vertexptr; /** End of active vertex region */
 257
 258         /**
 259          * If current_vertexptr != current_used then flush must be non-zero.
 260          * flush must be called before non-active vertex allocations can be
 261          * performed.
 262          */
 263         void (*flush) (GLcontext *);
 264
 265         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 266          * for which a DISCARD command is currently queued in the command buffer
 267 .
 268          */
 269         GLuint nr_released_bufs;
 270 };
 271
 272 /* radeon_swtcl.c
 273  */
 274 struct radeon_swtcl_info {
 275
 276         GLuint RenderIndex;
 277         GLuint vertex_size;
 278         GLubyte *verts;
 279
 280         /* Fallback rasterization functions
 281          */
 282         GLuint hw_primitive;
 283         GLenum render_primitive;
 284         GLuint numverts;
 285
 286         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 287         GLuint vertex_attr_count;
 288
 289 };
 290
 291 struct radeon_ioctl {
 292         GLuint vertex_offset;
 293         struct radeon_bo *bo;
 294         GLuint vertex_size;
 295 };
 296
 297 #define RADEON_MAX_PRIMS 64
 298
 299 struct radeon_prim {
 300         GLuint start;
 301         GLuint end;
 302         GLuint prim;
 303 };
 304
 305 static INLINE GLuint radeonPackColor(GLuint cpp,
 306                                      GLubyte r, GLubyte g,
 307                                      GLubyte b, GLubyte a)
 308 {
 309         switch (cpp) {
 310         case 2:
 311                 return PACK_COLOR_565(r, g, b);
 312         case 4:
 313                 return PACK_COLOR_8888(a, r, g, b);
 314         default:
 315                 return 0;
 316         }
 317 }
 318
 319 #define MAX_CMD_BUF_SZ (16*1024)
 320
 321 #define MAX_DMA_BUF_SZ (64*1024)
 322
 323 struct radeon_store {
 324         GLuint statenr;
 325         GLuint primnr;
 326         char cmd_buf[MAX_CMD_BUF_SZ];
 327         int cmd_used;
 328         int elts_start;
 329 };
 330
 331 struct radeon_dri_mirror {
 332         __DRIcontextPrivate *context;   /* DRI context */
 333         __DRIscreenPrivate *screen;     /* DRI screen */
 334
 335    /**
 336     * DRI drawable bound to this context for drawing.
 337     */
 338         __DRIdrawablePrivate *drawable;
 339
 340    /**
 341     * DRI drawable bound to this context for reading.
 342     */
 343         __DRIdrawablePrivate *readable;
 344
 345         drm_context_t hwContext;
 346         drm_hw_lock_t *hwLock;
 347         int fd;
 348         int drmMinor;
 349 };
 350
 351 #define DEBUG_TEXTURE   0x001
 352 #define DEBUG_STATE     0x002
 353 #define DEBUG_IOCTL     0x004
 354 #define DEBUG_PRIMS     0x008
 355 #define DEBUG_VERTS     0x010
 356 #define DEBUG_FALLBACKS 0x020
 357 #define DEBUG_VFMT      0x040
 358 #define DEBUG_CODEGEN   0x080
 359 #define DEBUG_VERBOSE   0x100
 360 #define DEBUG_DRI       0x200
 361 #define DEBUG_DMA       0x400
 362 #define DEBUG_SANITY    0x800
 363 #define DEBUG_SYNC      0x1000
 364 #define DEBUG_PIXEL     0x2000
 365 #define DEBUG_MEMORY    0x4000
 366
 367
 368
 369 typedef void (*radeon_tri_func) (radeonContextPtr,
 370                                  radeonVertex *,
 371                                  radeonVertex *, radeonVertex *);
 372
 373 typedef void (*radeon_line_func) (radeonContextPtr,
 374                                   radeonVertex *, radeonVertex *);
 375
 376 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 377
 378 struct radeon_state {
 379         struct radeon_colorbuffer_state color;
 380         struct radeon_depthbuffer_state depth;
 381         struct radeon_scissor_state scissor;
 382         struct radeon_stencilbuffer_state stencil;
 383 };
 384
 385 /**
 386  * This structure holds the command buffer while it is being constructed.
 387  *
 388  * The first batch of commands in the buffer is always the state that needs
 389  * to be re-emitted when the context is lost. This batch can be skipped
 390  * otherwise.
 391  */
 392 struct radeon_cmdbuf {
 393         struct radeon_cs_manager    *csm;
 394         struct radeon_cs            *cs;
 395         int size; /** # of dwords total */
 396         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 397 };
 398
 399 struct radeon_context {
 400    GLcontext *glCtx;
 401    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 402
 403    /* Texture object bookkeeping
 404     */
 405    int                   texture_depth;
 406    float                 initialMaxAnisotropy;
 407
 408   struct radeon_dma dma;
 409   struct radeon_hw_state hw;
 410    /* Rasterization and vertex state:
 411     */
 412    GLuint TclFallback;
 413    GLuint Fallback;
 414    GLuint NewGLState;
 415    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 416
 417    /* Drawable, cliprect and scissor information */
 418    GLuint numClipRects; /* Cliprects for the draw buffer */
 419    drm_clip_rect_t *pClipRects;
 420    unsigned int lastStamp;
 421    GLboolean lost_context;
 422    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 423
 424    /* Mirrors of some DRI state */
 425    struct radeon_dri_mirror dri;
 426
 427    /* Busy waiting */
 428    GLuint do_usleeps;
 429    GLuint do_irqs;
 430    GLuint irqsEmitted;
 431    drm_radeon_irq_wait_t iw;
 432
 433    /* Derived state - for r300 only */
 434    struct radeon_state state;
 435
 436    struct radeon_swtcl_info swtcl;
 437    /* Configuration cache
 438     */
 439    driOptionCache optionCache;
 440
 441    struct radeon_cmdbuf cmdbuf;
 442
 443         drm_clip_rect_t fboRect;
 444         GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 445         GLboolean front_cliprects;
 446
 447    struct {
 448            void (*get_lock)(radeonContextPtr radeon);
 449            void (*update_viewport_offset)(GLcontext *ctx);
 450            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 451            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 452            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 453            void (*pre_emit_state)(radeonContextPtr rmesa);
 454            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 455    } vtbl;
 456 };
 457
 458 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 459
 460 /**
 461  * This function takes a float and packs it into a uint32_t
 462  */
 463 static INLINE uint32_t radeonPackFloat32(float fl)
 464 {
 465         union {
 466                 float fl;
 467                 uint32_t u;
 468         } u;
 469
 470         u.fl = fl;
 471         return u.u;
 472 }
 473
 474 /* This is probably wrong for some values, I need to test this
 475  * some more.  Range checking would be a good idea also..
 476  *
 477  * But it works for most things.  I'll fix it later if someone
 478  * else with a better clue doesn't
 479  */
 480 static INLINE uint32_t radeonPackFloat24(float f)
 481 {
 482         float mantissa;
 483         int exponent;
 484         uint32_t float24 = 0;
 485
 486         if (f == 0.0)
 487                 return 0;
 488
 489         mantissa = frexpf(f, &exponent);
 490
 491         /* Handle -ve */
 492         if (mantissa < 0) {
 493                 float24 |= (1 << 23);
 494                 mantissa = mantissa * -1.0;
 495         }
 496         /* Handle exponent, bias of 63 */
 497         exponent += 62;
 498         float24 |= (exponent << 16);
 499         /* Kill 7 LSB of mantissa */
 500         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 501
 502         return float24;
 503 }
 504
 505 GLboolean radeonInitContext(radeonContextPtr radeon,
 506                             struct dd_function_table* functions,
 507                             const __GLcontextModes * glVisual,
 508                             __DRIcontextPrivate * driContextPriv,
 509                             void *sharedContextPrivate);
 510
 511 void radeonCleanupContext(radeonContextPtr radeon);
 512 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 513 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 514 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 515                             __DRIdrawablePrivate * driDrawPriv,
 516                             __DRIdrawablePrivate * driReadPriv);
 517
 518 /* ================================================================
 519  * Debugging:
 520  */
 521 #define DO_DEBUG                1
 522
 523 #if DO_DEBUG
 524 extern int RADEON_DEBUG;
 525 #else
 526 #define RADEON_DEBUG            0
 527 #endif
 528
 529 #endif