src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_debug.h"
  12 #include "radeon_screen.h"
  13 #include "radeon_drm.h"
  14 #include "dri_util.h"
  15 #include "tnl/t_vertex.h"
  16 #include "swrast/s_context.h"
  17
  18 struct radeon_context;
  19
  20 #include "radeon_bocs_wrapper.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct gl_renderbuffer base;
  84         struct radeon_bo *bo;
  85         unsigned int cpp;
  86         /* unsigned int offset; */
  87         unsigned int pitch;
  88
  89         uint32_t draw_offset; /* FBO */
  90         /* boo Xorg 6.8.2 compat */
  91         int has_surface;
  92
  93         GLuint pf_pending;  /**< sequence number of pending flip */
  94         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  95         __DRIdrawable *dPriv;
  96
  97         /* r6xx+ tiling */
  98         GLuint tile_config;
  99         GLint group_bytes;
 100         GLint num_channels;
 101         GLint num_banks;
 102         GLint r7xx_bank_op;
 103 };
 104
 105 struct radeon_framebuffer
 106 {
 107         struct gl_framebuffer base;
 108
 109         struct radeon_renderbuffer *color_rb[2];
 110
 111         GLuint vbl_waited;
 112
 113         /* buffer swap */
 114         int64_t swap_ust;
 115         int64_t swap_missed_ust;
 116
 117         GLuint swap_count;
 118         GLuint swap_missed_count;
 119
 120         /* Drawable page flipping state */
 121         GLboolean pf_active;
 122         GLint pf_current_page;
 123         GLint pf_num_pages;
 124
 125 };
 126
 127
 128 struct radeon_colorbuffer_state {
 129         GLuint clear;
 130         int roundEnable;
 131         struct gl_renderbuffer *rb;
 132         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 133 };
 134
 135 struct radeon_depthbuffer_state {
 136         GLuint clear;
 137         struct gl_renderbuffer *rb;
 138 };
 139
 140 struct radeon_scissor_state {
 141         drm_clip_rect_t rect;
 142         GLboolean enabled;
 143
 144         GLuint numClipRects;    /* Cliprects active */
 145         GLuint numAllocedClipRects;     /* Cliprects available */
 146         drm_clip_rect_t *pClipRects;
 147 };
 148
 149 struct radeon_stencilbuffer_state {
 150         GLuint clear;           /* rb3d_stencilrefmask value */
 151 };
 152
 153 struct radeon_state_atom {
 154         struct radeon_state_atom *next, *prev;
 155         const char *name;       /* for debug */
 156         int cmd_size;           /* size in bytes */
 157         GLuint idx;
 158         GLuint is_tcl;
 159         GLuint *cmd;            /* one or more cmd's */
 160         GLuint *lastcmd;                /* one or more cmd's */
 161         GLboolean dirty;        /* dirty-mark in emit_state_list */
 162         int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */
 163         void (*emit) (struct gl_context *, struct radeon_state_atom *atom);
 164 };
 165
 166 struct radeon_hw_state {
 167         /* Head of the linked list of state atoms. */
 168         struct radeon_state_atom atomlist;
 169         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 170         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 171         GLboolean is_dirty, all_dirty;
 172 };
 173
 174
 175 /* Texture related */
 176 typedef struct _radeon_texture_image radeon_texture_image;
 177
 178
 179 /**
 180  * This is a subclass of swrast_texture_image since we use swrast
 181  * for software fallback rendering.
 182  */
 183 struct _radeon_texture_image {
 184         struct swrast_texture_image base;
 185
 186         /**
 187          * If mt != 0, the image is stored in hardware format in the
 188          * given mipmap tree. In this case, base.Data may point into the
 189          * mapping of the buffer object that contains the mipmap tree.
 190          *
 191          * If mt == 0, the image is stored in normal memory pointed to
 192          * by base.Data.
 193          */
 194         struct _radeon_mipmap_tree *mt;
 195         struct radeon_bo *bo;
 196
 197         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 198         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 199 };
 200
 201
 202 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 203 {
 204         return (radeon_texture_image*)image;
 205 }
 206
 207
 208 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 209
 210 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 211
 212 /* Texture object in locally shared texture space.
 213  */
 214 struct radeon_tex_obj {
 215         struct gl_texture_object base;
 216         struct _radeon_mipmap_tree *mt;
 217
 218         /**
 219          * This is true if we've verified that the mipmap tree above is complete
 220          * and so on.
 221          */
 222         GLboolean validated;
 223         /* Minimum LOD to be used during rendering */
 224         unsigned minLod;
 225         /* Miximum LOD to be used during rendering */
 226         unsigned maxLod;
 227
 228         GLuint override_offset;
 229         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 230         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 231         struct radeon_bo *bo;
 232
 233         GLuint pp_txfilter;     /* hardware register values */
 234         GLuint pp_txformat;
 235         GLuint pp_txformat_x;
 236         GLuint pp_txsize;       /* npot only */
 237         GLuint pp_txpitch;      /* npot only */
 238         GLuint pp_border_color;
 239         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 240
 241         GLuint pp_txfilter_1;   /*  r300 */
 242
 243         /* r700 texture states */
 244         GLuint SQ_TEX_RESOURCE0;
 245         GLuint SQ_TEX_RESOURCE1;
 246         GLuint SQ_TEX_RESOURCE2;
 247         GLuint SQ_TEX_RESOURCE3;
 248         GLuint SQ_TEX_RESOURCE4;
 249         GLuint SQ_TEX_RESOURCE5;
 250         GLuint SQ_TEX_RESOURCE6;
 251
 252     GLuint SQ_TEX_RESOURCE7;
 253
 254         GLuint SQ_TEX_SAMPLER0;
 255         GLuint SQ_TEX_SAMPLER1;
 256         GLuint SQ_TEX_SAMPLER2;
 257
 258         GLuint TD_PS_SAMPLER0_BORDER_RED;
 259         GLuint TD_PS_SAMPLER0_BORDER_GREEN;
 260         GLuint TD_PS_SAMPLER0_BORDER_BLUE;
 261         GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
 262
 263         GLboolean border_fallback;
 264
 265
 266 };
 267
 268 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 269 {
 270         return (radeonTexObj*)texObj;
 271 }
 272
 273 /* occlusion query */
 274 struct radeon_query_object {
 275         struct gl_query_object Base;
 276         struct radeon_bo *bo;
 277         int curr_offset;
 278         GLboolean emitted_begin;
 279
 280         /* Double linked list of not flushed query objects */
 281         struct radeon_query_object *prev, *next;
 282 };
 283
 284 /* Need refcounting on dma buffers:
 285  */
 286 struct radeon_dma_buffer {
 287         int refcount;           /* the number of retained regions in buf */
 288         drmBufPtr buf;
 289 };
 290
 291 struct radeon_aos {
 292         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 293         int offset; /** Offset into buffer object, in bytes */
 294         int components; /** Number of components per vertex */
 295         int stride; /** Stride in dwords (may be 0 for repeating) */
 296         int count; /** Number of vertices */
 297 };
 298
 299 #define DMA_BO_FREE_TIME 100
 300
 301 struct radeon_dma_bo {
 302   struct radeon_dma_bo *next, *prev;
 303   struct radeon_bo *bo;
 304   int expire_counter;
 305 };
 306
 307 struct radeon_dma {
 308         /* Active dma region.  Allocations for vertices and retained
 309          * regions come from here.  Also used for emitting random vertices,
 310          * these may be flushed by calling flush_current();
 311          */
 312         struct radeon_dma_bo free;
 313         struct radeon_dma_bo wait;
 314         struct radeon_dma_bo reserved;
 315         size_t current_used; /** Number of bytes allocated and forgotten about */
 316         size_t current_vertexptr; /** End of active vertex region */
 317         size_t minimum_size;
 318
 319         /**
 320          * If current_vertexptr != current_used then flush must be non-zero.
 321          * flush must be called before non-active vertex allocations can be
 322          * performed.
 323          */
 324         void (*flush) (struct gl_context *);
 325 };
 326
 327 /* radeon_swtcl.c
 328  */
 329 struct radeon_swtcl_info {
 330
 331         GLuint RenderIndex;
 332         GLuint vertex_size;
 333         GLubyte *verts;
 334
 335         /* Fallback rasterization functions
 336          */
 337         GLuint hw_primitive;
 338         GLenum render_primitive;
 339         GLuint numverts;
 340
 341         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 342         GLuint vertex_attr_count;
 343
 344         GLuint emit_prediction;
 345         struct radeon_bo *bo;
 346 };
 347
 348 #define RADEON_MAX_AOS_ARRAYS           16
 349 struct radeon_tcl_info {
 350         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 351         GLuint aos_count;
 352         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 353         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 354 };
 355
 356 struct radeon_ioctl {
 357         GLuint vertex_offset;
 358         GLuint vertex_max;
 359         struct radeon_bo *bo;
 360         GLuint vertex_size;
 361 };
 362
 363 #define RADEON_MAX_PRIMS 64
 364
 365 struct radeon_prim {
 366         GLuint start;
 367         GLuint end;
 368         GLuint prim;
 369 };
 370
 371 static INLINE GLuint radeonPackColor(GLuint cpp,
 372                                      GLubyte r, GLubyte g,
 373                                      GLubyte b, GLubyte a)
 374 {
 375         switch (cpp) {
 376         case 2:
 377                 return PACK_COLOR_565(r, g, b);
 378         case 4:
 379                 return PACK_COLOR_8888(a, r, g, b);
 380         default:
 381                 return 0;
 382         }
 383 }
 384
 385 #define MAX_CMD_BUF_SZ (16*1024)
 386
 387 #define MAX_DMA_BUF_SZ (64*1024)
 388
 389 struct radeon_store {
 390         GLuint statenr;
 391         GLuint primnr;
 392         char cmd_buf[MAX_CMD_BUF_SZ];
 393         int cmd_used;
 394         int elts_start;
 395 };
 396
 397 struct radeon_dri_mirror {
 398         __DRIcontext *context;  /* DRI context */
 399         __DRIscreen *screen;    /* DRI screen */
 400
 401         drm_context_t hwContext;
 402         drm_hw_lock_t *hwLock;
 403         int hwLockCount;
 404         int fd;
 405         int drmMinor;
 406 };
 407
 408 typedef void (*radeon_tri_func) (radeonContextPtr,
 409                                  radeonVertex *,
 410                                  radeonVertex *, radeonVertex *);
 411
 412 typedef void (*radeon_line_func) (radeonContextPtr,
 413                                   radeonVertex *, radeonVertex *);
 414
 415 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 416
 417 #define RADEON_MAX_BOS 32
 418 struct radeon_state {
 419         struct radeon_colorbuffer_state color;
 420         struct radeon_depthbuffer_state depth;
 421         struct radeon_scissor_state scissor;
 422         struct radeon_stencilbuffer_state stencil;
 423 };
 424
 425 /**
 426  * This structure holds the command buffer while it is being constructed.
 427  *
 428  * The first batch of commands in the buffer is always the state that needs
 429  * to be re-emitted when the context is lost. This batch can be skipped
 430  * otherwise.
 431  */
 432 struct radeon_cmdbuf {
 433         struct radeon_cs_manager    *csm;
 434         struct radeon_cs            *cs;
 435         int size; /** # of dwords total */
 436         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 437 };
 438
 439 struct radeon_context {
 440    struct gl_context *glCtx;
 441    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 442
 443    /* Texture object bookkeeping
 444     */
 445    int                   texture_depth;
 446    float                 initialMaxAnisotropy;
 447    uint32_t              texture_row_align;
 448    uint32_t              texture_rect_row_align;
 449    uint32_t              texture_compressed_row_align;
 450
 451   struct radeon_dma dma;
 452   struct radeon_hw_state hw;
 453    /* Rasterization and vertex state:
 454     */
 455    GLuint TclFallback;
 456    GLuint Fallback;
 457    GLuint NewGLState;
 458    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 459
 460    /* Drawable information */
 461    unsigned int lastStamp;
 462    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 463
 464    /* Mirrors of some DRI state */
 465    struct radeon_dri_mirror dri;
 466
 467    /* Busy waiting */
 468    GLuint do_usleeps;
 469    GLuint do_irqs;
 470    GLuint irqsEmitted;
 471    drm_radeon_irq_wait_t iw;
 472
 473    /* Derived state - for r300 only */
 474    struct radeon_state state;
 475
 476    struct radeon_swtcl_info swtcl;
 477    struct radeon_tcl_info tcl;
 478    /* Configuration cache
 479     */
 480    driOptionCache optionCache;
 481
 482    struct radeon_cmdbuf cmdbuf;
 483
 484    struct radeon_debug debug;
 485
 486   drm_clip_rect_t fboRect;
 487   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 488   GLboolean front_cliprects;
 489
 490    /**
 491     * Set if rendering has occured to the drawable's front buffer.
 492     *
 493     * This is used in the DRI2 case to detect that glFlush should also copy
 494     * the contents of the fake front buffer to the real front buffer.
 495     */
 496    GLboolean front_buffer_dirty;
 497
 498    /**
 499     * Track whether front-buffer rendering is currently enabled
 500     *
 501     * A separate flag is used to track this in order to support MRT more
 502     * easily.
 503     */
 504    GLboolean is_front_buffer_rendering;
 505
 506    /**
 507     * Track whether front-buffer is the current read target.
 508     *
 509     * This is closely associated with is_front_buffer_rendering, but may
 510     * be set separately.  The DRI2 fake front buffer must be referenced
 511     * either way.
 512     */
 513    GLboolean is_front_buffer_reading;
 514
 515    struct {
 516         struct radeon_query_object *current;
 517         struct radeon_state_atom queryobj;
 518    } query;
 519
 520    struct {
 521            void (*get_lock)(radeonContextPtr radeon);
 522            void (*update_viewport_offset)(struct gl_context *ctx);
 523            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 524            void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);
 525            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 526            void (*pre_emit_state)(radeonContextPtr rmesa);
 527            void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);
 528            void (*free_context)(struct gl_context *ctx);
 529            void (*emit_query_finish)(radeonContextPtr radeon);
 530            void (*update_scissor)(struct gl_context *ctx);
 531            unsigned (*check_blit)(gl_format mesa_format);
 532            unsigned (*blit)(struct gl_context *ctx,
 533                         struct radeon_bo *src_bo,
 534                         intptr_t src_offset,
 535                         gl_format src_mesaformat,
 536                         unsigned src_pitch,
 537                         unsigned src_width,
 538                         unsigned src_height,
 539                         unsigned src_x_offset,
 540                         unsigned src_y_offset,
 541                         struct radeon_bo *dst_bo,
 542                         intptr_t dst_offset,
 543                         gl_format dst_mesaformat,
 544                         unsigned dst_pitch,
 545                         unsigned dst_width,
 546                         unsigned dst_height,
 547                         unsigned dst_x_offset,
 548                         unsigned dst_y_offset,
 549                         unsigned reg_width,
 550                         unsigned reg_height,
 551                         unsigned flip_y);
 552            unsigned (*is_format_renderable)(gl_format mesa_format);
 553    } vtbl;
 554 };
 555
 556 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 557
 558 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 559 {
 560         return radeon->dri.context->driDrawablePriv;
 561 }
 562
 563 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 564 {
 565         return radeon->dri.context->driReadablePriv;
 566 }
 567
 568 /**
 569  * This function takes a float and packs it into a uint32_t
 570  */
 571 static INLINE uint32_t radeonPackFloat32(float fl)
 572 {
 573         union {
 574                 float fl;
 575                 uint32_t u;
 576         } u;
 577
 578         u.fl = fl;
 579         return u.u;
 580 }
 581
 582 /* This is probably wrong for some values, I need to test this
 583  * some more.  Range checking would be a good idea also..
 584  *
 585  * But it works for most things.  I'll fix it later if someone
 586  * else with a better clue doesn't
 587  */
 588 static INLINE uint32_t radeonPackFloat24(float f)
 589 {
 590         float mantissa;
 591         int exponent;
 592         uint32_t float24 = 0;
 593
 594         if (f == 0.0)
 595                 return 0;
 596
 597         mantissa = frexpf(f, &exponent);
 598
 599         /* Handle -ve */
 600         if (mantissa < 0) {
 601                 float24 |= (1 << 23);
 602                 mantissa = mantissa * -1.0;
 603         }
 604         /* Handle exponent, bias of 63 */
 605         exponent += 62;
 606         float24 |= (exponent << 16);
 607         /* Kill 7 LSB of mantissa */
 608         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 609
 610         return float24;
 611 }
 612
 613 GLboolean radeonInitContext(radeonContextPtr radeon,
 614                             struct dd_function_table* functions,
 615                             const struct gl_config * glVisual,
 616                             __DRIcontext * driContextPriv,
 617                             void *sharedContextPrivate);
 618
 619 void radeonCleanupContext(radeonContextPtr radeon);
 620 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 621 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 622                                  GLboolean front_only);
 623 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 624                             __DRIdrawable * driDrawPriv,
 625                             __DRIdrawable * driReadPriv);
 626 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 627 void radeon_prepare_render(radeonContextPtr radeon);
 628
 629 #endif