2 #ifndef COMMON_CONTEXT_H
3 #define COMMON_CONTEXT_H
6 #include "math/m_vector.h"
7 #include "tnl/t_context.h"
8 #include "main/colormac.h"
10 #include "radeon_debug.h"
11 #include "radeon_screen.h"
12 #include "radeon_drm.h"
14 #include "tnl/t_vertex.h"
15 #include "swrast/s_context.h"
17 struct radeon_context
;
19 #include "radeon_bo_gem.h"
20 #include "radeon_cs_gem.h"
22 /* This union is used to avoid warnings/miscompilation
23 with float to uint32_t casts due to strict-aliasing */
24 typedef union { GLfloat f
; uint32_t ui32
; } float_ui32_type
;
26 struct radeon_context
;
27 typedef struct radeon_context radeonContextRec
;
28 typedef struct radeon_context
*radeonContextPtr
;
38 /* Rasterizing fallbacks */
39 /* See correponding strings in r200_swtcl.c */
40 #define RADEON_FALLBACK_TEXTURE 0x0001
41 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
42 #define RADEON_FALLBACK_STENCIL 0x0004
43 #define RADEON_FALLBACK_RENDER_MODE 0x0008
44 #define RADEON_FALLBACK_BLEND_EQ 0x0010
45 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
46 #define RADEON_FALLBACK_DISABLE 0x0040
47 #define RADEON_FALLBACK_BORDER_MODE 0x0080
48 #define RADEON_FALLBACK_DEPTH_BUFFER 0x0100
49 #define RADEON_FALLBACK_STENCIL_BUFFER 0x0200
51 #define R200_FALLBACK_TEXTURE 0x01
52 #define R200_FALLBACK_DRAW_BUFFER 0x02
53 #define R200_FALLBACK_STENCIL 0x04
54 #define R200_FALLBACK_RENDER_MODE 0x08
55 #define R200_FALLBACK_DISABLE 0x10
56 #define R200_FALLBACK_BORDER_MODE 0x20
58 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
59 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
61 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
62 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
63 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
64 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
65 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
68 /* The blit width for texture uploads
70 #define BLIT_WIDTH_BYTES 1024
72 /* Use the templated vertex format:
75 #define TAG(x) radeon##x
76 #include "tnl_dd/t_dd_vertex.h"
79 #define RADEON_RB_CLASS 0xdeadbeef
81 struct radeon_renderbuffer
83 struct gl_renderbuffer base
;
86 /* unsigned int offset; */
89 struct radeon_bo
*map_bo
;
91 int map_x
, map_y
, map_w
, map_h
;
93 uint32_t draw_offset
; /* FBO */
94 /* boo Xorg 6.8.2 compat */
97 GLuint pf_pending
; /**< sequence number of pending flip */
101 struct radeon_framebuffer
103 struct gl_framebuffer base
;
105 struct radeon_renderbuffer
*color_rb
[2];
109 struct radeon_colorbuffer_state
{
112 struct gl_renderbuffer
*rb
;
113 uint32_t draw_offset
; /* offset into color renderbuffer - FBOs */
116 struct radeon_depthbuffer_state
{
118 struct gl_renderbuffer
*rb
;
121 struct radeon_scissor_state
{
122 drm_clip_rect_t rect
;
125 GLuint numClipRects
; /* Cliprects active */
126 GLuint numAllocedClipRects
; /* Cliprects available */
127 drm_clip_rect_t
*pClipRects
;
130 struct radeon_stencilbuffer_state
{
131 GLuint clear
; /* rb3d_stencilrefmask value */
134 struct radeon_state_atom
{
135 struct radeon_state_atom
*next
, *prev
;
136 const char *name
; /* for debug */
137 int cmd_size
; /* size in bytes */
140 GLuint
*cmd
; /* one or more cmd's */
141 GLuint
*lastcmd
; /* one or more cmd's */
142 GLboolean dirty
; /* dirty-mark in emit_state_list */
143 int (*check
) (struct gl_context
*, struct radeon_state_atom
*atom
); /* is this state active? */
144 void (*emit
) (struct gl_context
*, struct radeon_state_atom
*atom
);
147 struct radeon_hw_state
{
148 /* Head of the linked list of state atoms. */
149 struct radeon_state_atom atomlist
;
150 int max_state_size
; /* Number of bytes necessary for a full state emit. */
151 int max_post_flush_size
; /* Number of bytes necessary for post flushing emits */
152 GLboolean is_dirty
, all_dirty
;
156 /* Texture related */
157 typedef struct _radeon_texture_image radeon_texture_image
;
161 * This is a subclass of swrast_texture_image since we use swrast
162 * for software fallback rendering.
164 struct _radeon_texture_image
{
165 struct swrast_texture_image base
;
168 * If mt != 0, the image is stored in hardware format in the
169 * given mipmap tree. In this case, base.Data may point into the
170 * mapping of the buffer object that contains the mipmap tree.
172 * If mt == 0, the image is stored in normal memory pointed to
175 struct _radeon_mipmap_tree
*mt
;
176 struct radeon_bo
*bo
;
180 static INLINE radeon_texture_image
*get_radeon_texture_image(struct gl_texture_image
*image
)
182 return (radeon_texture_image
*)image
;
186 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
188 #define RADEON_TXO_MICRO_TILE (1 << 3)
190 /* Texture object in locally shared texture space.
192 struct radeon_tex_obj
{
193 struct gl_texture_object base
;
194 struct _radeon_mipmap_tree
*mt
;
197 * This is true if we've verified that the mipmap tree above is complete
201 /* Minimum LOD to be used during rendering */
203 /* Miximum LOD to be used during rendering */
206 GLuint override_offset
;
207 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
208 GLuint tile_bits
; /* hw texture tile bits used on this texture */
209 struct radeon_bo
*bo
;
211 GLuint pp_txfilter
; /* hardware register values */
213 GLuint pp_txformat_x
;
214 GLuint pp_txsize
; /* npot only */
215 GLuint pp_txpitch
; /* npot only */
216 GLuint pp_border_color
;
217 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
219 GLboolean border_fallback
;
222 static INLINE radeonTexObj
* radeon_tex_obj(struct gl_texture_object
*texObj
)
224 return (radeonTexObj
*)texObj
;
227 /* occlusion query */
228 struct radeon_query_object
{
229 struct gl_query_object Base
;
230 struct radeon_bo
*bo
;
232 GLboolean emitted_begin
;
234 /* Double linked list of not flushed query objects */
235 struct radeon_query_object
*prev
, *next
;
238 /* Need refcounting on dma buffers:
240 struct radeon_dma_buffer
{
241 int refcount
; /* the number of retained regions in buf */
246 struct radeon_bo
*bo
; /** Buffer object where vertex data is stored */
247 int offset
; /** Offset into buffer object, in bytes */
248 int components
; /** Number of components per vertex */
249 int stride
; /** Stride in dwords (may be 0 for repeating) */
250 int count
; /** Number of vertices */
253 #define DMA_BO_FREE_TIME 100
255 struct radeon_dma_bo
{
256 struct radeon_dma_bo
*next
, *prev
;
257 struct radeon_bo
*bo
;
262 /* Active dma region. Allocations for vertices and retained
263 * regions come from here. Also used for emitting random vertices,
264 * these may be flushed by calling flush_current();
266 struct radeon_dma_bo free
;
267 struct radeon_dma_bo wait
;
268 struct radeon_dma_bo reserved
;
269 size_t current_used
; /** Number of bytes allocated and forgotten about */
270 size_t current_vertexptr
; /** End of active vertex region */
274 * If current_vertexptr != current_used then flush must be non-zero.
275 * flush must be called before non-active vertex allocations can be
278 void (*flush
) (struct gl_context
*);
283 struct radeon_swtcl_info
{
289 /* Fallback rasterization functions
292 GLenum render_primitive
;
295 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
296 GLuint vertex_attr_count
;
298 GLuint emit_prediction
;
299 struct radeon_bo
*bo
;
302 #define RADEON_MAX_AOS_ARRAYS 16
303 struct radeon_tcl_info
{
304 struct radeon_aos aos
[RADEON_MAX_AOS_ARRAYS
];
306 struct radeon_bo
*elt_dma_bo
; /** Buffer object that contains element indices */
307 int elt_dma_offset
; /** Offset into this buffer object, in bytes */
310 struct radeon_ioctl
{
311 GLuint vertex_offset
;
313 struct radeon_bo
*bo
;
317 #define RADEON_MAX_PRIMS 64
325 static INLINE GLuint
radeonPackColor(GLuint cpp
,
326 GLubyte r
, GLubyte g
,
327 GLubyte b
, GLubyte a
)
331 return PACK_COLOR_565(r
, g
, b
);
333 return PACK_COLOR_8888(a
, r
, g
, b
);
339 #define MAX_CMD_BUF_SZ (16*1024)
341 #define MAX_DMA_BUF_SZ (64*1024)
343 struct radeon_store
{
346 char cmd_buf
[MAX_CMD_BUF_SZ
];
351 struct radeon_dri_mirror
{
352 __DRIcontext
*context
; /* DRI context */
353 __DRIscreen
*screen
; /* DRI screen */
355 drm_context_t hwContext
;
356 drm_hw_lock_t
*hwLock
;
362 typedef void (*radeon_tri_func
) (radeonContextPtr
,
364 radeonVertex
*, radeonVertex
*);
366 typedef void (*radeon_line_func
) (radeonContextPtr
,
367 radeonVertex
*, radeonVertex
*);
369 typedef void (*radeon_point_func
) (radeonContextPtr
, radeonVertex
*);
371 #define RADEON_MAX_BOS 32
372 struct radeon_state
{
373 struct radeon_colorbuffer_state color
;
374 struct radeon_depthbuffer_state depth
;
375 struct radeon_scissor_state scissor
;
376 struct radeon_stencilbuffer_state stencil
;
380 * This structure holds the command buffer while it is being constructed.
382 * The first batch of commands in the buffer is always the state that needs
383 * to be re-emitted when the context is lost. This batch can be skipped
386 struct radeon_cmdbuf
{
387 struct radeon_cs_manager
*csm
;
388 struct radeon_cs
*cs
;
389 int size
; /** # of dwords total */
390 unsigned int flushing
:1; /** whether we're currently in FlushCmdBufLocked */
393 struct radeon_context
{
394 struct gl_context
*glCtx
;
395 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
397 /* Texture object bookkeeping
400 float initialMaxAnisotropy
;
401 uint32_t texture_row_align
;
402 uint32_t texture_rect_row_align
;
403 uint32_t texture_compressed_row_align
;
405 struct radeon_dma dma
;
406 struct radeon_hw_state hw
;
407 /* Rasterization and vertex state:
412 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
414 /* Drawable information */
415 unsigned int lastStamp
;
416 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
418 /* Mirrors of some DRI state */
419 struct radeon_dri_mirror dri
;
425 drm_radeon_irq_wait_t iw
;
427 /* Derived state - for r300 only */
428 struct radeon_state state
;
430 struct radeon_swtcl_info swtcl
;
431 struct radeon_tcl_info tcl
;
432 /* Configuration cache
434 driOptionCache optionCache
;
436 struct radeon_cmdbuf cmdbuf
;
438 struct radeon_debug debug
;
440 drm_clip_rect_t fboRect
;
441 GLboolean front_cliprects
;
444 * Set if rendering has occured to the drawable's front buffer.
446 * This is used in the DRI2 case to detect that glFlush should also copy
447 * the contents of the fake front buffer to the real front buffer.
449 GLboolean front_buffer_dirty
;
452 * Track whether front-buffer rendering is currently enabled
454 * A separate flag is used to track this in order to support MRT more
457 GLboolean is_front_buffer_rendering
;
460 * Track whether front-buffer is the current read target.
462 * This is closely associated with is_front_buffer_rendering, but may
463 * be set separately. The DRI2 fake front buffer must be referenced
466 GLboolean is_front_buffer_reading
;
469 struct radeon_query_object
*current
;
470 struct radeon_state_atom queryobj
;
474 void (*get_lock
)(radeonContextPtr radeon
);
475 void (*update_viewport_offset
)(struct gl_context
*ctx
);
476 void (*emit_cs_header
)(struct radeon_cs
*cs
, radeonContextPtr rmesa
);
477 void (*swtcl_flush
)(struct gl_context
*ctx
, uint32_t offset
);
478 void (*pre_emit_atoms
)(radeonContextPtr rmesa
);
479 void (*pre_emit_state
)(radeonContextPtr rmesa
);
480 void (*fallback
)(struct gl_context
*ctx
, GLuint bit
, GLboolean mode
);
481 void (*free_context
)(struct gl_context
*ctx
);
482 void (*emit_query_finish
)(radeonContextPtr radeon
);
483 void (*update_scissor
)(struct gl_context
*ctx
);
484 unsigned (*check_blit
)(gl_format mesa_format
);
485 unsigned (*blit
)(struct gl_context
*ctx
,
486 struct radeon_bo
*src_bo
,
488 gl_format src_mesaformat
,
492 unsigned src_x_offset
,
493 unsigned src_y_offset
,
494 struct radeon_bo
*dst_bo
,
496 gl_format dst_mesaformat
,
500 unsigned dst_x_offset
,
501 unsigned dst_y_offset
,
505 unsigned (*is_format_renderable
)(gl_format mesa_format
);
509 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
511 static inline __DRIdrawable
* radeon_get_drawable(radeonContextPtr radeon
)
513 return radeon
->dri
.context
->driDrawablePriv
;
516 static inline __DRIdrawable
* radeon_get_readable(radeonContextPtr radeon
)
518 return radeon
->dri
.context
->driReadablePriv
;
521 GLboolean
radeonInitContext(radeonContextPtr radeon
,
522 struct dd_function_table
* functions
,
523 const struct gl_config
* glVisual
,
524 __DRIcontext
* driContextPriv
,
525 void *sharedContextPrivate
);
527 void radeonCleanupContext(radeonContextPtr radeon
);
528 GLboolean
radeonUnbindContext(__DRIcontext
* driContextPriv
);
529 void radeon_update_renderbuffers(__DRIcontext
*context
, __DRIdrawable
*drawable
,
530 GLboolean front_only
);
531 GLboolean
radeonMakeCurrent(__DRIcontext
* driContextPriv
,
532 __DRIdrawable
* driDrawPriv
,
533 __DRIdrawable
* driReadPriv
);
534 extern void radeonDestroyContext(__DRIcontext
* driContextPriv
);
535 void radeon_prepare_render(radeonContextPtr radeon
);