src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 struct radeon_context;
  17
  18 #include "radeon_bocs_wrapper.h"
  19
  20 /* This union is used to avoid warnings/miscompilation
  21    with float to uint32_t casts due to strict-aliasing */
  22 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  23
  24 struct radeon_context;
  25 typedef struct radeon_context radeonContextRec;
  26 typedef struct radeon_context *radeonContextPtr;
  27
  28
  29 #define TEX_0   0x1
  30 #define TEX_1   0x2
  31 #define TEX_2   0x4
  32 #define TEX_3   0x8
  33 #define TEX_4   0x10
  34 #define TEX_5   0x20
  35
  36 /* Rasterizing fallbacks */
  37 /* See correponding strings in r200_swtcl.c */
  38 #define RADEON_FALLBACK_TEXTURE         0x0001
  39 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  40 #define RADEON_FALLBACK_STENCIL         0x0004
  41 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  42 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  43 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  44 #define RADEON_FALLBACK_DISABLE         0x0040
  45 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  46 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  47 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  48
  49 #define R200_FALLBACK_TEXTURE           0x01
  50 #define R200_FALLBACK_DRAW_BUFFER       0x02
  51 #define R200_FALLBACK_STENCIL           0x04
  52 #define R200_FALLBACK_RENDER_MODE       0x08
  53 #define R200_FALLBACK_DISABLE           0x10
  54 #define R200_FALLBACK_BORDER_MODE       0x20
  55
  56 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  57 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  58 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  59 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  60 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  61 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  63 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  64 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  65
  66 /* The blit width for texture uploads
  67  */
  68 #define BLIT_WIDTH_BYTES 1024
  69
  70 /* Use the templated vertex format:
  71  */
  72 #define COLOR_IS_RGBA
  73 #define TAG(x) radeon##x
  74 #include "tnl_dd/t_dd_vertex.h"
  75 #undef TAG
  76
  77 #define RADEON_RB_CLASS 0xdeadbeef
  78
  79 struct radeon_renderbuffer
  80 {
  81         struct gl_renderbuffer base;
  82         struct radeon_bo *bo;
  83         unsigned int cpp;
  84         /* unsigned int offset; */
  85         unsigned int pitch;
  86
  87         uint32_t draw_offset; /* FBO */
  88         /* boo Xorg 6.8.2 compat */
  89         int has_surface;
  90
  91         GLuint pf_pending;  /**< sequence number of pending flip */
  92         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  93         __DRIdrawablePrivate *dPriv;
  94 };
  95
  96 struct radeon_framebuffer
  97 {
  98         struct gl_framebuffer base;
  99
 100         struct radeon_renderbuffer *color_rb[2];
 101
 102         GLuint vbl_waited;
 103
 104         /* buffer swap */
 105         int64_t swap_ust;
 106         int64_t swap_missed_ust;
 107
 108         GLuint swap_count;
 109         GLuint swap_missed_count;
 110
 111         /* Drawable page flipping state */
 112         GLboolean pf_active;
 113         GLint pf_current_page;
 114         GLint pf_num_pages;
 115
 116 };
 117
 118
 119 struct radeon_colorbuffer_state {
 120         GLuint clear;
 121         int roundEnable;
 122         struct gl_renderbuffer *rb;
 123         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 124 };
 125
 126 struct radeon_depthbuffer_state {
 127         GLuint clear;
 128         struct gl_renderbuffer *rb;
 129 };
 130
 131 struct radeon_scissor_state {
 132         drm_clip_rect_t rect;
 133         GLboolean enabled;
 134
 135         GLuint numClipRects;    /* Cliprects active */
 136         GLuint numAllocedClipRects;     /* Cliprects available */
 137         drm_clip_rect_t *pClipRects;
 138 };
 139
 140 struct radeon_stencilbuffer_state {
 141         GLuint clear;           /* rb3d_stencilrefmask value */
 142 };
 143
 144 struct radeon_stipple_state {
 145         GLuint mask[32];
 146 };
 147
 148 struct radeon_state_atom {
 149         struct radeon_state_atom *next, *prev;
 150         const char *name;       /* for debug */
 151         int cmd_size;           /* size in bytes */
 152         GLuint idx;
 153         GLuint is_tcl;
 154         GLuint *cmd;            /* one or more cmd's */
 155         GLuint *lastcmd;                /* one or more cmd's */
 156         GLboolean dirty;        /* dirty-mark in emit_state_list */
 157         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 158         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 159 };
 160
 161 struct radeon_hw_state {
 162         /* Head of the linked list of state atoms. */
 163         struct radeon_state_atom atomlist;
 164         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 165         GLboolean is_dirty, all_dirty;
 166 };
 167
 168
 169 /* Texture related */
 170 typedef struct _radeon_texture_image radeon_texture_image;
 171
 172 struct _radeon_texture_image {
 173         struct gl_texture_image base;
 174
 175         /**
 176          * If mt != 0, the image is stored in hardware format in the
 177          * given mipmap tree. In this case, base.Data may point into the
 178          * mapping of the buffer object that contains the mipmap tree.
 179          *
 180          * If mt == 0, the image is stored in normal memory pointed to
 181          * by base.Data.
 182          */
 183         struct _radeon_mipmap_tree *mt;
 184         struct radeon_bo *bo;
 185
 186         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 187         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 188 };
 189
 190
 191 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 192 {
 193         return (radeon_texture_image*)image;
 194 }
 195
 196
 197 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 198
 199 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 200
 201 /* Texture object in locally shared texture space.
 202  */
 203 struct radeon_tex_obj {
 204         struct gl_texture_object base;
 205         struct _radeon_mipmap_tree *mt;
 206
 207         /**
 208          * This is true if we've verified that the mipmap tree above is complete
 209          * and so on.
 210          */
 211         GLboolean validated;
 212
 213         GLuint override_offset;
 214         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 215         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 216         struct radeon_bo *bo;
 217
 218         GLuint pp_txfilter;     /* hardware register values */
 219         GLuint pp_txformat;
 220         GLuint pp_txformat_x;
 221         GLuint pp_txsize;       /* npot only */
 222         GLuint pp_txpitch;      /* npot only */
 223         GLuint pp_border_color;
 224         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 225
 226         GLuint pp_txfilter_1;   /*  r300 */
 227
 228         GLboolean border_fallback;
 229
 230
 231 };
 232
 233 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 234 {
 235         return (radeonTexObj*)texObj;
 236 }
 237
 238 /* Need refcounting on dma buffers:
 239  */
 240 struct radeon_dma_buffer {
 241         int refcount;           /* the number of retained regions in buf */
 242         drmBufPtr buf;
 243 };
 244
 245 struct radeon_aos {
 246         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 247         int offset; /** Offset into buffer object, in bytes */
 248         int components; /** Number of components per vertex */
 249         int stride; /** Stride in dwords (may be 0 for repeating) */
 250         int count; /** Number of vertices */
 251 };
 252
 253 struct radeon_dma {
 254         /* Active dma region.  Allocations for vertices and retained
 255          * regions come from here.  Also used for emitting random vertices,
 256          * these may be flushed by calling flush_current();
 257          */
 258         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 259         int current_used; /** Number of bytes allocated and forgotten about */
 260         int current_vertexptr; /** End of active vertex region */
 261
 262         /**
 263          * If current_vertexptr != current_used then flush must be non-zero.
 264          * flush must be called before non-active vertex allocations can be
 265          * performed.
 266          */
 267         void (*flush) (GLcontext *);
 268
 269         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 270          * for which a DISCARD command is currently queued in the command buffer
 271 .
 272          */
 273         GLuint nr_released_bufs;
 274 };
 275
 276 /* radeon_swtcl.c
 277  */
 278 struct radeon_swtcl_info {
 279
 280         GLuint RenderIndex;
 281         GLuint vertex_size;
 282         GLubyte *verts;
 283
 284         /* Fallback rasterization functions
 285          */
 286         GLuint hw_primitive;
 287         GLenum render_primitive;
 288         GLuint numverts;
 289
 290         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 291         GLuint vertex_attr_count;
 292
 293 };
 294
 295 #define RADEON_MAX_AOS_ARRAYS           16
 296 struct radeon_tcl_info {
 297         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 298         GLuint aos_count;
 299         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 300         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 301 };
 302
 303 struct radeon_ioctl {
 304         GLuint vertex_offset;
 305         struct radeon_bo *bo;
 306         GLuint vertex_size;
 307 };
 308
 309 #define RADEON_MAX_PRIMS 64
 310
 311 struct radeon_prim {
 312         GLuint start;
 313         GLuint end;
 314         GLuint prim;
 315 };
 316
 317 static INLINE GLuint radeonPackColor(GLuint cpp,
 318                                      GLubyte r, GLubyte g,
 319                                      GLubyte b, GLubyte a)
 320 {
 321         switch (cpp) {
 322         case 2:
 323                 return PACK_COLOR_565(r, g, b);
 324         case 4:
 325                 return PACK_COLOR_8888(a, r, g, b);
 326         default:
 327                 return 0;
 328         }
 329 }
 330
 331 #define MAX_CMD_BUF_SZ (16*1024)
 332
 333 #define MAX_DMA_BUF_SZ (64*1024)
 334
 335 struct radeon_store {
 336         GLuint statenr;
 337         GLuint primnr;
 338         char cmd_buf[MAX_CMD_BUF_SZ];
 339         int cmd_used;
 340         int elts_start;
 341 };
 342
 343 struct radeon_dri_mirror {
 344         __DRIcontextPrivate *context;   /* DRI context */
 345         __DRIscreenPrivate *screen;     /* DRI screen */
 346
 347         drm_context_t hwContext;
 348         drm_hw_lock_t *hwLock;
 349         int fd;
 350         int drmMinor;
 351 };
 352
 353 #define DEBUG_TEXTURE   0x001
 354 #define DEBUG_STATE     0x002
 355 #define DEBUG_IOCTL     0x004
 356 #define DEBUG_PRIMS     0x008
 357 #define DEBUG_VERTS     0x010
 358 #define DEBUG_FALLBACKS 0x020
 359 #define DEBUG_VFMT      0x040
 360 #define DEBUG_CODEGEN   0x080
 361 #define DEBUG_VERBOSE   0x100
 362 #define DEBUG_DRI       0x200
 363 #define DEBUG_DMA       0x400
 364 #define DEBUG_SANITY    0x800
 365 #define DEBUG_SYNC      0x1000
 366 #define DEBUG_PIXEL     0x2000
 367 #define DEBUG_MEMORY    0x4000
 368
 369
 370 typedef void (*radeon_tri_func) (radeonContextPtr,
 371                                  radeonVertex *,
 372                                  radeonVertex *, radeonVertex *);
 373
 374 typedef void (*radeon_line_func) (radeonContextPtr,
 375                                   radeonVertex *, radeonVertex *);
 376
 377 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 378
 379 #define RADEON_MAX_BOS 32
 380 struct radeon_state {
 381         struct radeon_colorbuffer_state color;
 382         struct radeon_depthbuffer_state depth;
 383         struct radeon_scissor_state scissor;
 384         struct radeon_stencilbuffer_state stencil;
 385
 386         struct radeon_cs_space_check bos[RADEON_MAX_BOS];
 387         int validated_bo_count;
 388 };
 389
 390 /**
 391  * This structure holds the command buffer while it is being constructed.
 392  *
 393  * The first batch of commands in the buffer is always the state that needs
 394  * to be re-emitted when the context is lost. This batch can be skipped
 395  * otherwise.
 396  */
 397 struct radeon_cmdbuf {
 398         struct radeon_cs_manager    *csm;
 399         struct radeon_cs            *cs;
 400         int size; /** # of dwords total */
 401         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 402 };
 403
 404 struct radeon_context {
 405    GLcontext *glCtx;
 406    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 407
 408    /* Texture object bookkeeping
 409     */
 410    int                   texture_depth;
 411    float                 initialMaxAnisotropy;
 412    uint32_t              texture_row_align;
 413
 414   struct radeon_dma dma;
 415   struct radeon_hw_state hw;
 416    /* Rasterization and vertex state:
 417     */
 418    GLuint TclFallback;
 419    GLuint Fallback;
 420    GLuint NewGLState;
 421    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 422
 423    /* Drawable, cliprect and scissor information */
 424    GLuint numClipRects; /* Cliprects for the draw buffer */
 425    drm_clip_rect_t *pClipRects;
 426    unsigned int lastStamp;
 427    GLboolean lost_context;
 428    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 429
 430    /* Mirrors of some DRI state */
 431    struct radeon_dri_mirror dri;
 432
 433    /* Busy waiting */
 434    GLuint do_usleeps;
 435    GLuint do_irqs;
 436    GLuint irqsEmitted;
 437    drm_radeon_irq_wait_t iw;
 438
 439    /* Derived state - for r300 only */
 440    struct radeon_state state;
 441
 442    struct radeon_swtcl_info swtcl;
 443    struct radeon_tcl_info tcl;
 444    /* Configuration cache
 445     */
 446    driOptionCache optionCache;
 447
 448    struct radeon_cmdbuf cmdbuf;
 449
 450   drm_clip_rect_t fboRect;
 451   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 452   GLboolean front_cliprects;
 453
 454    /**
 455     * Set if rendering has occured to the drawable's front buffer.
 456     *
 457     * This is used in the DRI2 case to detect that glFlush should also copy
 458     * the contents of the fake front buffer to the real front buffer.
 459     */
 460    GLboolean front_buffer_dirty;
 461
 462    /**
 463     * Track whether front-buffer rendering is currently enabled
 464     *
 465     * A separate flag is used to track this in order to support MRT more
 466     * easily.
 467     */
 468    GLboolean is_front_buffer_rendering;
 469
 470   struct {
 471       struct gl_fragment_program *bitmap_fp;
 472       struct gl_vertex_program *passthrough_vp;
 473
 474       struct gl_fragment_program *saved_fp;
 475       GLboolean saved_fp_enable;
 476       struct gl_vertex_program *saved_vp;
 477       GLboolean saved_vp_enable;
 478
 479       GLint saved_vp_x, saved_vp_y;
 480       GLsizei saved_vp_width, saved_vp_height;
 481       GLenum saved_matrix_mode;
 482    } meta;
 483
 484    struct {
 485            void (*get_lock)(radeonContextPtr radeon);
 486            void (*update_viewport_offset)(GLcontext *ctx);
 487            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 488            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 489            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 490            void (*pre_emit_state)(radeonContextPtr rmesa);
 491            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 492            void (*free_context)(GLcontext *ctx);
 493    } vtbl;
 494 };
 495
 496 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 497
 498 static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon)
 499 {
 500         return radeon->dri.context->driDrawablePriv;
 501 }
 502
 503 static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon)
 504 {
 505         return radeon->dri.context->driReadablePriv;
 506 }
 507
 508
 509 /**
 510  * This function takes a float and packs it into a uint32_t
 511  */
 512 static INLINE uint32_t radeonPackFloat32(float fl)
 513 {
 514         union {
 515                 float fl;
 516                 uint32_t u;
 517         } u;
 518
 519         u.fl = fl;
 520         return u.u;
 521 }
 522
 523 /* This is probably wrong for some values, I need to test this
 524  * some more.  Range checking would be a good idea also..
 525  *
 526  * But it works for most things.  I'll fix it later if someone
 527  * else with a better clue doesn't
 528  */
 529 static INLINE uint32_t radeonPackFloat24(float f)
 530 {
 531         float mantissa;
 532         int exponent;
 533         uint32_t float24 = 0;
 534
 535         if (f == 0.0)
 536                 return 0;
 537
 538         mantissa = frexpf(f, &exponent);
 539
 540         /* Handle -ve */
 541         if (mantissa < 0) {
 542                 float24 |= (1 << 23);
 543                 mantissa = mantissa * -1.0;
 544         }
 545         /* Handle exponent, bias of 63 */
 546         exponent += 62;
 547         float24 |= (exponent << 16);
 548         /* Kill 7 LSB of mantissa */
 549         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 550
 551         return float24;
 552 }
 553
 554 GLboolean radeonInitContext(radeonContextPtr radeon,
 555                             struct dd_function_table* functions,
 556                             const __GLcontextModes * glVisual,
 557                             __DRIcontextPrivate * driContextPriv,
 558                             void *sharedContextPrivate);
 559
 560 void radeonCleanupContext(radeonContextPtr radeon);
 561 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 562 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 563 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 564                             __DRIdrawablePrivate * driDrawPriv,
 565                             __DRIdrawablePrivate * driReadPriv);
 566 extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
 567
 568 /* ================================================================
 569  * Debugging:
 570  */
 571 #define DO_DEBUG                1
 572
 573 #if DO_DEBUG
 574 extern int RADEON_DEBUG;
 575 #else
 576 #define RADEON_DEBUG            0
 577 #endif
 578
 579 #endif