src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "tnl/t_context.h"
   8 #include "main/colormac.h"
   9
  10 #include "radeon_debug.h"
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15 #include "swrast/s_context.h"
  16
  17 struct radeon_context;
  18
  19 #include "radeon_bo_gem.h"
  20 #include "radeon_cs_gem.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct swrast_renderbuffer base;
  84
  85         struct radeon_bo *bo;
  86         unsigned int cpp;
  87         /* unsigned int offset; */
  88         unsigned int pitch;
  89
  90         struct radeon_bo *map_bo;
  91         GLbitfield map_mode;
  92         int map_x, map_y, map_w, map_h;
  93         int map_pitch;
  94         void *map_buffer;
  95
  96         uint32_t draw_offset; /* FBO */
  97         /* boo Xorg 6.8.2 compat */
  98         int has_surface;
  99
 100         GLuint pf_pending;  /**< sequence number of pending flip */
 101         __DRIdrawable *dPriv;
 102 };
 103
 104 struct radeon_framebuffer
 105 {
 106         struct gl_framebuffer base;
 107
 108         struct radeon_renderbuffer *color_rb[2];
 109 };
 110
 111
 112 struct radeon_colorbuffer_state {
 113         GLuint clear;
 114         int roundEnable;
 115         struct gl_renderbuffer *rb;
 116         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 117 };
 118
 119 struct radeon_depthbuffer_state {
 120         struct gl_renderbuffer *rb;
 121 };
 122
 123 struct radeon_scissor_state {
 124         drm_clip_rect_t rect;
 125         GLboolean enabled;
 126
 127         GLuint numClipRects;    /* Cliprects active */
 128         GLuint numAllocedClipRects;     /* Cliprects available */
 129         drm_clip_rect_t *pClipRects;
 130 };
 131
 132 struct radeon_state_atom {
 133         struct radeon_state_atom *next, *prev;
 134         const char *name;       /* for debug */
 135         int cmd_size;           /* size in bytes */
 136         GLuint idx;
 137         GLuint is_tcl;
 138         GLuint *cmd;            /* one or more cmd's */
 139         GLuint *lastcmd;                /* one or more cmd's */
 140         GLboolean dirty;        /* dirty-mark in emit_state_list */
 141         int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */
 142         void (*emit) (struct gl_context *, struct radeon_state_atom *atom);
 143 };
 144
 145 struct radeon_hw_state {
 146         /* Head of the linked list of state atoms. */
 147         struct radeon_state_atom atomlist;
 148         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 149         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 150         GLboolean is_dirty, all_dirty;
 151 };
 152
 153
 154 /* Texture related */
 155 typedef struct _radeon_texture_image radeon_texture_image;
 156
 157
 158 /**
 159  * This is a subclass of swrast_texture_image since we use swrast
 160  * for software fallback rendering.
 161  */
 162 struct _radeon_texture_image {
 163         struct swrast_texture_image base;
 164
 165         /**
 166          * If mt != 0, the image is stored in hardware format in the
 167          * given mipmap tree. In this case, base.Data may point into the
 168          * mapping of the buffer object that contains the mipmap tree.
 169          *
 170          * If mt == 0, the image is stored in normal memory pointed to
 171          * by base.Data.
 172          */
 173         struct _radeon_mipmap_tree *mt;
 174         struct radeon_bo *bo;
 175         GLboolean used_as_render_target;
 176 };
 177
 178
 179 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 180 {
 181         return (radeon_texture_image*)image;
 182 }
 183
 184
 185 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 186
 187 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 188
 189 /* Texture object in locally shared texture space.
 190  */
 191 struct radeon_tex_obj {
 192         struct gl_texture_object base;
 193         struct _radeon_mipmap_tree *mt;
 194
 195         /**
 196          * This is true if we've verified that the mipmap tree above is complete
 197          * and so on.
 198          */
 199         GLboolean validated;
 200         /* Minimum LOD to be used during rendering */
 201         unsigned minLod;
 202         /* Miximum LOD to be used during rendering */
 203         unsigned maxLod;
 204
 205         GLuint override_offset;
 206         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 207         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 208         struct radeon_bo *bo;
 209
 210         GLuint pp_txfilter;     /* hardware register values */
 211         GLuint pp_txformat;
 212         GLuint pp_txformat_x;
 213         GLuint pp_txsize;       /* npot only */
 214         GLuint pp_txpitch;      /* npot only */
 215         GLuint pp_border_color;
 216         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 217
 218         GLboolean border_fallback;
 219 };
 220
 221 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 222 {
 223         return (radeonTexObj*)texObj;
 224 }
 225
 226 /* occlusion query */
 227 struct radeon_query_object {
 228         struct gl_query_object Base;
 229         struct radeon_bo *bo;
 230         int curr_offset;
 231         GLboolean emitted_begin;
 232
 233         /* Double linked list of not flushed query objects */
 234         struct radeon_query_object *prev, *next;
 235 };
 236
 237 /* Need refcounting on dma buffers:
 238  */
 239 struct radeon_dma_buffer {
 240         int refcount;           /* the number of retained regions in buf */
 241         drmBufPtr buf;
 242 };
 243
 244 struct radeon_aos {
 245         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 246         int offset; /** Offset into buffer object, in bytes */
 247         int components; /** Number of components per vertex */
 248         int stride; /** Stride in dwords (may be 0 for repeating) */
 249         int count; /** Number of vertices */
 250 };
 251
 252 #define DMA_BO_FREE_TIME 100
 253
 254 struct radeon_dma_bo {
 255   struct radeon_dma_bo *next, *prev;
 256   struct radeon_bo *bo;
 257   int expire_counter;
 258 };
 259
 260 struct radeon_dma {
 261         /* Active dma region.  Allocations for vertices and retained
 262          * regions come from here.  Also used for emitting random vertices,
 263          * these may be flushed by calling flush_current();
 264          */
 265         struct radeon_dma_bo free;
 266         struct radeon_dma_bo wait;
 267         struct radeon_dma_bo reserved;
 268         size_t current_used; /** Number of bytes allocated and forgotten about */
 269         size_t current_vertexptr; /** End of active vertex region */
 270         size_t minimum_size;
 271
 272         /**
 273          * If current_vertexptr != current_used then flush must be non-zero.
 274          * flush must be called before non-active vertex allocations can be
 275          * performed.
 276          */
 277         void (*flush) (struct gl_context *);
 278 };
 279
 280 /* radeon_swtcl.c
 281  */
 282 struct radeon_swtcl_info {
 283
 284         GLuint RenderIndex;
 285         GLuint vertex_size;
 286         GLubyte *verts;
 287
 288         /* Fallback rasterization functions
 289          */
 290         GLuint hw_primitive;
 291         GLenum render_primitive;
 292         GLuint numverts;
 293
 294         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 295         GLuint vertex_attr_count;
 296
 297         GLuint emit_prediction;
 298         struct radeon_bo *bo;
 299 };
 300
 301 #define RADEON_MAX_AOS_ARRAYS           16
 302 struct radeon_tcl_info {
 303         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 304         GLuint aos_count;
 305         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 306         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 307 };
 308
 309 struct radeon_ioctl {
 310         GLuint vertex_offset;
 311         GLuint vertex_max;
 312         struct radeon_bo *bo;
 313         GLuint vertex_size;
 314 };
 315
 316 #define RADEON_MAX_PRIMS 64
 317
 318 struct radeon_prim {
 319         GLuint start;
 320         GLuint end;
 321         GLuint prim;
 322 };
 323
 324 static INLINE GLuint radeonPackColor(GLuint cpp,
 325                                      GLubyte r, GLubyte g,
 326                                      GLubyte b, GLubyte a)
 327 {
 328         switch (cpp) {
 329         case 2:
 330                 return PACK_COLOR_565(r, g, b);
 331         case 4:
 332                 return PACK_COLOR_8888(a, r, g, b);
 333         default:
 334                 return 0;
 335         }
 336 }
 337
 338 #define MAX_CMD_BUF_SZ (16*1024)
 339
 340 #define MAX_DMA_BUF_SZ (64*1024)
 341
 342 struct radeon_store {
 343         GLuint statenr;
 344         GLuint primnr;
 345         char cmd_buf[MAX_CMD_BUF_SZ];
 346         int cmd_used;
 347         int elts_start;
 348 };
 349
 350 struct radeon_dri_mirror {
 351         __DRIcontext *context;  /* DRI context */
 352         __DRIscreen *screen;    /* DRI screen */
 353
 354         drm_context_t hwContext;
 355         drm_hw_lock_t *hwLock;
 356         int hwLockCount;
 357         int fd;
 358         int drmMinor;
 359 };
 360
 361 typedef void (*radeon_tri_func) (radeonContextPtr,
 362                                  radeonVertex *,
 363                                  radeonVertex *, radeonVertex *);
 364
 365 typedef void (*radeon_line_func) (radeonContextPtr,
 366                                   radeonVertex *, radeonVertex *);
 367
 368 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 369
 370 #define RADEON_MAX_BOS 32
 371 struct radeon_state {
 372         struct radeon_colorbuffer_state color;
 373         struct radeon_depthbuffer_state depth;
 374         struct radeon_scissor_state scissor;
 375 };
 376
 377 /**
 378  * This structure holds the command buffer while it is being constructed.
 379  *
 380  * The first batch of commands in the buffer is always the state that needs
 381  * to be re-emitted when the context is lost. This batch can be skipped
 382  * otherwise.
 383  */
 384 struct radeon_cmdbuf {
 385         struct radeon_cs_manager    *csm;
 386         struct radeon_cs            *cs;
 387         int size; /** # of dwords total */
 388         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 389 };
 390
 391 struct radeon_context {
 392    struct gl_context *glCtx;
 393    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 394
 395    /* Texture object bookkeeping
 396     */
 397    int                   texture_depth;
 398    float                 initialMaxAnisotropy;
 399    uint32_t              texture_row_align;
 400    uint32_t              texture_rect_row_align;
 401    uint32_t              texture_compressed_row_align;
 402
 403   struct radeon_dma dma;
 404   struct radeon_hw_state hw;
 405    /* Rasterization and vertex state:
 406     */
 407    GLuint TclFallback;
 408    GLuint Fallback;
 409    GLuint NewGLState;
 410    GLbitfield64 tnl_index_bitset;       /* index of bits for last tnl_install_attrs */
 411
 412    /* Drawable information */
 413    unsigned int lastStamp;
 414    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 415
 416    /* Mirrors of some DRI state */
 417    struct radeon_dri_mirror dri;
 418
 419    /* Busy waiting */
 420    GLuint do_usleeps;
 421    GLuint do_irqs;
 422    GLuint irqsEmitted;
 423    drm_radeon_irq_wait_t iw;
 424
 425    /* Derived state - for r300 only */
 426    struct radeon_state state;
 427
 428    struct radeon_swtcl_info swtcl;
 429    struct radeon_tcl_info tcl;
 430    /* Configuration cache
 431     */
 432    driOptionCache optionCache;
 433
 434    struct radeon_cmdbuf cmdbuf;
 435
 436    struct radeon_debug debug;
 437
 438   drm_clip_rect_t fboRect;
 439   GLboolean front_cliprects;
 440
 441    /**
 442     * Set if rendering has occured to the drawable's front buffer.
 443     *
 444     * This is used in the DRI2 case to detect that glFlush should also copy
 445     * the contents of the fake front buffer to the real front buffer.
 446     */
 447    GLboolean front_buffer_dirty;
 448
 449    /**
 450     * Track whether front-buffer rendering is currently enabled
 451     *
 452     * A separate flag is used to track this in order to support MRT more
 453     * easily.
 454     */
 455    GLboolean is_front_buffer_rendering;
 456
 457    /**
 458     * Track whether front-buffer is the current read target.
 459     *
 460     * This is closely associated with is_front_buffer_rendering, but may
 461     * be set separately.  The DRI2 fake front buffer must be referenced
 462     * either way.
 463     */
 464    GLboolean is_front_buffer_reading;
 465
 466    struct {
 467         struct radeon_query_object *current;
 468         struct radeon_state_atom queryobj;
 469    } query;
 470
 471    struct {
 472            void (*get_lock)(radeonContextPtr radeon);
 473            void (*update_viewport_offset)(struct gl_context *ctx);
 474            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 475            void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);
 476            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 477            void (*pre_emit_state)(radeonContextPtr rmesa);
 478            void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);
 479            void (*free_context)(struct gl_context *ctx);
 480            void (*emit_query_finish)(radeonContextPtr radeon);
 481            void (*update_scissor)(struct gl_context *ctx);
 482            unsigned (*check_blit)(gl_format mesa_format, uint32_t dst_pitch);
 483            unsigned (*blit)(struct gl_context *ctx,
 484                         struct radeon_bo *src_bo,
 485                         intptr_t src_offset,
 486                         gl_format src_mesaformat,
 487                         unsigned src_pitch,
 488                         unsigned src_width,
 489                         unsigned src_height,
 490                         unsigned src_x_offset,
 491                         unsigned src_y_offset,
 492                         struct radeon_bo *dst_bo,
 493                         intptr_t dst_offset,
 494                         gl_format dst_mesaformat,
 495                         unsigned dst_pitch,
 496                         unsigned dst_width,
 497                         unsigned dst_height,
 498                         unsigned dst_x_offset,
 499                         unsigned dst_y_offset,
 500                         unsigned reg_width,
 501                         unsigned reg_height,
 502                         unsigned flip_y);
 503            unsigned (*is_format_renderable)(gl_format mesa_format);
 504    } vtbl;
 505 };
 506
 507 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 508
 509 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 510 {
 511         return radeon->dri.context->driDrawablePriv;
 512 }
 513
 514 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 515 {
 516         return radeon->dri.context->driReadablePriv;
 517 }
 518
 519 GLboolean radeonInitContext(radeonContextPtr radeon,
 520                             struct dd_function_table* functions,
 521                             const struct gl_config * glVisual,
 522                             __DRIcontext * driContextPriv,
 523                             void *sharedContextPrivate);
 524
 525 void radeonCleanupContext(radeonContextPtr radeon);
 526 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 527 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 528                                  GLboolean front_only);
 529 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 530                             __DRIdrawable * driDrawPriv,
 531                             __DRIdrawable * driReadPriv);
 532 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 533 void radeon_prepare_render(radeonContextPtr radeon);
 534
 535 #endif