src/mesa/drivers/dri/radeon/radeon_compat.c

   1 /* $XFree86$ */
   2 /**************************************************************************
   3
   4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
   5                Tungsten Graphics Inc., Austin, Texas.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining a
  10 copy of this software and associated documentation files (the "Software"),
  11 to deal in the Software without restriction, including without limitation
  12 on the rights to use, copy, modify, merge, publish, distribute, sub
  13 license, and/or sell copies of the Software, and to permit persons to whom
  14 the Software is furnished to do so, subject to the following conditions:
  15
  16 The above copyright notice and this permission notice (including the next
  17 paragraph) shall be included in all copies or substantial portions of the
  18 Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  26 USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38
  39 #include "radeon_context.h"
  40 #include "radeon_state.h"
  41 #include "radeon_ioctl.h"
  42
  43
  44 static struct {
  45         int start;
  46         int len;
  47         const char *name;
  48 } packet[RADEON_MAX_STATE_PACKETS] = {
  49         { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
  50         { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
  51         { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
  52         { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
  53         { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
  54         { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
  55         { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
  56         { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
  57         { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
  58         { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
  59         { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
  60         { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
  61         { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
  62         { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
  63         { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
  64         { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
  65         { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
  66         { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
  67         { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
  68         { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
  69         { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
  70 };
  71
  72
  73 static void radeonCompatEmitPacket( radeonContextPtr rmesa,
  74                                     struct radeon_state_atom *state )
  75 {
  76    drm_radeon_sarea_t *sarea = rmesa->sarea;
  77    drm_radeon_context_regs_t *ctx = &sarea->context_state;
  78    drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0];
  79    drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1];
  80    int i;
  81    int *buf = state->cmd;
  82
  83    for ( i = 0 ; i < state->cmd_size ; ) {
  84       drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++];
  85
  86       if (RADEON_DEBUG & DEBUG_STATE)
  87          fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id,
  88                  packet[(int)header->packet.packet_id].name);
  89
  90       switch (header->packet.packet_id) {
  91       case RADEON_EMIT_PP_MISC:
  92          ctx->pp_misc = buf[i++];
  93          ctx->pp_fog_color = buf[i++];
  94          ctx->re_solid_color = buf[i++];
  95          ctx->rb3d_blendcntl = buf[i++];
  96          ctx->rb3d_depthoffset = buf[i++];
  97          ctx->rb3d_depthpitch = buf[i++];
  98          ctx->rb3d_zstencilcntl = buf[i++];
  99          sarea->dirty |= RADEON_UPLOAD_CONTEXT;
 100          break;
 101       case RADEON_EMIT_PP_CNTL:
 102          ctx->pp_cntl = buf[i++];
 103          ctx->rb3d_cntl = buf[i++];
 104          ctx->rb3d_coloroffset = buf[i++];
 105          sarea->dirty |= RADEON_UPLOAD_CONTEXT;
 106          break;
 107       case RADEON_EMIT_RB3D_COLORPITCH:
 108          ctx->rb3d_colorpitch = buf[i++];
 109          sarea->dirty |= RADEON_UPLOAD_CONTEXT;
 110          break;
 111       case RADEON_EMIT_RE_LINE_PATTERN:
 112          ctx->re_line_pattern = buf[i++];
 113          ctx->re_line_state = buf[i++];
 114          sarea->dirty |= RADEON_UPLOAD_LINE;
 115          break;
 116       case RADEON_EMIT_SE_LINE_WIDTH:
 117          ctx->se_line_width = buf[i++];
 118          sarea->dirty |= RADEON_UPLOAD_LINE;
 119          break;
 120       case RADEON_EMIT_PP_LUM_MATRIX:
 121          ctx->pp_lum_matrix = buf[i++];
 122          sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
 123          break;
 124       case RADEON_EMIT_PP_ROT_MATRIX_0:
 125          ctx->pp_rot_matrix_0 = buf[i++];
 126          ctx->pp_rot_matrix_1 = buf[i++];
 127          sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
 128          break;
 129       case RADEON_EMIT_RB3D_STENCILREFMASK:
 130          ctx->rb3d_stencilrefmask = buf[i++];
 131          ctx->rb3d_ropcntl = buf[i++];
 132          ctx->rb3d_planemask = buf[i++];
 133          sarea->dirty |= RADEON_UPLOAD_MASKS;
 134          break;
 135       case RADEON_EMIT_SE_VPORT_XSCALE:
 136          ctx->se_vport_xscale = buf[i++];
 137          ctx->se_vport_xoffset = buf[i++];
 138          ctx->se_vport_yscale = buf[i++];
 139          ctx->se_vport_yoffset = buf[i++];
 140          ctx->se_vport_zscale = buf[i++];
 141          ctx->se_vport_zoffset = buf[i++];
 142          sarea->dirty |= RADEON_UPLOAD_VIEWPORT;
 143          break;
 144       case RADEON_EMIT_SE_CNTL:
 145          ctx->se_cntl = buf[i++];
 146          ctx->se_coord_fmt = buf[i++];
 147          sarea->dirty |= RADEON_UPLOAD_CONTEXT | RADEON_UPLOAD_VERTFMT;
 148          break;
 149       case RADEON_EMIT_SE_CNTL_STATUS:
 150          ctx->se_cntl_status = buf[i++];
 151          sarea->dirty |= RADEON_UPLOAD_SETUP;
 152          break;
 153       case RADEON_EMIT_RE_MISC:
 154          ctx->re_misc = buf[i++];
 155          sarea->dirty |= RADEON_UPLOAD_MISC;
 156          break;
 157       case RADEON_EMIT_PP_TXFILTER_0:
 158          tex0->pp_txfilter = buf[i++];
 159          tex0->pp_txformat = buf[i++];
 160          tex0->pp_txoffset = buf[i++];
 161          tex0->pp_txcblend = buf[i++];
 162          tex0->pp_txablend = buf[i++];
 163          tex0->pp_tfactor = buf[i++];
 164          sarea->dirty |= RADEON_UPLOAD_TEX0;
 165          break;
 166       case RADEON_EMIT_PP_BORDER_COLOR_0:
 167          tex0->pp_border_color = buf[i++];
 168          sarea->dirty |= RADEON_UPLOAD_TEX0;
 169          break;
 170       case RADEON_EMIT_PP_TXFILTER_1:
 171          tex1->pp_txfilter = buf[i++];
 172          tex1->pp_txformat = buf[i++];
 173          tex1->pp_txoffset = buf[i++];
 174          tex1->pp_txcblend = buf[i++];
 175          tex1->pp_txablend = buf[i++];
 176          tex1->pp_tfactor = buf[i++];
 177          sarea->dirty |= RADEON_UPLOAD_TEX1;
 178          break;
 179       case RADEON_EMIT_PP_BORDER_COLOR_1:
 180          tex1->pp_border_color = buf[i++];
 181          sarea->dirty |= RADEON_UPLOAD_TEX1;
 182          break;
 183
 184       case RADEON_EMIT_SE_ZBIAS_FACTOR:
 185          i++;
 186          i++;
 187          break;
 188
 189       case RADEON_EMIT_PP_TXFILTER_2:
 190       case RADEON_EMIT_PP_BORDER_COLOR_2:
 191       case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
 192       case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
 193       default:
 194          /* These states aren't understood by radeon drm 1.1 */
 195          fprintf(stderr, "Tried to emit unsupported state\n");
 196          return;
 197       }
 198    }
 199 }
 200
 201
 202
 203 static void radeonCompatEmitStateLocked( radeonContextPtr rmesa )
 204 {
 205    struct radeon_state_atom *atom;
 206
 207    if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
 208       fprintf(stderr, "%s\n", __FUNCTION__);
 209
 210    if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
 211       return;
 212
 213    foreach(atom, &rmesa->hw.atomlist) {
 214       if (rmesa->hw.all_dirty)
 215          atom->dirty = GL_TRUE;
 216       if (atom->is_tcl)
 217          atom->dirty = GL_FALSE;
 218       if (atom->dirty)
 219          radeonCompatEmitPacket(rmesa, atom);
 220    }
 221
 222    rmesa->hw.is_dirty = GL_FALSE;
 223    rmesa->hw.all_dirty = GL_FALSE;
 224 }
 225
 226
 227 static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa,
 228                                              GLuint hw_primitive,
 229                                              GLuint nverts,
 230                                              drm_clip_rect_t *pbox,
 231                                              GLuint nbox )
 232 {
 233    int i;
 234
 235    for ( i = 0 ; i < nbox ; ) {
 236       int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox );
 237       drm_clip_rect_t *b = rmesa->sarea->boxes;
 238       drm_radeon_vertex_t vtx;
 239
 240       rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS;
 241       rmesa->sarea->nbox = nr - i;
 242
 243       for ( ; i < nr ; i++)
 244          *b++ = pbox[i];
 245
 246       if (RADEON_DEBUG & DEBUG_IOCTL)
 247          fprintf(stderr,
 248                  "RadeonFlushVertexBuffer: prim %x buf %d verts %d "
 249                  "disc %d nbox %d\n",
 250                  hw_primitive,
 251                  rmesa->dma.current.buf->buf->idx,
 252                  nverts,
 253                  nr == nbox,
 254                  rmesa->sarea->nbox );
 255
 256       vtx.prim = hw_primitive;
 257       vtx.idx = rmesa->dma.current.buf->buf->idx;
 258       vtx.count = nverts;
 259       vtx.discard = (nr == nbox);
 260
 261       drmCommandWrite( rmesa->dri.fd,
 262                        DRM_RADEON_VERTEX,
 263                        &vtx, sizeof(vtx));
 264    }
 265 }
 266
 267
 268
 269 /* No 'start' for 1.1 vertices ioctl: only one vertex prim/buffer!
 270  */
 271 void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
 272                                 GLuint vertex_format,
 273                                 GLuint hw_primitive,
 274                                 GLuint nrverts )
 275 {
 276    if (RADEON_DEBUG & DEBUG_IOCTL)
 277       fprintf(stderr, "%s\n", __FUNCTION__);
 278
 279    LOCK_HARDWARE( rmesa );
 280
 281    radeonCompatEmitStateLocked( rmesa );
 282    rmesa->sarea->vc_format = vertex_format;
 283
 284    if (rmesa->state.scissor.enabled) {
 285       radeonCompatEmitPrimitiveLocked( rmesa,
 286                                        hw_primitive,
 287                                        nrverts,
 288                                        rmesa->state.scissor.pClipRects,
 289                                        rmesa->state.scissor.numClipRects );
 290    }
 291    else {
 292       radeonCompatEmitPrimitiveLocked( rmesa,
 293                                        hw_primitive,
 294                                        nrverts,
 295                                        rmesa->pClipRects,
 296                                        rmesa->numClipRects );
 297    }
 298
 299
 300    UNLOCK_HARDWARE( rmesa );
 301 }
 302