2 /**************************************************************************
4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
5 Tungsten Graphics Inc., Austin, Texas.
9 Permission is hereby granted, free of charge, to any person obtaining a
10 copy of this software and associated documentation files (the "Software"),
11 to deal in the Software without restriction, including without limitation
12 on the rights to use, copy, modify, merge, publish, distribute, sub
13 license, and/or sell copies of the Software, and to permit persons to whom
14 the Software is furnished to do so, subject to the following conditions:
16 The above copyright notice and this permission notice (including the next
17 paragraph) shall be included in all copies or substantial portions of the
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
26 USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "radeon_context.h"
40 #include "radeon_state.h"
41 #include "radeon_ioctl.h"
48 } packet
[RADEON_MAX_STATE_PACKETS
] = {
49 { RADEON_PP_MISC
,7,"RADEON_PP_MISC" },
50 { RADEON_PP_CNTL
,3,"RADEON_PP_CNTL" },
51 { RADEON_RB3D_COLORPITCH
,1,"RADEON_RB3D_COLORPITCH" },
52 { RADEON_RE_LINE_PATTERN
,2,"RADEON_RE_LINE_PATTERN" },
53 { RADEON_SE_LINE_WIDTH
,1,"RADEON_SE_LINE_WIDTH" },
54 { RADEON_PP_LUM_MATRIX
,1,"RADEON_PP_LUM_MATRIX" },
55 { RADEON_PP_ROT_MATRIX_0
,2,"RADEON_PP_ROT_MATRIX_0" },
56 { RADEON_RB3D_STENCILREFMASK
,3,"RADEON_RB3D_STENCILREFMASK" },
57 { RADEON_SE_VPORT_XSCALE
,6,"RADEON_SE_VPORT_XSCALE" },
58 { RADEON_SE_CNTL
,2,"RADEON_SE_CNTL" },
59 { RADEON_SE_CNTL_STATUS
,1,"RADEON_SE_CNTL_STATUS" },
60 { RADEON_RE_MISC
,1,"RADEON_RE_MISC" },
61 { RADEON_PP_TXFILTER_0
,6,"RADEON_PP_TXFILTER_0" },
62 { RADEON_PP_BORDER_COLOR_0
,1,"RADEON_PP_BORDER_COLOR_0" },
63 { RADEON_PP_TXFILTER_1
,6,"RADEON_PP_TXFILTER_1" },
64 { RADEON_PP_BORDER_COLOR_1
,1,"RADEON_PP_BORDER_COLOR_1" },
65 { RADEON_PP_TXFILTER_2
,6,"RADEON_PP_TXFILTER_2" },
66 { RADEON_PP_BORDER_COLOR_2
,1,"RADEON_PP_BORDER_COLOR_2" },
67 { RADEON_SE_ZBIAS_FACTOR
,2,"RADEON_SE_ZBIAS_FACTOR" },
68 { RADEON_SE_TCL_OUTPUT_VTX_FMT
,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
69 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
73 static void radeonCompatEmitPacket( radeonContextPtr rmesa
,
74 struct radeon_state_atom
*state
)
76 drm_radeon_sarea_t
*sarea
= rmesa
->sarea
;
77 drm_radeon_context_regs_t
*ctx
= &sarea
->context_state
;
78 drm_radeon_texture_regs_t
*tex0
= &sarea
->tex_state
[0];
79 drm_radeon_texture_regs_t
*tex1
= &sarea
->tex_state
[1];
81 int *buf
= state
->cmd
;
83 for ( i
= 0 ; i
< state
->cmd_size
; ) {
84 drm_radeon_cmd_header_t
*header
= (drm_radeon_cmd_header_t
*)&buf
[i
++];
86 if (RADEON_DEBUG
& DEBUG_STATE
)
87 fprintf(stderr
, "%s %d: %s\n", __FUNCTION__
, header
->packet
.packet_id
,
88 packet
[(int)header
->packet
.packet_id
].name
);
90 switch (header
->packet
.packet_id
) {
91 case RADEON_EMIT_PP_MISC
:
92 ctx
->pp_misc
= buf
[i
++];
93 ctx
->pp_fog_color
= buf
[i
++];
94 ctx
->re_solid_color
= buf
[i
++];
95 ctx
->rb3d_blendcntl
= buf
[i
++];
96 ctx
->rb3d_depthoffset
= buf
[i
++];
97 ctx
->rb3d_depthpitch
= buf
[i
++];
98 ctx
->rb3d_zstencilcntl
= buf
[i
++];
99 sarea
->dirty
|= RADEON_UPLOAD_CONTEXT
;
101 case RADEON_EMIT_PP_CNTL
:
102 ctx
->pp_cntl
= buf
[i
++];
103 ctx
->rb3d_cntl
= buf
[i
++];
104 ctx
->rb3d_coloroffset
= buf
[i
++];
105 sarea
->dirty
|= RADEON_UPLOAD_CONTEXT
;
107 case RADEON_EMIT_RB3D_COLORPITCH
:
108 ctx
->rb3d_colorpitch
= buf
[i
++];
109 sarea
->dirty
|= RADEON_UPLOAD_CONTEXT
;
111 case RADEON_EMIT_RE_LINE_PATTERN
:
112 ctx
->re_line_pattern
= buf
[i
++];
113 ctx
->re_line_state
= buf
[i
++];
114 sarea
->dirty
|= RADEON_UPLOAD_LINE
;
116 case RADEON_EMIT_SE_LINE_WIDTH
:
117 ctx
->se_line_width
= buf
[i
++];
118 sarea
->dirty
|= RADEON_UPLOAD_LINE
;
120 case RADEON_EMIT_PP_LUM_MATRIX
:
121 ctx
->pp_lum_matrix
= buf
[i
++];
122 sarea
->dirty
|= RADEON_UPLOAD_BUMPMAP
;
124 case RADEON_EMIT_PP_ROT_MATRIX_0
:
125 ctx
->pp_rot_matrix_0
= buf
[i
++];
126 ctx
->pp_rot_matrix_1
= buf
[i
++];
127 sarea
->dirty
|= RADEON_UPLOAD_BUMPMAP
;
129 case RADEON_EMIT_RB3D_STENCILREFMASK
:
130 ctx
->rb3d_stencilrefmask
= buf
[i
++];
131 ctx
->rb3d_ropcntl
= buf
[i
++];
132 ctx
->rb3d_planemask
= buf
[i
++];
133 sarea
->dirty
|= RADEON_UPLOAD_MASKS
;
135 case RADEON_EMIT_SE_VPORT_XSCALE
:
136 ctx
->se_vport_xscale
= buf
[i
++];
137 ctx
->se_vport_xoffset
= buf
[i
++];
138 ctx
->se_vport_yscale
= buf
[i
++];
139 ctx
->se_vport_yoffset
= buf
[i
++];
140 ctx
->se_vport_zscale
= buf
[i
++];
141 ctx
->se_vport_zoffset
= buf
[i
++];
142 sarea
->dirty
|= RADEON_UPLOAD_VIEWPORT
;
144 case RADEON_EMIT_SE_CNTL
:
145 ctx
->se_cntl
= buf
[i
++];
146 ctx
->se_coord_fmt
= buf
[i
++];
147 sarea
->dirty
|= RADEON_UPLOAD_CONTEXT
| RADEON_UPLOAD_VERTFMT
;
149 case RADEON_EMIT_SE_CNTL_STATUS
:
150 ctx
->se_cntl_status
= buf
[i
++];
151 sarea
->dirty
|= RADEON_UPLOAD_SETUP
;
153 case RADEON_EMIT_RE_MISC
:
154 ctx
->re_misc
= buf
[i
++];
155 sarea
->dirty
|= RADEON_UPLOAD_MISC
;
157 case RADEON_EMIT_PP_TXFILTER_0
:
158 tex0
->pp_txfilter
= buf
[i
++];
159 tex0
->pp_txformat
= buf
[i
++];
160 tex0
->pp_txoffset
= buf
[i
++];
161 tex0
->pp_txcblend
= buf
[i
++];
162 tex0
->pp_txablend
= buf
[i
++];
163 tex0
->pp_tfactor
= buf
[i
++];
164 sarea
->dirty
|= RADEON_UPLOAD_TEX0
;
166 case RADEON_EMIT_PP_BORDER_COLOR_0
:
167 tex0
->pp_border_color
= buf
[i
++];
168 sarea
->dirty
|= RADEON_UPLOAD_TEX0
;
170 case RADEON_EMIT_PP_TXFILTER_1
:
171 tex1
->pp_txfilter
= buf
[i
++];
172 tex1
->pp_txformat
= buf
[i
++];
173 tex1
->pp_txoffset
= buf
[i
++];
174 tex1
->pp_txcblend
= buf
[i
++];
175 tex1
->pp_txablend
= buf
[i
++];
176 tex1
->pp_tfactor
= buf
[i
++];
177 sarea
->dirty
|= RADEON_UPLOAD_TEX1
;
179 case RADEON_EMIT_PP_BORDER_COLOR_1
:
180 tex1
->pp_border_color
= buf
[i
++];
181 sarea
->dirty
|= RADEON_UPLOAD_TEX1
;
184 case RADEON_EMIT_SE_ZBIAS_FACTOR
:
189 case RADEON_EMIT_PP_TXFILTER_2
:
190 case RADEON_EMIT_PP_BORDER_COLOR_2
:
191 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT
:
192 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED
:
194 /* These states aren't understood by radeon drm 1.1 */
195 fprintf(stderr
, "Tried to emit unsupported state\n");
203 static void radeonCompatEmitStateLocked( radeonContextPtr rmesa
)
205 struct radeon_state_atom
*atom
;
207 if (RADEON_DEBUG
& (DEBUG_STATE
|DEBUG_PRIMS
))
208 fprintf(stderr
, "%s\n", __FUNCTION__
);
210 if (!rmesa
->hw
.is_dirty
&& !rmesa
->hw
.all_dirty
)
213 foreach(atom
, &rmesa
->hw
.atomlist
) {
214 if (rmesa
->hw
.all_dirty
)
215 atom
->dirty
= GL_TRUE
;
217 atom
->dirty
= GL_FALSE
;
219 radeonCompatEmitPacket(rmesa
, atom
);
222 rmesa
->hw
.is_dirty
= GL_FALSE
;
223 rmesa
->hw
.all_dirty
= GL_FALSE
;
227 static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa
,
230 drm_clip_rect_t
*pbox
,
235 for ( i
= 0 ; i
< nbox
; ) {
236 int nr
= MIN2( i
+ RADEON_NR_SAREA_CLIPRECTS
, nbox
);
237 drm_clip_rect_t
*b
= rmesa
->sarea
->boxes
;
238 drm_radeon_vertex_t vtx
;
240 rmesa
->sarea
->dirty
|= RADEON_UPLOAD_CLIPRECTS
;
241 rmesa
->sarea
->nbox
= nr
- i
;
243 for ( ; i
< nr
; i
++)
246 if (RADEON_DEBUG
& DEBUG_IOCTL
)
248 "RadeonFlushVertexBuffer: prim %x buf %d verts %d "
251 rmesa
->dma
.current
.buf
->buf
->idx
,
254 rmesa
->sarea
->nbox
);
256 vtx
.prim
= hw_primitive
;
257 vtx
.idx
= rmesa
->dma
.current
.buf
->buf
->idx
;
259 vtx
.discard
= (nr
== nbox
);
261 drmCommandWrite( rmesa
->dri
.fd
,
269 /* No 'start' for 1.1 vertices ioctl: only one vertex prim/buffer!
271 void radeonCompatEmitPrimitive( radeonContextPtr rmesa
,
272 GLuint vertex_format
,
276 if (RADEON_DEBUG
& DEBUG_IOCTL
)
277 fprintf(stderr
, "%s\n", __FUNCTION__
);
279 LOCK_HARDWARE( rmesa
);
281 radeonCompatEmitStateLocked( rmesa
);
282 rmesa
->sarea
->vc_format
= vertex_format
;
284 if (rmesa
->state
.scissor
.enabled
) {
285 radeonCompatEmitPrimitiveLocked( rmesa
,
288 rmesa
->state
.scissor
.pClipRects
,
289 rmesa
->state
.scissor
.numClipRects
);
292 radeonCompatEmitPrimitiveLocked( rmesa
,
296 rmesa
->numClipRects
);
300 UNLOCK_HARDWARE( rmesa
);