src/mesa/drivers/dri/radeon/radeon_compat.c

   1 /**************************************************************************
   2
   3 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
   4                Tungsten Graphics Inc., Austin, Texas.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining a
   9 copy of this software and associated documentation files (the "Software"),
  10 to deal in the Software without restriction, including without limitation
  11 on the rights to use, copy, modify, merge, publish, distribute, sub
  12 license, and/or sell copies of the Software, and to permit persons to whom
  13 the Software is furnished to do so, subject to the following conditions:
  14
  15 The above copyright notice and this permission notice (including the next
  16 paragraph) shall be included in all copies or substantial portions of the
  17 Software.
  18
  19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  22 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  23 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  24 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  25 USE OR OTHER DEALINGS IN THE SOFTWARE.
  26
  27 **************************************************************************/
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keith@tungstengraphics.com>
  32  *
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37
  38 #include "radeon_context.h"
  39 #include "radeon_state.h"
  40 #include "radeon_ioctl.h"
  41
  42
  43 static struct {
  44         int start;
  45         int len;
  46         const char *name;
  47 } packet[RADEON_MAX_STATE_PACKETS] = {
  48         { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
  49         { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
  50         { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
  51         { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
  52         { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
  53         { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
  54         { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
  55         { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
  56         { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
  57         { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
  58         { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
  59         { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
  60         { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
  61         { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
  62         { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
  63         { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
  64         { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
  65         { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
  66         { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
  67         { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
  68         { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
  69 };
  70
  71
  72 static void radeonCompatEmitPacket( radeonContextPtr rmesa,
  73                                     struct radeon_state_atom *state )
  74 {
  75    drm_radeon_sarea_t *sarea = rmesa->sarea;
  76    drm_radeon_context_regs_t *ctx = &sarea->context_state;
  77    drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0];
  78    drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1];
  79    int i;
  80    int *buf = state->cmd;
  81
  82    for ( i = 0 ; i < state->cmd_size ; ) {
  83       drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++];
  84
  85       if (RADEON_DEBUG & DEBUG_STATE)
  86          fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id,
  87                  packet[(int)header->packet.packet_id].name);
  88
  89       switch (header->packet.packet_id) {
  90       case RADEON_EMIT_PP_MISC:
  91          ctx->pp_misc = buf[i++];
  92          ctx->pp_fog_color = buf[i++];
  93          ctx->re_solid_color = buf[i++];
  94          ctx->rb3d_blendcntl = buf[i++];
  95          ctx->rb3d_depthoffset = buf[i++];
  96          ctx->rb3d_depthpitch = buf[i++];
  97          ctx->rb3d_zstencilcntl = buf[i++];
  98          sarea->dirty |= RADEON_UPLOAD_CONTEXT;
  99          break;
 100       case RADEON_EMIT_PP_CNTL:
 101          ctx->pp_cntl = buf[i++];
 102          ctx->rb3d_cntl = buf[i++];
 103          ctx->rb3d_coloroffset = buf[i++];
 104          sarea->dirty |= RADEON_UPLOAD_CONTEXT;
 105          break;
 106       case RADEON_EMIT_RB3D_COLORPITCH:
 107          ctx->rb3d_colorpitch = buf[i++];
 108          sarea->dirty |= RADEON_UPLOAD_CONTEXT;
 109          break;
 110       case RADEON_EMIT_RE_LINE_PATTERN:
 111          ctx->re_line_pattern = buf[i++];
 112          ctx->re_line_state = buf[i++];
 113          sarea->dirty |= RADEON_UPLOAD_LINE;
 114          break;
 115       case RADEON_EMIT_SE_LINE_WIDTH:
 116          ctx->se_line_width = buf[i++];
 117          sarea->dirty |= RADEON_UPLOAD_LINE;
 118          break;
 119       case RADEON_EMIT_PP_LUM_MATRIX:
 120          ctx->pp_lum_matrix = buf[i++];
 121          sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
 122          break;
 123       case RADEON_EMIT_PP_ROT_MATRIX_0:
 124          ctx->pp_rot_matrix_0 = buf[i++];
 125          ctx->pp_rot_matrix_1 = buf[i++];
 126          sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
 127          break;
 128       case RADEON_EMIT_RB3D_STENCILREFMASK:
 129          ctx->rb3d_stencilrefmask = buf[i++];
 130          ctx->rb3d_ropcntl = buf[i++];
 131          ctx->rb3d_planemask = buf[i++];
 132          sarea->dirty |= RADEON_UPLOAD_MASKS;
 133          break;
 134       case RADEON_EMIT_SE_VPORT_XSCALE:
 135          ctx->se_vport_xscale = buf[i++];
 136          ctx->se_vport_xoffset = buf[i++];
 137          ctx->se_vport_yscale = buf[i++];
 138          ctx->se_vport_yoffset = buf[i++];
 139          ctx->se_vport_zscale = buf[i++];
 140          ctx->se_vport_zoffset = buf[i++];
 141          sarea->dirty |= RADEON_UPLOAD_VIEWPORT;
 142          break;
 143       case RADEON_EMIT_SE_CNTL:
 144          ctx->se_cntl = buf[i++];
 145          ctx->se_coord_fmt = buf[i++];
 146          sarea->dirty |= RADEON_UPLOAD_CONTEXT | RADEON_UPLOAD_VERTFMT;
 147          break;
 148       case RADEON_EMIT_SE_CNTL_STATUS:
 149          ctx->se_cntl_status = buf[i++];
 150          sarea->dirty |= RADEON_UPLOAD_SETUP;
 151          break;
 152       case RADEON_EMIT_RE_MISC:
 153          ctx->re_misc = buf[i++];
 154          sarea->dirty |= RADEON_UPLOAD_MISC;
 155          break;
 156       case RADEON_EMIT_PP_TXFILTER_0:
 157          tex0->pp_txfilter = buf[i++];
 158          tex0->pp_txformat = buf[i++];
 159          tex0->pp_txoffset = buf[i++];
 160          tex0->pp_txcblend = buf[i++];
 161          tex0->pp_txablend = buf[i++];
 162          tex0->pp_tfactor = buf[i++];
 163          sarea->dirty |= RADEON_UPLOAD_TEX0;
 164          break;
 165       case RADEON_EMIT_PP_BORDER_COLOR_0:
 166          tex0->pp_border_color = buf[i++];
 167          sarea->dirty |= RADEON_UPLOAD_TEX0;
 168          break;
 169       case RADEON_EMIT_PP_TXFILTER_1:
 170          tex1->pp_txfilter = buf[i++];
 171          tex1->pp_txformat = buf[i++];
 172          tex1->pp_txoffset = buf[i++];
 173          tex1->pp_txcblend = buf[i++];
 174          tex1->pp_txablend = buf[i++];
 175          tex1->pp_tfactor = buf[i++];
 176          sarea->dirty |= RADEON_UPLOAD_TEX1;
 177          break;
 178       case RADEON_EMIT_PP_BORDER_COLOR_1:
 179          tex1->pp_border_color = buf[i++];
 180          sarea->dirty |= RADEON_UPLOAD_TEX1;
 181          break;
 182
 183       case RADEON_EMIT_SE_ZBIAS_FACTOR:
 184          i++;
 185          i++;
 186          break;
 187
 188       case RADEON_EMIT_PP_TXFILTER_2:
 189       case RADEON_EMIT_PP_BORDER_COLOR_2:
 190       case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
 191       case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
 192       default:
 193          /* These states aren't understood by radeon drm 1.1 */
 194          fprintf(stderr, "Tried to emit unsupported state\n");
 195          return;
 196       }
 197    }
 198 }
 199
 200
 201
 202 static void radeonCompatEmitStateLocked( radeonContextPtr rmesa )
 203 {
 204    struct radeon_state_atom *atom;
 205
 206    if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
 207       fprintf(stderr, "%s\n", __FUNCTION__);
 208
 209    if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
 210       return;
 211
 212    foreach(atom, &rmesa->hw.atomlist) {
 213       if (rmesa->hw.all_dirty)
 214          atom->dirty = GL_TRUE;
 215       if (atom->is_tcl)
 216          atom->dirty = GL_FALSE;
 217       if (atom->dirty)
 218          radeonCompatEmitPacket(rmesa, atom);
 219    }
 220
 221    rmesa->hw.is_dirty = GL_FALSE;
 222    rmesa->hw.all_dirty = GL_FALSE;
 223 }
 224
 225
 226 static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa,
 227                                              GLuint hw_primitive,
 228                                              GLuint nverts,
 229                                              drm_clip_rect_t *pbox,
 230                                              GLuint nbox )
 231 {
 232    int i;
 233
 234    for ( i = 0 ; i < nbox ; ) {
 235       int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox );
 236       drm_clip_rect_t *b = rmesa->sarea->boxes;
 237       drm_radeon_vertex_t vtx;
 238
 239       rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS;
 240       rmesa->sarea->nbox = nr - i;
 241
 242       for ( ; i < nr ; i++)
 243          *b++ = pbox[i];
 244
 245       if (RADEON_DEBUG & DEBUG_IOCTL)
 246          fprintf(stderr,
 247                  "RadeonFlushVertexBuffer: prim %x buf %d verts %d "
 248                  "disc %d nbox %d\n",
 249                  hw_primitive,
 250                  rmesa->dma.current.buf->buf->idx,
 251                  nverts,
 252                  nr == nbox,
 253                  rmesa->sarea->nbox );
 254
 255       vtx.prim = hw_primitive;
 256       vtx.idx = rmesa->dma.current.buf->buf->idx;
 257       vtx.count = nverts;
 258       vtx.discard = (nr == nbox);
 259
 260       drmCommandWrite( rmesa->dri.fd,
 261                        DRM_RADEON_VERTEX,
 262                        &vtx, sizeof(vtx));
 263    }
 264 }
 265
 266
 267
 268 /* No 'start' for 1.1 vertices ioctl: only one vertex prim/buffer!
 269  */
 270 void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
 271                                 GLuint vertex_format,
 272                                 GLuint hw_primitive,
 273                                 GLuint nrverts )
 274 {
 275    if (RADEON_DEBUG & DEBUG_IOCTL)
 276       fprintf(stderr, "%s\n", __FUNCTION__);
 277
 278    LOCK_HARDWARE( rmesa );
 279
 280    radeonCompatEmitStateLocked( rmesa );
 281    rmesa->sarea->vc_format = vertex_format;
 282
 283    if (rmesa->state.scissor.enabled) {
 284       radeonCompatEmitPrimitiveLocked( rmesa,
 285                                        hw_primitive,
 286                                        nrverts,
 287                                        rmesa->state.scissor.pClipRects,
 288                                        rmesa->state.scissor.numClipRects );
 289    }
 290    else {
 291       radeonCompatEmitPrimitiveLocked( rmesa,
 292                                        hw_primitive,
 293                                        nrverts,
 294                                        rmesa->pClipRects,
 295                                        rmesa->numClipRects );
 296    }
 297
 298
 299    UNLOCK_HARDWARE( rmesa );
 300 }
 301