1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keithw@vmware.com>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/api_exec.h"
41 #include "main/context.h"
42 #include "main/simple_list.h"
43 #include "main/imports.h"
44 #include "main/extensions.h"
45 #include "main/version.h"
46 #include "main/vtxfmt.h"
48 #include "swrast/swrast.h"
49 #include "swrast_setup/swrast_setup.h"
53 #include "tnl/t_pipeline.h"
55 #include "drivers/common/driverfuncs.h"
57 #include "radeon_common.h"
58 #include "radeon_context.h"
59 #include "radeon_ioctl.h"
60 #include "radeon_state.h"
61 #include "radeon_span.h"
62 #include "radeon_tex.h"
63 #include "radeon_swtcl.h"
64 #include "radeon_tcl.h"
65 #include "radeon_queryobj.h"
66 #include "radeon_blit.h"
67 #include "radeon_fog.h"
70 #include "xmlpool.h" /* for symbolic values of enum-type options */
72 extern const struct tnl_pipeline_stage _radeon_render_stage
;
73 extern const struct tnl_pipeline_stage _radeon_tcl_stage
;
75 static const struct tnl_pipeline_stage
*radeon_pipeline
[] = {
77 /* Try and go straight to t&l
81 /* Catch any t&l fallbacks
83 &_tnl_vertex_transform_stage
,
84 &_tnl_normal_transform_stage
,
86 &_tnl_fog_coordinate_stage
,
88 &_tnl_texture_transform_stage
,
90 &_radeon_render_stage
,
91 &_tnl_render_stage
, /* FALLBACK: */
95 static void r100_get_lock(radeonContextPtr radeon
)
97 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
98 drm_radeon_sarea_t
*sarea
= radeon
->sarea
;
100 RADEON_STATECHANGE(rmesa
, ctx
);
101 if (rmesa
->radeon
.sarea
->tiling_enabled
) {
102 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |=
103 RADEON_COLOR_TILE_ENABLE
;
105 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] &=
106 ~RADEON_COLOR_TILE_ENABLE
;
109 if (sarea
->ctx_owner
!= rmesa
->radeon
.dri
.hwContext
) {
110 sarea
->ctx_owner
= rmesa
->radeon
.dri
.hwContext
;
114 static void r100_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
118 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon
)
120 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
122 /* r100 always needs to emit ZBS to avoid TCL lockups */
123 rmesa
->hw
.zbs
.dirty
= 1;
124 radeon
->hw
.is_dirty
= 1;
127 static void r100_vtbl_free_context(struct gl_context
*ctx
)
129 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
130 _mesa_vector4f_free( &rmesa
->tcl
.ObjClean
);
133 static void r100_emit_query_finish(radeonContextPtr radeon
)
135 BATCH_LOCALS(radeon
);
136 struct radeon_query_object
*query
= radeon
->query
.current
;
139 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR
, 0));
140 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
142 query
->curr_offset
+= sizeof(uint32_t);
143 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
144 query
->emitted_begin
= GL_FALSE
;
147 static void r100_init_vtbl(radeonContextPtr radeon
)
149 radeon
->vtbl
.get_lock
= r100_get_lock
;
150 radeon
->vtbl
.update_viewport_offset
= radeonUpdateViewportOffset
;
151 radeon
->vtbl
.emit_cs_header
= r100_vtbl_emit_cs_header
;
152 radeon
->vtbl
.swtcl_flush
= r100_swtcl_flush
;
153 radeon
->vtbl
.pre_emit_state
= r100_vtbl_pre_emit_state
;
154 radeon
->vtbl
.fallback
= radeonFallback
;
155 radeon
->vtbl
.free_context
= r100_vtbl_free_context
;
156 radeon
->vtbl
.emit_query_finish
= r100_emit_query_finish
;
157 radeon
->vtbl
.check_blit
= r100_check_blit
;
158 radeon
->vtbl
.blit
= r100_blit
;
159 radeon
->vtbl
.is_format_renderable
= radeonIsFormatRenderable
;
162 /* Create the device specific context.
165 r100CreateContext( gl_api api
,
166 const struct gl_config
*glVisual
,
167 __DRIcontext
*driContextPriv
,
168 unsigned major_version
,
169 unsigned minor_version
,
173 void *sharedContextPrivate
)
175 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
176 radeonScreenPtr screen
= (radeonScreenPtr
)(sPriv
->driverPrivate
);
177 struct dd_function_table functions
;
178 r100ContextPtr rmesa
;
179 struct gl_context
*ctx
;
181 int tcl_mode
, fthrottle_mode
;
183 if (flags
& ~__DRI_CTX_FLAG_DEBUG
) {
184 *error
= __DRI_CTX_ERROR_UNKNOWN_FLAG
;
189 *error
= __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE
;
194 assert(driContextPriv
);
197 /* Allocate the Radeon context */
198 rmesa
= calloc(1, sizeof(*rmesa
));
200 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
204 rmesa
->radeon
.radeonScreen
= screen
;
205 r100_init_vtbl(&rmesa
->radeon
);
207 /* init exp fog table data */
208 radeonInitStaticFogData();
210 /* Parse configuration files.
211 * Do this here so that initialMaxAnisotropy is set before we create
212 * the default textures.
214 driParseConfigFiles (&rmesa
->radeon
.optionCache
, &screen
->optionCache
,
215 screen
->driScreen
->myNum
, "radeon");
216 rmesa
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&rmesa
->radeon
.optionCache
,
217 "def_max_anisotropy");
219 if ( driQueryOptionb( &rmesa
->radeon
.optionCache
, "hyperz" ) ) {
220 if ( sPriv
->drm_version
.minor
< 13 )
221 fprintf( stderr
, "DRM version 1.%d too old to support HyperZ, "
222 "disabling.\n", sPriv
->drm_version
.minor
);
224 rmesa
->using_hyperz
= GL_TRUE
;
227 if ( sPriv
->drm_version
.minor
>= 15 )
228 rmesa
->texmicrotile
= GL_TRUE
;
230 /* Init default driver functions then plug in our Radeon-specific functions
231 * (the texture functions are especially important)
233 _mesa_init_driver_functions( &functions
);
234 radeonInitTextureFuncs( &rmesa
->radeon
, &functions
);
235 radeonInitQueryObjFunctions(&functions
);
237 if (!radeonInitContext(&rmesa
->radeon
, api
, &functions
,
238 glVisual
, driContextPriv
,
239 sharedContextPrivate
)) {
241 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
245 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
246 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
248 ctx
= &rmesa
->radeon
.glCtx
;
250 driContextSetFlags(ctx
, flags
);
252 /* Initialize the software rasterizer and helper modules.
254 _swrast_CreateContext( ctx
);
255 _vbo_CreateContext( ctx
);
256 _tnl_CreateContext( ctx
);
257 _swsetup_CreateContext( ctx
);
258 _ae_create_context( ctx
);
260 ctx
->Const
.MaxTextureUnits
= driQueryOptioni (&rmesa
->radeon
.optionCache
,
262 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
263 ctx
->Const
.MaxTextureCoordUnits
= ctx
->Const
.MaxTextureUnits
;
264 ctx
->Const
.MaxCombinedTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
266 ctx
->Const
.StripTextureBorder
= GL_TRUE
;
268 /* FIXME: When no memory manager is available we should set this
269 * to some reasonable value based on texture memory pool size */
270 ctx
->Const
.MaxTextureLevels
= 12;
271 ctx
->Const
.Max3DTextureLevels
= 9;
272 ctx
->Const
.MaxCubeTextureLevels
= 12;
273 ctx
->Const
.MaxTextureRectSize
= 2048;
275 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
279 ctx
->Const
.MinPointSize
= 1.0;
280 ctx
->Const
.MinPointSizeAA
= 1.0;
281 ctx
->Const
.MaxPointSize
= 1.0;
282 ctx
->Const
.MaxPointSizeAA
= 1.0;
284 ctx
->Const
.MinLineWidth
= 1.0;
285 ctx
->Const
.MinLineWidthAA
= 1.0;
286 ctx
->Const
.MaxLineWidth
= 10.0;
287 ctx
->Const
.MaxLineWidthAA
= 10.0;
288 ctx
->Const
.LineWidthGranularity
= 0.0625;
290 /* Set maxlocksize (and hence vb size) small enough to avoid
291 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
292 * fit in a single dma buffer for indexed rendering of quad strips,
295 ctx
->Const
.MaxArrayLockSize
=
296 MIN2( ctx
->Const
.MaxArrayLockSize
,
297 RADEON_BUFFER_SIZE
/ RADEON_MAX_TCL_VERTSIZE
);
301 ctx
->Const
.MaxDrawBuffers
= 1;
302 ctx
->Const
.MaxColorAttachments
= 1;
303 ctx
->Const
.MaxRenderbufferSize
= 2048;
305 ctx
->ShaderCompilerOptions
[MESA_SHADER_VERTEX
].OptimizeForAOS
= true;
307 /* Install the customized pipeline:
309 _tnl_destroy_pipeline( ctx
);
310 _tnl_install_pipeline( ctx
, radeon_pipeline
);
312 /* Try and keep materials and vertices separate:
314 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
316 /* Configure swrast and T&L to match hardware characteristics:
318 _swrast_allow_pixel_fog( ctx
, GL_FALSE
);
319 _swrast_allow_vertex_fog( ctx
, GL_TRUE
);
320 _tnl_allow_pixel_fog( ctx
, GL_FALSE
);
321 _tnl_allow_vertex_fog( ctx
, GL_TRUE
);
324 for ( i
= 0 ; i
< RADEON_MAX_TEXTURE_UNITS
; i
++ ) {
325 _math_matrix_ctr( &rmesa
->TexGenMatrix
[i
] );
326 _math_matrix_ctr( &rmesa
->tmpmat
[i
] );
327 _math_matrix_set_identity( &rmesa
->TexGenMatrix
[i
] );
328 _math_matrix_set_identity( &rmesa
->tmpmat
[i
] );
331 ctx
->Extensions
.ARB_occlusion_query
= true;
332 ctx
->Extensions
.ARB_texture_border_clamp
= true;
333 ctx
->Extensions
.ARB_texture_cube_map
= true;
334 ctx
->Extensions
.ARB_texture_env_combine
= true;
335 ctx
->Extensions
.ARB_texture_env_crossbar
= true;
336 ctx
->Extensions
.ARB_texture_env_dot3
= true;
337 ctx
->Extensions
.ARB_texture_mirror_clamp_to_edge
= true;
338 ctx
->Extensions
.ATI_texture_env_combine3
= true;
339 ctx
->Extensions
.ATI_texture_mirror_once
= true;
340 ctx
->Extensions
.EXT_texture_env_dot3
= true;
341 ctx
->Extensions
.EXT_texture_filter_anisotropic
= true;
342 ctx
->Extensions
.EXT_texture_mirror_clamp
= true;
343 ctx
->Extensions
.MESA_ycbcr_texture
= true;
344 ctx
->Extensions
.NV_texture_rectangle
= true;
345 ctx
->Extensions
.OES_EGL_image
= true;
347 if (rmesa
->radeon
.glCtx
.Mesa_DXTn
) {
348 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
349 ctx
->Extensions
.ANGLE_texture_compression_dxt
= true;
351 else if (driQueryOptionb (&rmesa
->radeon
.optionCache
, "force_s3tc_enable")) {
352 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
353 ctx
->Extensions
.ANGLE_texture_compression_dxt
= true;
356 /* XXX these should really go right after _mesa_init_driver_functions() */
357 radeon_fbo_init(&rmesa
->radeon
);
358 radeonInitSpanFuncs( ctx
);
359 radeonInitIoctlFuncs( ctx
);
360 radeonInitStateFuncs( ctx
);
361 radeonInitState( rmesa
);
362 radeonInitSwtcl( ctx
);
364 _mesa_vector4f_alloc( &rmesa
->tcl
.ObjClean
, 0,
365 ctx
->Const
.MaxArrayLockSize
, 32 );
367 fthrottle_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "fthrottle_mode");
368 rmesa
->radeon
.iw
.irq_seq
= -1;
369 rmesa
->radeon
.irqsEmitted
= 0;
370 rmesa
->radeon
.do_irqs
= (rmesa
->radeon
.radeonScreen
->irq
!= 0 &&
371 fthrottle_mode
== DRI_CONF_FTHROTTLE_IRQS
);
373 rmesa
->radeon
.do_usleeps
= (fthrottle_mode
== DRI_CONF_FTHROTTLE_USLEEPS
);
377 RADEON_DEBUG
= driParseDebugString( getenv( "RADEON_DEBUG" ),
381 tcl_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "tcl_mode");
382 if (driQueryOptionb(&rmesa
->radeon
.optionCache
, "no_rast")) {
383 fprintf(stderr
, "disabling 3D acceleration\n");
384 FALLBACK(rmesa
, RADEON_FALLBACK_DISABLE
, 1);
385 } else if (tcl_mode
== DRI_CONF_TCL_SW
||
386 !(rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
387 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
388 rmesa
->radeon
.radeonScreen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
389 fprintf(stderr
, "Disabling HW TCL support\n");
391 TCL_FALLBACK(&rmesa
->radeon
.glCtx
, RADEON_TCL_FALLBACK_TCL_DISABLE
, 1);
394 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
395 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
398 _mesa_compute_version(ctx
);
400 /* Exec table initialization requires the version to be computed */
401 _mesa_initialize_dispatch_tables(ctx
);
402 _mesa_initialize_vbo_vtxfmt(ctx
);
404 *error
= __DRI_CTX_ERROR_SUCCESS
;