fixup pci code for Jon's last checkin for changing page size
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.c
1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */
2 /**************************************************************************
3
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 All Rights Reserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29 **************************************************************************/
30
31 /*
32 * Authors:
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
36 */
37
38 #include "glheader.h"
39 #include "api_arrayelt.h"
40 #include "context.h"
41 #include "simple_list.h"
42 #include "imports.h"
43 #include "matrix.h"
44 #include "extensions.h"
45
46 #include "swrast/swrast.h"
47 #include "swrast_setup/swrast_setup.h"
48 #include "array_cache/acache.h"
49
50 #include "tnl/tnl.h"
51 #include "tnl/t_pipeline.h"
52
53 #include "drivers/common/driverfuncs.h"
54
55 #include "radeon_context.h"
56 #include "radeon_ioctl.h"
57 #include "radeon_state.h"
58 #include "radeon_span.h"
59 #include "radeon_tex.h"
60 #include "radeon_swtcl.h"
61 #include "radeon_tcl.h"
62 #include "radeon_vtxfmt.h"
63 #include "radeon_maos.h"
64
65 #define DRIVER_DATE "20041207"
66
67 #include "vblank.h"
68 #include "utils.h"
69 #include "xmlpool.h" /* for symbolic values of enum-type options */
70 #ifndef RADEON_DEBUG
71 int RADEON_DEBUG = (0);
72 #endif
73
74
75 /* Return the width and height of the given buffer.
76 */
77 static void radeonGetBufferSize( GLframebuffer *buffer,
78 GLuint *width, GLuint *height )
79 {
80 GET_CURRENT_CONTEXT(ctx);
81 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
82
83 LOCK_HARDWARE( rmesa );
84 *width = rmesa->dri.drawable->w;
85 *height = rmesa->dri.drawable->h;
86 UNLOCK_HARDWARE( rmesa );
87 }
88
89 /* Return various strings for glGetString().
90 */
91 static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
92 {
93 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
94 static char buffer[128];
95 unsigned offset;
96 GLuint agp_mode = rmesa->radeonScreen->IsPCI ? 0 :
97 rmesa->radeonScreen->AGPMode;
98
99 switch ( name ) {
100 case GL_VENDOR:
101 return (GLubyte *)"Tungsten Graphics, Inc.";
102
103 case GL_RENDERER:
104 offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
105 agp_mode );
106
107 sprintf( & buffer[ offset ], " %sTCL",
108 !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
109 ? "" : "NO-" );
110
111 return (GLubyte *)buffer;
112
113 default:
114 return NULL;
115 }
116 }
117
118
119 /* Extension strings exported by the R100 driver.
120 */
121 static const char * const card_extensions[] =
122 {
123 "GL_ARB_multisample",
124 "GL_ARB_multitexture",
125 "GL_ARB_texture_border_clamp",
126 "GL_ARB_texture_compression",
127 "GL_ARB_texture_env_add",
128 "GL_ARB_texture_env_combine",
129 "GL_ARB_texture_env_crossbar",
130 "GL_ARB_texture_env_dot3",
131 "GL_ARB_texture_mirrored_repeat",
132 "GL_EXT_blend_logic_op",
133 "GL_EXT_blend_subtract",
134 "GL_EXT_secondary_color",
135 "GL_EXT_stencil_wrap",
136 "GL_EXT_texture_edge_clamp",
137 "GL_EXT_texture_env_combine",
138 "GL_EXT_texture_env_dot3",
139 "GL_EXT_texture_filter_anisotropic",
140 "GL_EXT_texture_lod_bias",
141 "GL_EXT_texture_mirror_clamp",
142 "GL_ATI_texture_env_combine3",
143 "GL_ATI_texture_mirror_once",
144 "GL_MESA_ycbcr_texture",
145 "GL_NV_blend_square",
146 "GL_SGIS_generate_mipmap",
147 NULL
148 };
149
150 extern const struct tnl_pipeline_stage _radeon_texrect_stage;
151 extern const struct tnl_pipeline_stage _radeon_render_stage;
152 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
153
154 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
155
156 /* Try and go straight to t&l
157 */
158 &_radeon_tcl_stage,
159
160 /* Catch any t&l fallbacks
161 */
162 &_tnl_vertex_transform_stage,
163 &_tnl_normal_transform_stage,
164 &_tnl_lighting_stage,
165 &_tnl_fog_coordinate_stage,
166 &_tnl_texgen_stage,
167 &_tnl_texture_transform_stage,
168
169 /* Scale texture rectangle to 0..1.
170 */
171 &_radeon_texrect_stage,
172
173 &_radeon_render_stage,
174 &_tnl_render_stage, /* FALLBACK: */
175 0,
176 };
177
178
179
180 /* Initialize the driver's misc functions.
181 */
182 static void radeonInitDriverFuncs( struct dd_function_table *functions )
183 {
184 functions->GetBufferSize = radeonGetBufferSize;
185 functions->ResizeBuffers = _swrast_alloc_buffers;
186 functions->GetString = radeonGetString;
187 }
188
189 static const struct dri_debug_control debug_control[] =
190 {
191 { "fall", DEBUG_FALLBACKS },
192 { "tex", DEBUG_TEXTURE },
193 { "ioctl", DEBUG_IOCTL },
194 { "prim", DEBUG_PRIMS },
195 { "vert", DEBUG_VERTS },
196 { "state", DEBUG_STATE },
197 { "code", DEBUG_CODEGEN },
198 { "vfmt", DEBUG_VFMT },
199 { "vtxf", DEBUG_VFMT },
200 { "verb", DEBUG_VERBOSE },
201 { "dri", DEBUG_DRI },
202 { "dma", DEBUG_DMA },
203 { "san", DEBUG_SANITY },
204 { NULL, 0 }
205 };
206
207
208 static int
209 get_ust_nop( int64_t * ust )
210 {
211 *ust = 1;
212 return 0;
213 }
214
215
216 /* Create the device specific context.
217 */
218 GLboolean
219 radeonCreateContext( const __GLcontextModes *glVisual,
220 __DRIcontextPrivate *driContextPriv,
221 void *sharedContextPrivate)
222 {
223 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
224 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
225 struct dd_function_table functions;
226 radeonContextPtr rmesa;
227 GLcontext *ctx, *shareCtx;
228 int i;
229 int tcl_mode, fthrottle_mode;
230
231 assert(glVisual);
232 assert(driContextPriv);
233 assert(screen);
234
235 /* Allocate the Radeon context */
236 rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
237 if ( !rmesa )
238 return GL_FALSE;
239
240 /* Parse configuration files.
241 * Do this here so that initialMaxAnisotropy is set before we create
242 * the default textures.
243 */
244 driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
245 screen->driScreen->myNum, "radeon");
246 rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
247 "def_max_anisotropy");
248
249 if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
250 if ( sPriv->drmMinor < 13 )
251 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
252 "disabling.\n",sPriv->drmMinor );
253 else
254 rmesa->using_hyperz = GL_TRUE;
255 }
256
257 /* Init default driver functions then plug in our Radeon-specific functions
258 * (the texture functions are especially important)
259 */
260 _mesa_init_driver_functions( &functions );
261 radeonInitDriverFuncs( &functions );
262 radeonInitTextureFuncs( &functions );
263
264 /* Allocate the Mesa context */
265 if (sharedContextPrivate)
266 shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
267 else
268 shareCtx = NULL;
269 rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
270 &functions, (void *) rmesa);
271 if (!rmesa->glCtx) {
272 FREE(rmesa);
273 return GL_FALSE;
274 }
275 driContextPriv->driverPrivate = rmesa;
276
277 /* Init radeon context data */
278 rmesa->dri.context = driContextPriv;
279 rmesa->dri.screen = sPriv;
280 rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */
281 rmesa->dri.hwContext = driContextPriv->hHWContext;
282 rmesa->dri.hwLock = &sPriv->pSAREA->lock;
283 rmesa->dri.fd = sPriv->fd;
284 rmesa->dri.drmMinor = sPriv->drmMinor;
285
286 rmesa->radeonScreen = screen;
287 rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
288 screen->sarea_priv_offset);
289
290
291 rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
292
293 (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
294 make_empty_list( & rmesa->swapped );
295
296 rmesa->nr_heaps = screen->numTexHeaps;
297 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
298 rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
299 screen->texSize[i],
300 12,
301 RADEON_NR_TEX_REGIONS,
302 (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
303 & rmesa->sarea->tex_age[i],
304 & rmesa->swapped,
305 sizeof( radeonTexObj ),
306 (destroy_texture_object_t *) radeonDestroyTexObj );
307
308 driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
309 & rmesa->c_textureSwaps );
310 }
311 rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
312 "texture_depth");
313 if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
314 rmesa->texture_depth = ( screen->cpp == 4 ) ?
315 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
316
317 rmesa->swtcl.RenderIndex = ~0;
318 rmesa->hw.all_dirty = GL_TRUE;
319
320 /* Set the maximum texture size small enough that we can guarentee that
321 * all texture units can bind a maximal texture and have them both in
322 * texturable memory at once.
323 */
324
325 ctx = rmesa->glCtx;
326 ctx->Const.MaxTextureUnits = 2;
327 ctx->Const.MaxTextureImageUnits = 2;
328 ctx->Const.MaxTextureCoordUnits = 2;
329
330 driCalculateMaxTextureLevels( rmesa->texture_heaps,
331 rmesa->nr_heaps,
332 & ctx->Const,
333 4,
334 11, /* max 2D texture size is 2048x2048 */
335 0, /* 3D textures unsupported. */
336 0, /* cube textures unsupported. */
337 11, /* max rect texture size is 2048x2048. */
338 12,
339 GL_FALSE );
340
341 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
342
343 /* No wide points.
344 */
345 ctx->Const.MinPointSize = 1.0;
346 ctx->Const.MinPointSizeAA = 1.0;
347 ctx->Const.MaxPointSize = 1.0;
348 ctx->Const.MaxPointSizeAA = 1.0;
349
350 ctx->Const.MinLineWidth = 1.0;
351 ctx->Const.MinLineWidthAA = 1.0;
352 ctx->Const.MaxLineWidth = 10.0;
353 ctx->Const.MaxLineWidthAA = 10.0;
354 ctx->Const.LineWidthGranularity = 0.0625;
355
356 /* Set maxlocksize (and hence vb size) small enough to avoid
357 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
358 * fit in a single dma buffer for indexed rendering of quad strips,
359 * etc.
360 */
361 ctx->Const.MaxArrayLockSize =
362 MIN2( ctx->Const.MaxArrayLockSize,
363 RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
364
365 rmesa->boxes = 0;
366
367 /* Initialize the software rasterizer and helper modules.
368 */
369 _swrast_CreateContext( ctx );
370 _ac_CreateContext( ctx );
371 _tnl_CreateContext( ctx );
372 _swsetup_CreateContext( ctx );
373 _ae_create_context( ctx );
374
375 /* Install the customized pipeline:
376 */
377 _tnl_destroy_pipeline( ctx );
378 _tnl_install_pipeline( ctx, radeon_pipeline );
379 ctx->Driver.FlushVertices = radeonFlushVertices;
380
381 /* Try and keep materials and vertices separate:
382 */
383 _tnl_isolate_materials( ctx, GL_TRUE );
384
385
386 /* _mesa_allow_light_in_model( ctx, GL_FALSE ); */
387
388 /* Try and keep materials and vertices separate:
389 */
390 _tnl_isolate_materials( ctx, GL_TRUE );
391
392
393 /* Configure swrast and T&L to match hardware characteristics:
394 */
395 _swrast_allow_pixel_fog( ctx, GL_FALSE );
396 _swrast_allow_vertex_fog( ctx, GL_TRUE );
397 _tnl_allow_pixel_fog( ctx, GL_FALSE );
398 _tnl_allow_vertex_fog( ctx, GL_TRUE );
399
400
401 _math_matrix_ctr( &rmesa->TexGenMatrix[0] );
402 _math_matrix_ctr( &rmesa->TexGenMatrix[1] );
403 _math_matrix_ctr( &rmesa->tmpmat );
404 _math_matrix_set_identity( &rmesa->TexGenMatrix[0] );
405 _math_matrix_set_identity( &rmesa->TexGenMatrix[1] );
406 _math_matrix_set_identity( &rmesa->tmpmat );
407
408 driInitExtensions( ctx, card_extensions, GL_TRUE );
409 if (rmesa->glCtx->Mesa_DXTn) {
410 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
411 _mesa_enable_extension( ctx, "GL_S3_s3tc" );
412 }
413 else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
414 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
415 }
416
417 if (rmesa->dri.drmMinor >= 9)
418 _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
419
420 /* XXX these should really go right after _mesa_init_driver_functions() */
421 radeonInitIoctlFuncs( ctx );
422 radeonInitStateFuncs( ctx );
423 radeonInitSpanFuncs( ctx );
424 radeonInitState( rmesa );
425 radeonInitSwtcl( ctx );
426
427 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
428 ctx->Const.MaxArrayLockSize, 32 );
429
430 fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
431 rmesa->iw.irq_seq = -1;
432 rmesa->irqsEmitted = 0;
433 rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
434 fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
435
436 rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
437
438 rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
439 ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
440
441 rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( (const GLubyte *) "__glXGetUST" );
442 if ( rmesa->get_ust == NULL ) {
443 rmesa->get_ust = get_ust_nop;
444 }
445 (*rmesa->get_ust)( & rmesa->swap_ust );
446
447
448 #if DO_DEBUG
449 RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
450 debug_control );
451 #endif
452
453 tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
454 if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
455 fprintf(stderr, "disabling 3D acceleration\n");
456 FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
457 } else if (tcl_mode == DRI_CONF_TCL_SW ||
458 !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
459 if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
460 rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
461 fprintf(stderr, "Disabling HW TCL support\n");
462 }
463 TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
464 }
465
466 if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
467 if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
468 radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
469
470 _tnl_need_dlist_norm_lengths( ctx, GL_FALSE );
471 }
472 return GL_TRUE;
473 }
474
475
476 /* Destroy the device specific context.
477 */
478 /* Destroy the Mesa and driver specific context data.
479 */
480 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
481 {
482 GET_CURRENT_CONTEXT(ctx);
483 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
484 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
485
486 /* check if we're deleting the currently bound context */
487 if (rmesa == current) {
488 RADEON_FIREVERTICES( rmesa );
489 _mesa_make_current2(NULL, NULL, NULL);
490 }
491
492 /* Free radeon context resources */
493 assert(rmesa); /* should never be null */
494 if ( rmesa ) {
495 GLboolean release_texture_heaps;
496
497
498 release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
499 _swsetup_DestroyContext( rmesa->glCtx );
500 _tnl_DestroyContext( rmesa->glCtx );
501 _ac_DestroyContext( rmesa->glCtx );
502 _swrast_DestroyContext( rmesa->glCtx );
503
504 radeonDestroySwtcl( rmesa->glCtx );
505 radeonReleaseArrays( rmesa->glCtx, ~0 );
506 if (rmesa->dma.current.buf) {
507 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
508 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
509 }
510
511 if (!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)) {
512 int tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
513 if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
514 radeonVtxfmtDestroy( rmesa->glCtx );
515 }
516
517 /* free the Mesa context */
518 rmesa->glCtx->DriverCtx = NULL;
519 _mesa_destroy_context( rmesa->glCtx );
520
521 _mesa_vector4f_free( &rmesa->tcl.ObjClean );
522
523 if (rmesa->state.scissor.pClipRects) {
524 FREE(rmesa->state.scissor.pClipRects);
525 rmesa->state.scissor.pClipRects = 0;
526 }
527
528 if ( release_texture_heaps ) {
529 /* This share group is about to go away, free our private
530 * texture object data.
531 */
532 int i;
533
534 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
535 driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
536 rmesa->texture_heaps[ i ] = NULL;
537 }
538
539 assert( is_empty_list( & rmesa->swapped ) );
540 }
541
542 /* free the option cache */
543 driDestroyOptionCache (&rmesa->optionCache);
544
545 FREE( rmesa );
546 }
547 }
548
549
550
551
552 void
553 radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
554 {
555
556 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
557 radeonContextPtr rmesa;
558 GLcontext *ctx;
559 rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
560 ctx = rmesa->glCtx;
561 if (ctx->Visual.doubleBufferMode) {
562 _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */
563
564 if ( rmesa->doPageFlip ) {
565 radeonPageFlip( dPriv );
566 }
567 else {
568 radeonCopyBuffer( dPriv );
569 }
570 }
571 }
572 else {
573 /* XXX this shouldn't be an error but we can't handle it for now */
574 _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__);
575 }
576 }
577
578
579 /* Force the context `c' to be the current context and associate with it
580 * buffer `b'.
581 */
582 GLboolean
583 radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
584 __DRIdrawablePrivate *driDrawPriv,
585 __DRIdrawablePrivate *driReadPriv )
586 {
587 if ( driContextPriv ) {
588 radeonContextPtr newCtx =
589 (radeonContextPtr) driContextPriv->driverPrivate;
590
591 if (RADEON_DEBUG & DEBUG_DRI)
592 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
593
594 if ( newCtx->dri.drawable != driDrawPriv ) {
595 driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags );
596 newCtx->dri.drawable = driDrawPriv;
597 radeonUpdateWindow( newCtx->glCtx );
598 radeonUpdateViewportOffset( newCtx->glCtx );
599 }
600
601 _mesa_make_current2( newCtx->glCtx,
602 (GLframebuffer *) driDrawPriv->driverPrivate,
603 (GLframebuffer *) driReadPriv->driverPrivate );
604
605 if (newCtx->vb.enabled)
606 radeonVtxfmtMakeCurrent( newCtx->glCtx );
607
608 } else {
609 if (RADEON_DEBUG & DEBUG_DRI)
610 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
611 _mesa_make_current( 0, 0 );
612 }
613
614 if (RADEON_DEBUG & DEBUG_DRI)
615 fprintf(stderr, "End %s\n", __FUNCTION__);
616 return GL_TRUE;
617 }
618
619 /* Force the context `c' to be unbound from its buffer.
620 */
621 GLboolean
622 radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
623 {
624 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
625
626 if (RADEON_DEBUG & DEBUG_DRI)
627 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
628
629 return GL_TRUE;
630 }