src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/extensions.h"
  43 #include "main/mfeatures.h"
  44
  45 #include "swrast/swrast.h"
  46 #include "swrast_setup/swrast_setup.h"
  47 #include "vbo/vbo.h"
  48
  49 #include "tnl/tnl.h"
  50 #include "tnl/t_pipeline.h"
  51
  52 #include "drivers/common/driverfuncs.h"
  53
  54 #include "radeon_common.h"
  55 #include "radeon_context.h"
  56 #include "radeon_ioctl.h"
  57 #include "radeon_state.h"
  58 #include "radeon_span.h"
  59 #include "radeon_tex.h"
  60 #include "radeon_swtcl.h"
  61 #include "radeon_tcl.h"
  62 #include "radeon_queryobj.h"
  63 #include "radeon_blit.h"
  64
  65 #define need_GL_ARB_occlusion_query
  66 #define need_GL_EXT_blend_minmax
  67 #define need_GL_EXT_fog_coord
  68 #define need_GL_EXT_secondary_color
  69 #define need_GL_EXT_framebuffer_object
  70 #define need_GL_OES_EGL_image
  71 #include "main/remap_helper.h"
  72
  73 #include "utils.h"
  74 #include "xmlpool.h" /* for symbolic values of enum-type options */
  75
  76 /* Extension strings exported by the R100 driver.
  77  */
  78 static const struct dri_extension card_extensions[] =
  79 {
  80     { "GL_ARB_multitexture",               NULL },
  81     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  82     { "GL_ARB_texture_border_clamp",       NULL },
  83     { "GL_ARB_texture_env_add",            NULL },
  84     { "GL_ARB_texture_env_combine",        NULL },
  85     { "GL_ARB_texture_env_crossbar",       NULL },
  86     { "GL_ARB_texture_env_dot3",           NULL },
  87     { "GL_ARB_texture_mirrored_repeat",    NULL },
  88     { "GL_EXT_blend_logic_op",             NULL },
  89     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  90     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  91     { "GL_EXT_packed_depth_stencil",       NULL},
  92     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  93     { "GL_EXT_stencil_wrap",               NULL },
  94     { "GL_EXT_texture_edge_clamp",         NULL },
  95     { "GL_EXT_texture_env_combine",        NULL },
  96     { "GL_EXT_texture_env_dot3",           NULL },
  97     { "GL_EXT_texture_filter_anisotropic", NULL },
  98     { "GL_EXT_texture_lod_bias",           NULL },
  99     { "GL_EXT_texture_mirror_clamp",       NULL },
 100     { "GL_ATI_texture_env_combine3",       NULL },
 101     { "GL_ATI_texture_mirror_once",        NULL },
 102     { "GL_MESA_ycbcr_texture",             NULL },
 103     { "GL_NV_blend_square",                NULL },
 104 #if FEATURE_OES_EGL_image
 105     { "GL_OES_EGL_image",                  GL_OES_EGL_image_functions },
 106 #endif
 107     { NULL,                                NULL }
 108 };
 109
 110 static const struct dri_extension mm_extensions[] = {
 111   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 112   { NULL, NULL }
 113 };
 114
 115 extern const struct tnl_pipeline_stage _radeon_render_stage;
 116 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 117
 118 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 119
 120    /* Try and go straight to t&l
 121     */
 122    &_radeon_tcl_stage,
 123
 124    /* Catch any t&l fallbacks
 125     */
 126    &_tnl_vertex_transform_stage,
 127    &_tnl_normal_transform_stage,
 128    &_tnl_lighting_stage,
 129    &_tnl_fog_coordinate_stage,
 130    &_tnl_texgen_stage,
 131    &_tnl_texture_transform_stage,
 132
 133    &_radeon_render_stage,
 134    &_tnl_render_stage,          /* FALLBACK:  */
 135    NULL,
 136 };
 137
 138 static void r100_get_lock(radeonContextPtr radeon)
 139 {
 140    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 141    drm_radeon_sarea_t *sarea = radeon->sarea;
 142
 143    RADEON_STATECHANGE(rmesa, ctx);
 144    if (rmesa->radeon.sarea->tiling_enabled) {
 145       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 146          RADEON_COLOR_TILE_ENABLE;
 147    } else {
 148       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 149          ~RADEON_COLOR_TILE_ENABLE;
 150    }
 151
 152    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 153       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 154
 155       if (!radeon->radeonScreen->kernel_mm)
 156          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 157    }
 158 }
 159
 160 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 161 {
 162 }
 163
 164 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 165 {
 166    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 167
 168    /* r100 always needs to emit ZBS to avoid TCL lockups */
 169    rmesa->hw.zbs.dirty = 1;
 170    radeon->hw.is_dirty = 1;
 171 }
 172
 173 static void r100_vtbl_free_context(struct gl_context *ctx)
 174 {
 175    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 176    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 177 }
 178
 179 static void r100_emit_query_finish(radeonContextPtr radeon)
 180 {
 181    BATCH_LOCALS(radeon);
 182    struct radeon_query_object *query = radeon->query.current;
 183
 184    BEGIN_BATCH_NO_AUTOSTATE(4);
 185    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 186    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 187    END_BATCH();
 188    query->curr_offset += sizeof(uint32_t);
 189    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 190    query->emitted_begin = GL_FALSE;
 191 }
 192
 193 static void r100_init_vtbl(radeonContextPtr radeon)
 194 {
 195    radeon->vtbl.get_lock = r100_get_lock;
 196    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 197    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 198    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 199    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 200    radeon->vtbl.fallback = radeonFallback;
 201    radeon->vtbl.free_context = r100_vtbl_free_context;
 202    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 203    radeon->vtbl.check_blit = r100_check_blit;
 204    radeon->vtbl.blit = r100_blit;
 205    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 206 }
 207
 208 /* Create the device specific context.
 209  */
 210 GLboolean
 211 r100CreateContext( gl_api api,
 212                    const struct gl_config *glVisual,
 213                    __DRIcontext *driContextPriv,
 214                    void *sharedContextPrivate)
 215 {
 216    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 217    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 218    struct dd_function_table functions;
 219    r100ContextPtr rmesa;
 220    struct gl_context *ctx;
 221    int i;
 222    int tcl_mode, fthrottle_mode;
 223
 224    assert(glVisual);
 225    assert(driContextPriv);
 226    assert(screen);
 227
 228    /* Allocate the Radeon context */
 229    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 230    if ( !rmesa )
 231       return GL_FALSE;
 232
 233    rmesa->radeon.radeonScreen = screen;
 234    r100_init_vtbl(&rmesa->radeon);
 235
 236    /* init exp fog table data */
 237    radeonInitStaticFogData();
 238
 239    /* Parse configuration files.
 240     * Do this here so that initialMaxAnisotropy is set before we create
 241     * the default textures.
 242     */
 243    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 244                         screen->driScreen->myNum, "radeon");
 245    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 246                                                  "def_max_anisotropy");
 247
 248    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 249       if ( sPriv->drm_version.minor < 13 )
 250          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 251                           "disabling.\n", sPriv->drm_version.minor );
 252       else
 253          rmesa->using_hyperz = GL_TRUE;
 254    }
 255
 256    if ( sPriv->drm_version.minor >= 15 )
 257       rmesa->texmicrotile = GL_TRUE;
 258
 259    /* Init default driver functions then plug in our Radeon-specific functions
 260     * (the texture functions are especially important)
 261     */
 262    _mesa_init_driver_functions( &functions );
 263    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 264    radeonInitQueryObjFunctions(&functions);
 265
 266    if (!radeonInitContext(&rmesa->radeon, &functions,
 267                           glVisual, driContextPriv,
 268                           sharedContextPrivate)) {
 269      FREE(rmesa);
 270      return GL_FALSE;
 271    }
 272
 273    rmesa->radeon.swtcl.RenderIndex = ~0;
 274    rmesa->radeon.hw.all_dirty = GL_TRUE;
 275
 276    /* Set the maximum texture size small enough that we can guarentee that
 277     * all texture units can bind a maximal texture and have all of them in
 278     * texturable memory at once. Depending on the allow_large_textures driconf
 279     * setting allow larger textures.
 280     */
 281
 282    ctx = rmesa->radeon.glCtx;
 283    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 284                                                  "texture_units");
 285    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 286    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 287    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 288
 289    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 290
 291    /* FIXME: When no memory manager is available we should set this
 292     * to some reasonable value based on texture memory pool size */
 293    ctx->Const.MaxTextureLevels = 12;
 294    ctx->Const.Max3DTextureLevels = 9;
 295    ctx->Const.MaxCubeTextureLevels = 12;
 296    ctx->Const.MaxTextureRectSize = 2048;
 297
 298    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 299
 300    /* No wide points.
 301     */
 302    ctx->Const.MinPointSize = 1.0;
 303    ctx->Const.MinPointSizeAA = 1.0;
 304    ctx->Const.MaxPointSize = 1.0;
 305    ctx->Const.MaxPointSizeAA = 1.0;
 306
 307    ctx->Const.MinLineWidth = 1.0;
 308    ctx->Const.MinLineWidthAA = 1.0;
 309    ctx->Const.MaxLineWidth = 10.0;
 310    ctx->Const.MaxLineWidthAA = 10.0;
 311    ctx->Const.LineWidthGranularity = 0.0625;
 312
 313    /* Set maxlocksize (and hence vb size) small enough to avoid
 314     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 315     * fit in a single dma buffer for indexed rendering of quad strips,
 316     * etc.
 317     */
 318    ctx->Const.MaxArrayLockSize =
 319       MIN2( ctx->Const.MaxArrayLockSize,
 320             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 321
 322    rmesa->boxes = 0;
 323
 324    ctx->Const.MaxDrawBuffers = 1;
 325    ctx->Const.MaxColorAttachments = 1;
 326    ctx->Const.MaxRenderbufferSize = 2048;
 327
 328    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 329
 330    /* Initialize the software rasterizer and helper modules.
 331     */
 332    _swrast_CreateContext( ctx );
 333    _vbo_CreateContext( ctx );
 334    _tnl_CreateContext( ctx );
 335    _swsetup_CreateContext( ctx );
 336    _ae_create_context( ctx );
 337
 338    /* Install the customized pipeline:
 339     */
 340    _tnl_destroy_pipeline( ctx );
 341    _tnl_install_pipeline( ctx, radeon_pipeline );
 342
 343    /* Try and keep materials and vertices separate:
 344     */
 345 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 346
 347    /* Configure swrast and T&L to match hardware characteristics:
 348     */
 349    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 350    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 351    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 352    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 353
 354
 355    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 356       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 357       _math_matrix_ctr( &rmesa->tmpmat[i] );
 358       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 359       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 360    }
 361
 362    driInitExtensions( ctx, card_extensions, GL_TRUE );
 363    if (rmesa->radeon.radeonScreen->kernel_mm)
 364      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 365    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 366       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 367    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 368       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 369       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 370    }
 371    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 372       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 373    }
 374
 375    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 376       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 377
 378    if (!rmesa->radeon.radeonScreen->kernel_mm)
 379       _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 380
 381    /* XXX these should really go right after _mesa_init_driver_functions() */
 382    radeon_fbo_init(&rmesa->radeon);
 383    radeonInitSpanFuncs( ctx );
 384    radeonInitIoctlFuncs( ctx );
 385    radeonInitStateFuncs( ctx , rmesa->radeon.radeonScreen->kernel_mm );
 386    radeonInitState( rmesa );
 387    radeonInitSwtcl( ctx );
 388
 389    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 390                          ctx->Const.MaxArrayLockSize, 32 );
 391
 392    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 393    rmesa->radeon.iw.irq_seq = -1;
 394    rmesa->radeon.irqsEmitted = 0;
 395    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 396                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 397
 398    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 399
 400
 401 #if DO_DEBUG
 402    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 403                                        debug_control );
 404 #endif
 405
 406    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 407    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 408       fprintf(stderr, "disabling 3D acceleration\n");
 409       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 410    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 411               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 412       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 413          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 414          fprintf(stderr, "Disabling HW TCL support\n");
 415       }
 416       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 417    }
 418
 419    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 420 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 421    }
 422    return GL_TRUE;
 423 }