src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/matrix.h"
  43 #include "main/extensions.h"
  44 #include "main/framebuffer.h"
  45 #include "main/state.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55
  56 #include "radeon_common.h"
  57 #include "radeon_context.h"
  58 #include "radeon_ioctl.h"
  59 #include "radeon_state.h"
  60 #include "radeon_span.h"
  61 #include "radeon_tex.h"
  62 #include "radeon_swtcl.h"
  63 #include "radeon_tcl.h"
  64 #include "radeon_maos.h"
  65 #include "radeon_queryobj.h"
  66 #include "radeon_blit.h"
  67
  68 #define need_GL_ARB_occlusion_query
  69 #define need_GL_EXT_blend_minmax
  70 #define need_GL_EXT_fog_coord
  71 #define need_GL_EXT_secondary_color
  72 #define need_GL_EXT_framebuffer_object
  73 #include "main/remap_helper.h"
  74
  75 #define DRIVER_DATE     "20061018"
  76
  77 #include "vblank.h"
  78 #include "utils.h"
  79 #include "xmlpool.h" /* for symbolic values of enum-type options */
  80
  81 /* Extension strings exported by the R100 driver.
  82  */
  83 static const struct dri_extension card_extensions[] =
  84 {
  85     { "GL_ARB_multitexture",               NULL },
  86     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  87     { "GL_ARB_texture_border_clamp",       NULL },
  88     { "GL_ARB_texture_env_add",            NULL },
  89     { "GL_ARB_texture_env_combine",        NULL },
  90     { "GL_ARB_texture_env_crossbar",       NULL },
  91     { "GL_ARB_texture_env_dot3",           NULL },
  92     { "GL_ARB_texture_mirrored_repeat",    NULL },
  93     { "GL_EXT_blend_logic_op",             NULL },
  94     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  95     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  96     { "GL_EXT_packed_depth_stencil",       NULL},
  97     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  98     { "GL_EXT_stencil_wrap",               NULL },
  99     { "GL_EXT_texture_edge_clamp",         NULL },
 100     { "GL_EXT_texture_env_combine",        NULL },
 101     { "GL_EXT_texture_env_dot3",           NULL },
 102     { "GL_EXT_texture_filter_anisotropic", NULL },
 103     { "GL_EXT_texture_lod_bias",           NULL },
 104     { "GL_EXT_texture_mirror_clamp",       NULL },
 105     { "GL_ATI_texture_env_combine3",       NULL },
 106     { "GL_ATI_texture_mirror_once",        NULL },
 107     { "GL_MESA_ycbcr_texture",             NULL },
 108     { "GL_NV_blend_square",                NULL },
 109     { "GL_SGIS_generate_mipmap",           NULL },
 110     { NULL,                                NULL }
 111 };
 112
 113 static const struct dri_extension mm_extensions[] = {
 114   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 115   { NULL, NULL }
 116 };
 117
 118 extern const struct tnl_pipeline_stage _radeon_render_stage;
 119 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 120
 121 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 122
 123    /* Try and go straight to t&l
 124     */
 125    &_radeon_tcl_stage,
 126
 127    /* Catch any t&l fallbacks
 128     */
 129    &_tnl_vertex_transform_stage,
 130    &_tnl_normal_transform_stage,
 131    &_tnl_lighting_stage,
 132    &_tnl_fog_coordinate_stage,
 133    &_tnl_texgen_stage,
 134    &_tnl_texture_transform_stage,
 135
 136    &_radeon_render_stage,
 137    &_tnl_render_stage,          /* FALLBACK:  */
 138    NULL,
 139 };
 140
 141 static void r100_get_lock(radeonContextPtr radeon)
 142 {
 143    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 144    drm_radeon_sarea_t *sarea = radeon->sarea;
 145
 146    RADEON_STATECHANGE(rmesa, ctx);
 147    if (rmesa->radeon.sarea->tiling_enabled) {
 148       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 149          RADEON_COLOR_TILE_ENABLE;
 150    } else {
 151       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 152          ~RADEON_COLOR_TILE_ENABLE;
 153    }
 154
 155    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 156       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 157
 158       if (!radeon->radeonScreen->kernel_mm)
 159          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 160    }
 161 }
 162
 163 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 164 {
 165 }
 166
 167 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 168 {
 169    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 170
 171    /* r100 always needs to emit ZBS to avoid TCL lockups */
 172    rmesa->hw.zbs.dirty = 1;
 173    radeon->hw.is_dirty = 1;
 174 }
 175
 176 static void r100_vtbl_free_context(GLcontext *ctx)
 177 {
 178    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 179    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 180 }
 181
 182 static void r100_emit_query_finish(radeonContextPtr radeon)
 183 {
 184    BATCH_LOCALS(radeon);
 185    struct radeon_query_object *query = radeon->query.current;
 186
 187    BEGIN_BATCH_NO_AUTOSTATE(4);
 188    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 189    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 190    END_BATCH();
 191    query->curr_offset += sizeof(uint32_t);
 192    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 193    query->emitted_begin = GL_FALSE;
 194 }
 195
 196 static void r100_init_vtbl(radeonContextPtr radeon)
 197 {
 198    radeon->vtbl.get_lock = r100_get_lock;
 199    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 200    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 201    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 202    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 203    radeon->vtbl.fallback = radeonFallback;
 204    radeon->vtbl.free_context = r100_vtbl_free_context;
 205    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 206    radeon->vtbl.blit = r100_blit;
 207 }
 208
 209 /* Create the device specific context.
 210  */
 211 GLboolean
 212 r100CreateContext( const __GLcontextModes *glVisual,
 213                      __DRIcontext *driContextPriv,
 214                      void *sharedContextPrivate)
 215 {
 216    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 217    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 218    struct dd_function_table functions;
 219    r100ContextPtr rmesa;
 220    GLcontext *ctx;
 221    int i;
 222    int tcl_mode, fthrottle_mode;
 223
 224    assert(glVisual);
 225    assert(driContextPriv);
 226    assert(screen);
 227
 228    /* Allocate the Radeon context */
 229    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 230    if ( !rmesa )
 231       return GL_FALSE;
 232
 233    rmesa->radeon.radeonScreen = screen;
 234    r100_init_vtbl(&rmesa->radeon);
 235
 236    /* init exp fog table data */
 237    radeonInitStaticFogData();
 238
 239    /* Parse configuration files.
 240     * Do this here so that initialMaxAnisotropy is set before we create
 241     * the default textures.
 242     */
 243    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 244                         screen->driScreen->myNum, "radeon");
 245    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 246                                                  "def_max_anisotropy");
 247
 248    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 249       if ( sPriv->drm_version.minor < 13 )
 250          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 251                           "disabling.\n", sPriv->drm_version.minor );
 252       else
 253          rmesa->using_hyperz = GL_TRUE;
 254    }
 255
 256    if ( sPriv->drm_version.minor >= 15 )
 257       rmesa->texmicrotile = GL_TRUE;
 258
 259    /* Init default driver functions then plug in our Radeon-specific functions
 260     * (the texture functions are especially important)
 261     */
 262    _mesa_init_driver_functions( &functions );
 263    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 264    radeonInitQueryObjFunctions(&functions);
 265
 266    if (!radeonInitContext(&rmesa->radeon, &functions,
 267                           glVisual, driContextPriv,
 268                           sharedContextPrivate)) {
 269      FREE(rmesa);
 270      return GL_FALSE;
 271    }
 272
 273    rmesa->radeon.swtcl.RenderIndex = ~0;
 274    rmesa->radeon.hw.all_dirty = GL_TRUE;
 275
 276    /* Set the maximum texture size small enough that we can guarentee that
 277     * all texture units can bind a maximal texture and have all of them in
 278     * texturable memory at once. Depending on the allow_large_textures driconf
 279     * setting allow larger textures.
 280     */
 281
 282    ctx = rmesa->radeon.glCtx;
 283    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 284                                                  "texture_units");
 285    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 286    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 287
 288    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 289
 290    /* FIXME: When no memory manager is available we should set this
 291     * to some reasonable value based on texture memory pool size */
 292    ctx->Const.MaxTextureLevels = 12;
 293    ctx->Const.Max3DTextureLevels = 9;
 294    ctx->Const.MaxCubeTextureLevels = 12;
 295    ctx->Const.MaxTextureRectSize = 2048;
 296
 297    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 298
 299    /* No wide points.
 300     */
 301    ctx->Const.MinPointSize = 1.0;
 302    ctx->Const.MinPointSizeAA = 1.0;
 303    ctx->Const.MaxPointSize = 1.0;
 304    ctx->Const.MaxPointSizeAA = 1.0;
 305
 306    ctx->Const.MinLineWidth = 1.0;
 307    ctx->Const.MinLineWidthAA = 1.0;
 308    ctx->Const.MaxLineWidth = 10.0;
 309    ctx->Const.MaxLineWidthAA = 10.0;
 310    ctx->Const.LineWidthGranularity = 0.0625;
 311
 312    /* Set maxlocksize (and hence vb size) small enough to avoid
 313     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 314     * fit in a single dma buffer for indexed rendering of quad strips,
 315     * etc.
 316     */
 317    ctx->Const.MaxArrayLockSize =
 318       MIN2( ctx->Const.MaxArrayLockSize,
 319             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 320
 321    rmesa->boxes = 0;
 322
 323    ctx->Const.MaxDrawBuffers = 1;
 324
 325    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 326
 327    /* Initialize the software rasterizer and helper modules.
 328     */
 329    _swrast_CreateContext( ctx );
 330    _vbo_CreateContext( ctx );
 331    _tnl_CreateContext( ctx );
 332    _swsetup_CreateContext( ctx );
 333    _ae_create_context( ctx );
 334
 335    /* Install the customized pipeline:
 336     */
 337    _tnl_destroy_pipeline( ctx );
 338    _tnl_install_pipeline( ctx, radeon_pipeline );
 339
 340    /* Try and keep materials and vertices separate:
 341     */
 342 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 343
 344    /* Configure swrast and T&L to match hardware characteristics:
 345     */
 346    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 347    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 348    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 349    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 350
 351
 352    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 353       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 354       _math_matrix_ctr( &rmesa->tmpmat[i] );
 355       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 356       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 357    }
 358
 359    driInitExtensions( ctx, card_extensions, GL_TRUE );
 360    if (rmesa->radeon.radeonScreen->kernel_mm)
 361      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 362    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 363       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 364    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 365       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 366       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 367    }
 368    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 369       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 370    }
 371
 372    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 373       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 374
 375    if (!rmesa->radeon.radeonScreen->kernel_mm)
 376       _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 377
 378    /* XXX these should really go right after _mesa_init_driver_functions() */
 379    radeon_fbo_init(&rmesa->radeon);
 380    radeonInitSpanFuncs( ctx );
 381    radeonInitIoctlFuncs( ctx );
 382    radeonInitStateFuncs( ctx , rmesa->radeon.radeonScreen->kernel_mm );
 383    radeonInitState( rmesa );
 384    radeonInitSwtcl( ctx );
 385
 386    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 387                          ctx->Const.MaxArrayLockSize, 32 );
 388
 389    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 390    rmesa->radeon.iw.irq_seq = -1;
 391    rmesa->radeon.irqsEmitted = 0;
 392    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 393                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 394
 395    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 396
 397
 398 #if DO_DEBUG
 399    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 400                                        debug_control );
 401 #endif
 402
 403    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 404    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 405       fprintf(stderr, "disabling 3D acceleration\n");
 406       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 407    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 408               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 409       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 410          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 411          fprintf(stderr, "Disabling HW TCL support\n");
 412       }
 413       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 414    }
 415
 416    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 417 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 418    }
 419    return GL_TRUE;
 420 }