src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/matrix.h"
  43 #include "main/extensions.h"
  44 #include "main/framebuffer.h"
  45 #include "main/state.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55
  56 #include "radeon_context.h"
  57 #include "common_cmdbuf.h"
  58 #include "radeon_ioctl.h"
  59 #include "radeon_state.h"
  60 #include "radeon_span.h"
  61 #include "radeon_tex.h"
  62 #include "radeon_swtcl.h"
  63 #include "radeon_tcl.h"
  64 #include "radeon_maos.h"
  65
  66 #define need_GL_ARB_multisample
  67 #define need_GL_ARB_texture_compression
  68 #define need_GL_ARB_vertex_buffer_object
  69 #define need_GL_EXT_blend_minmax
  70 #define need_GL_EXT_fog_coord
  71 #define need_GL_EXT_secondary_color
  72 #include "extension_helper.h"
  73
  74 #define DRIVER_DATE     "20061018"
  75
  76 #include "vblank.h"
  77 #include "utils.h"
  78 #include "xmlpool.h" /* for symbolic values of enum-type options */
  79
  80 /* Return various strings for glGetString().
  81  */
  82 static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
  83 {
  84    r100ContextPtr rmesa = R100_CONTEXT(ctx);
  85    static char buffer[128];
  86    unsigned   offset;
  87    GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
  88       rmesa->radeon.radeonScreen->AGPMode;
  89
  90    switch ( name ) {
  91    case GL_VENDOR:
  92       return (GLubyte *)"Tungsten Graphics, Inc.";
  93
  94    case GL_RENDERER:
  95       offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
  96                                      agp_mode );
  97
  98       sprintf( & buffer[ offset ], " %sTCL",
  99                !(rmesa->radeon.TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
 100                ? "" : "NO-" );
 101
 102       return (GLubyte *)buffer;
 103
 104    default:
 105       return NULL;
 106    }
 107 }
 108
 109
 110 /* Extension strings exported by the R100 driver.
 111  */
 112 const struct dri_extension card_extensions[] =
 113 {
 114     { "GL_ARB_multisample",                GL_ARB_multisample_functions },
 115     { "GL_ARB_multitexture",               NULL },
 116     { "GL_ARB_texture_border_clamp",       NULL },
 117     { "GL_ARB_texture_compression",        GL_ARB_texture_compression_functions },
 118     { "GL_ARB_texture_env_add",            NULL },
 119     { "GL_ARB_texture_env_combine",        NULL },
 120     { "GL_ARB_texture_env_crossbar",       NULL },
 121     { "GL_ARB_texture_env_dot3",           NULL },
 122     { "GL_ARB_texture_mirrored_repeat",    NULL },
 123     { "GL_ARB_vertex_buffer_object",       GL_ARB_vertex_buffer_object_functions },
 124     { "GL_EXT_blend_logic_op",             NULL },
 125     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
 126     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 127     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
 128     { "GL_EXT_stencil_wrap",               NULL },
 129     { "GL_EXT_texture_edge_clamp",         NULL },
 130     { "GL_EXT_texture_env_combine",        NULL },
 131     { "GL_EXT_texture_env_dot3",           NULL },
 132     { "GL_EXT_texture_filter_anisotropic", NULL },
 133     { "GL_EXT_texture_lod_bias",           NULL },
 134     { "GL_EXT_texture_mirror_clamp",       NULL },
 135     { "GL_ATI_texture_env_combine3",       NULL },
 136     { "GL_ATI_texture_mirror_once",        NULL },
 137     { "GL_MESA_ycbcr_texture",             NULL },
 138     { "GL_NV_blend_square",                NULL },
 139     { "GL_SGIS_generate_mipmap",           NULL },
 140     { NULL,                                NULL }
 141 };
 142
 143 extern const struct tnl_pipeline_stage _radeon_render_stage;
 144 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 145
 146 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 147
 148    /* Try and go straight to t&l
 149     */
 150    &_radeon_tcl_stage,
 151
 152    /* Catch any t&l fallbacks
 153     */
 154    &_tnl_vertex_transform_stage,
 155    &_tnl_normal_transform_stage,
 156    &_tnl_lighting_stage,
 157    &_tnl_fog_coordinate_stage,
 158    &_tnl_texgen_stage,
 159    &_tnl_texture_transform_stage,
 160
 161    &_radeon_render_stage,
 162    &_tnl_render_stage,          /* FALLBACK:  */
 163    NULL,
 164 };
 165
 166
 167
 168 /* Initialize the driver's misc functions.
 169  */
 170 static void radeonInitDriverFuncs( struct dd_function_table *functions )
 171 {
 172     functions->GetString        = radeonGetString;
 173 }
 174
 175 static const struct dri_debug_control debug_control[] =
 176 {
 177     { "fall",  DEBUG_FALLBACKS },
 178     { "tex",   DEBUG_TEXTURE },
 179     { "ioctl", DEBUG_IOCTL },
 180     { "prim",  DEBUG_PRIMS },
 181     { "vert",  DEBUG_VERTS },
 182     { "state", DEBUG_STATE },
 183     { "code",  DEBUG_CODEGEN },
 184     { "vfmt",  DEBUG_VFMT },
 185     { "vtxf",  DEBUG_VFMT },
 186     { "verb",  DEBUG_VERBOSE },
 187     { "dri",   DEBUG_DRI },
 188     { "dma",   DEBUG_DMA },
 189     { "san",   DEBUG_SANITY },
 190     { "sync",  DEBUG_SYNC },
 191     { NULL,    0 }
 192 };
 193
 194 static void r100_get_lock(radeonContextPtr radeon)
 195 {
 196    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 197    drm_radeon_sarea_t *sarea = radeon->sarea;
 198
 199    RADEON_STATECHANGE(rmesa, ctx);
 200    if (rmesa->radeon.sarea->tiling_enabled) {
 201       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 202          RADEON_COLOR_TILE_ENABLE;
 203    } else {
 204       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 205          ~RADEON_COLOR_TILE_ENABLE;
 206    }
 207
 208    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 209       int i;
 210       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 211
 212       for (i = 0; i < rmesa->radeon.nr_heaps; i++) {
 213          DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]);
 214       }
 215    }
 216 }
 217
 218 static void r100_vtbl_flush(GLcontext *ctx)
 219 {
 220    RADEON_FIREVERTICES(R100_CONTEXT(ctx));
 221 }
 222
 223 static void r100_vtbl_set_all_dirty(GLcontext *ctx)
 224 {
 225    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 226    rmesa->hw.all_dirty = GL_TRUE;
 227 }
 228
 229 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 230 {
 231 }
 232
 233 static void r100_vtbl_emit_state(radeonContextPtr rmesa)
 234 {
 235         radeonEmitState((r100ContextPtr)rmesa);
 236 }
 237
 238 static void r100_vtbl_flush_vertices(radeonContextPtr rmesa)
 239 {
 240   RADEON_FIREVERTICES(((r100ContextPtr)rmesa));
 241 }
 242
 243
 244 static void r100_init_vtbl(radeonContextPtr radeon)
 245 {
 246    radeon->vtbl.get_lock = r100_get_lock;
 247    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 248    radeon->vtbl.flush = r100_vtbl_flush;
 249    radeon->vtbl.set_all_dirty = r100_vtbl_set_all_dirty;
 250    radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer;
 251    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 252    radeon->vtbl.emit_state = r100_vtbl_emit_state;
 253    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 254    radeon->vtbl.flush_vertices = r100_vtbl_flush_vertices;
 255 }
 256
 257 /* Create the device specific context.
 258  */
 259 GLboolean
 260 radeonCreateContext( const __GLcontextModes *glVisual,
 261                      __DRIcontextPrivate *driContextPriv,
 262                      void *sharedContextPrivate)
 263 {
 264    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 265    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 266    struct dd_function_table functions;
 267    r100ContextPtr rmesa;
 268    GLcontext *ctx;
 269    int i;
 270    int tcl_mode, fthrottle_mode;
 271
 272    assert(glVisual);
 273    assert(driContextPriv);
 274    assert(screen);
 275
 276    /* Allocate the Radeon context */
 277    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 278    if ( !rmesa )
 279       return GL_FALSE;
 280
 281    r100_init_vtbl(&rmesa->radeon);
 282
 283    /* init exp fog table data */
 284    radeonInitStaticFogData();
 285
 286    /* Parse configuration files.
 287     * Do this here so that initialMaxAnisotropy is set before we create
 288     * the default textures.
 289     */
 290    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 291                         screen->driScreen->myNum, "radeon");
 292    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 293                                                  "def_max_anisotropy");
 294
 295    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 296       if ( sPriv->drm_version.minor < 13 )
 297          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 298                           "disabling.\n", sPriv->drm_version.minor );
 299       else
 300          rmesa->using_hyperz = GL_TRUE;
 301    }
 302
 303    if ( sPriv->drm_version.minor >= 15 )
 304       rmesa->texmicrotile = GL_TRUE;
 305
 306    /* Init default driver functions then plug in our Radeon-specific functions
 307     * (the texture functions are especially important)
 308     */
 309    _mesa_init_driver_functions( &functions );
 310    radeonInitDriverFuncs( &functions );
 311    radeonInitTextureFuncs( &functions );
 312
 313    if (!radeonInitContext(&rmesa->radeon, &functions,
 314                           glVisual, driContextPriv,
 315                           sharedContextPrivate)) {
 316      FREE(rmesa);
 317      return GL_FALSE;
 318    }
 319
 320    (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
 321    make_empty_list( & rmesa->radeon.swapped );
 322
 323 #if 0
 324    rmesa->radeon.nr_heaps = screen->numTexHeaps;
 325    for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
 326       rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
 327             screen->texSize[i],
 328             12,
 329             RADEON_NR_TEX_REGIONS,
 330             (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
 331             & rmesa->radeon.sarea->tex_age[i],
 332             & rmesa->radeon.swapped,
 333             sizeof( radeonTexObj ),
 334             (destroy_texture_object_t *) radeonDestroyTexObj );
 335
 336       driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i],
 337                                         & rmesa->c_textureSwaps );
 338    }
 339 #endif
 340    rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
 341                                            "texture_depth");
 342    if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
 343       rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ?
 344          DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 345
 346    rmesa->radeon.swtcl.RenderIndex = ~0;
 347    rmesa->hw.all_dirty = GL_TRUE;
 348
 349    /* Set the maximum texture size small enough that we can guarentee that
 350     * all texture units can bind a maximal texture and have all of them in
 351     * texturable memory at once. Depending on the allow_large_textures driconf
 352     * setting allow larger textures.
 353     */
 354
 355    ctx = rmesa->radeon.glCtx;
 356    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 357                                                  "texture_units");
 358    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 359    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 360
 361    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 362
 363    driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
 364                                  rmesa->radeon.nr_heaps,
 365                                  & ctx->Const,
 366                                  4,
 367                                  11, /* max 2D texture size is 2048x2048 */
 368                                  8,  /* 256^3 */
 369                                  9,  /* \todo: max cube texture size seems to be 512x512(x6) */
 370                                  11, /* max rect texture size is 2048x2048. */
 371                                  12,
 372                                  GL_FALSE,
 373                                  i );
 374
 375
 376    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 377
 378    /* No wide points.
 379     */
 380    ctx->Const.MinPointSize = 1.0;
 381    ctx->Const.MinPointSizeAA = 1.0;
 382    ctx->Const.MaxPointSize = 1.0;
 383    ctx->Const.MaxPointSizeAA = 1.0;
 384
 385    ctx->Const.MinLineWidth = 1.0;
 386    ctx->Const.MinLineWidthAA = 1.0;
 387    ctx->Const.MaxLineWidth = 10.0;
 388    ctx->Const.MaxLineWidthAA = 10.0;
 389    ctx->Const.LineWidthGranularity = 0.0625;
 390
 391    /* Set maxlocksize (and hence vb size) small enough to avoid
 392     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 393     * fit in a single dma buffer for indexed rendering of quad strips,
 394     * etc.
 395     */
 396    ctx->Const.MaxArrayLockSize =
 397       MIN2( ctx->Const.MaxArrayLockSize,
 398             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 399
 400    rmesa->boxes = 0;
 401
 402    /* Initialize the software rasterizer and helper modules.
 403     */
 404    _swrast_CreateContext( ctx );
 405    _vbo_CreateContext( ctx );
 406    _tnl_CreateContext( ctx );
 407    _swsetup_CreateContext( ctx );
 408    _ae_create_context( ctx );
 409
 410    /* Install the customized pipeline:
 411     */
 412    _tnl_destroy_pipeline( ctx );
 413    _tnl_install_pipeline( ctx, radeon_pipeline );
 414
 415    /* Try and keep materials and vertices separate:
 416     */
 417 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 418
 419    /* Configure swrast and T&L to match hardware characteristics:
 420     */
 421    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 422    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 423    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 424    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 425
 426
 427    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 428       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 429       _math_matrix_ctr( &rmesa->tmpmat[i] );
 430       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 431       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 432    }
 433
 434    driInitExtensions( ctx, card_extensions, GL_TRUE );
 435    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 436       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 437    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 438       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 439       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 440    }
 441    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 442       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 443    }
 444
 445    if (rmesa->radeon.dri.drmMinor >= 9)
 446       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 447
 448    /* XXX these should really go right after _mesa_init_driver_functions() */
 449    radeonInitSpanFuncs( ctx );
 450    radeonInitIoctlFuncs( ctx );
 451    radeonInitStateFuncs( ctx );
 452    radeonInitState( rmesa );
 453    radeonInitSwtcl( ctx );
 454
 455    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 456                          ctx->Const.MaxArrayLockSize, 32 );
 457
 458    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 459    rmesa->radeon.iw.irq_seq = -1;
 460    rmesa->radeon.irqsEmitted = 0;
 461    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 462                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 463
 464    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 465
 466    (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
 467
 468
 469 #if DO_DEBUG
 470    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 471                                        debug_control );
 472 #endif
 473
 474    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 475    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 476       fprintf(stderr, "disabling 3D acceleration\n");
 477       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 478    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 479               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 480       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 481          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 482          fprintf(stderr, "Disabling HW TCL support\n");
 483       }
 484       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 485    }
 486
 487    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 488 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 489    }
 490    return GL_TRUE;
 491 }
 492
 493
 494 /* Destroy the device specific context.
 495  */
 496 /* Destroy the Mesa and driver specific context data.
 497  */
 498 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
 499 {
 500    GET_CURRENT_CONTEXT(ctx);
 501    r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
 502    r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL;
 503
 504    /* check if we're deleting the currently bound context */
 505    if (rmesa == current) {
 506       RADEON_FIREVERTICES( rmesa );
 507       _mesa_make_current(NULL, NULL, NULL);
 508    }
 509
 510    /* Free radeon context resources */
 511    assert(rmesa); /* should never be null */
 512    if ( rmesa ) {
 513       GLboolean   release_texture_heaps;
 514
 515
 516       release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
 517       _swsetup_DestroyContext( rmesa->radeon.glCtx );
 518       _tnl_DestroyContext( rmesa->radeon.glCtx );
 519       _vbo_DestroyContext( rmesa->radeon.glCtx );
 520       _swrast_DestroyContext( rmesa->radeon.glCtx );
 521
 522       radeonDestroySwtcl( rmesa->radeon.glCtx );
 523       radeonReleaseArrays( rmesa->radeon.glCtx, ~0 );
 524       if (rmesa->radeon.dma.current) {
 525          radeonReleaseDmaRegion( &rmesa->radeon );
 526          rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
 527       }
 528
 529       _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 530
 531       if (rmesa->radeon.state.scissor.pClipRects) {
 532          FREE(rmesa->radeon.state.scissor.pClipRects);
 533          rmesa->radeon.state.scissor.pClipRects = NULL;
 534       }
 535
 536       if ( release_texture_heaps ) {
 537          /* This share group is about to go away, free our private
 538           * texture object data.
 539           */
 540          int i;
 541
 542          for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
 543             driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
 544             rmesa->radeon.texture_heaps[ i ] = NULL;
 545          }
 546
 547          assert( is_empty_list( & rmesa->radeon.swapped ) );
 548       }
 549
 550       radeonCleanupContext(&rmesa->radeon);
 551
 552       FREE( rmesa );
 553    }
 554 }
 555
 556
 557 /* Force the context `c' to be unbound from its buffer.
 558  */
 559 GLboolean
 560 radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
 561 {
 562    r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
 563
 564    if (RADEON_DEBUG & DEBUG_DRI)
 565       fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx);
 566
 567    return GL_TRUE;
 568 }