radeon/r200/r300: attempt to move lock to common code
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
35 */
36
37 #include "main/glheader.h"
38 #include "main/api_arrayelt.h"
39 #include "main/context.h"
40 #include "main/simple_list.h"
41 #include "main/imports.h"
42 #include "main/matrix.h"
43 #include "main/extensions.h"
44 #include "main/framebuffer.h"
45 #include "main/state.h"
46
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
49 #include "vbo/vbo.h"
50
51 #include "tnl/tnl.h"
52 #include "tnl/t_pipeline.h"
53
54 #include "drivers/common/driverfuncs.h"
55
56 #include "radeon_context.h"
57 #include "radeon_ioctl.h"
58 #include "radeon_state.h"
59 #include "radeon_span.h"
60 #include "radeon_tex.h"
61 #include "radeon_swtcl.h"
62 #include "radeon_tcl.h"
63 #include "radeon_maos.h"
64
65 #define need_GL_ARB_multisample
66 #define need_GL_ARB_texture_compression
67 #define need_GL_ARB_vertex_buffer_object
68 #define need_GL_EXT_blend_minmax
69 #define need_GL_EXT_fog_coord
70 #define need_GL_EXT_secondary_color
71 #include "extension_helper.h"
72
73 #define DRIVER_DATE "20061018"
74
75 #include "vblank.h"
76 #include "utils.h"
77 #include "xmlpool.h" /* for symbolic values of enum-type options */
78 #ifndef RADEON_DEBUG
79 int RADEON_DEBUG = (0);
80 #endif
81
82
83 /* Return various strings for glGetString().
84 */
85 static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
86 {
87 r100ContextPtr rmesa = R100_CONTEXT(ctx);
88 static char buffer[128];
89 unsigned offset;
90 GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
91 rmesa->radeon.radeonScreen->AGPMode;
92
93 switch ( name ) {
94 case GL_VENDOR:
95 return (GLubyte *)"Tungsten Graphics, Inc.";
96
97 case GL_RENDERER:
98 offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
99 agp_mode );
100
101 sprintf( & buffer[ offset ], " %sTCL",
102 !(rmesa->radeon.TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
103 ? "" : "NO-" );
104
105 return (GLubyte *)buffer;
106
107 default:
108 return NULL;
109 }
110 }
111
112
113 /* Extension strings exported by the R100 driver.
114 */
115 const struct dri_extension card_extensions[] =
116 {
117 { "GL_ARB_multisample", GL_ARB_multisample_functions },
118 { "GL_ARB_multitexture", NULL },
119 { "GL_ARB_texture_border_clamp", NULL },
120 { "GL_ARB_texture_compression", GL_ARB_texture_compression_functions },
121 { "GL_ARB_texture_env_add", NULL },
122 { "GL_ARB_texture_env_combine", NULL },
123 { "GL_ARB_texture_env_crossbar", NULL },
124 { "GL_ARB_texture_env_dot3", NULL },
125 { "GL_ARB_texture_mirrored_repeat", NULL },
126 { "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
127 { "GL_EXT_blend_logic_op", NULL },
128 { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions },
129 { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
130 { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions },
131 { "GL_EXT_stencil_wrap", NULL },
132 { "GL_EXT_texture_edge_clamp", NULL },
133 { "GL_EXT_texture_env_combine", NULL },
134 { "GL_EXT_texture_env_dot3", NULL },
135 { "GL_EXT_texture_filter_anisotropic", NULL },
136 { "GL_EXT_texture_lod_bias", NULL },
137 { "GL_EXT_texture_mirror_clamp", NULL },
138 { "GL_ATI_texture_env_combine3", NULL },
139 { "GL_ATI_texture_mirror_once", NULL },
140 { "GL_MESA_ycbcr_texture", NULL },
141 { "GL_NV_blend_square", NULL },
142 { "GL_SGIS_generate_mipmap", NULL },
143 { NULL, NULL }
144 };
145
146 extern const struct tnl_pipeline_stage _radeon_render_stage;
147 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
148
149 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
150
151 /* Try and go straight to t&l
152 */
153 &_radeon_tcl_stage,
154
155 /* Catch any t&l fallbacks
156 */
157 &_tnl_vertex_transform_stage,
158 &_tnl_normal_transform_stage,
159 &_tnl_lighting_stage,
160 &_tnl_fog_coordinate_stage,
161 &_tnl_texgen_stage,
162 &_tnl_texture_transform_stage,
163
164 &_radeon_render_stage,
165 &_tnl_render_stage, /* FALLBACK: */
166 NULL,
167 };
168
169
170
171 /* Initialize the driver's misc functions.
172 */
173 static void radeonInitDriverFuncs( struct dd_function_table *functions )
174 {
175 functions->GetString = radeonGetString;
176 }
177
178 static const struct dri_debug_control debug_control[] =
179 {
180 { "fall", DEBUG_FALLBACKS },
181 { "tex", DEBUG_TEXTURE },
182 { "ioctl", DEBUG_IOCTL },
183 { "prim", DEBUG_PRIMS },
184 { "vert", DEBUG_VERTS },
185 { "state", DEBUG_STATE },
186 { "code", DEBUG_CODEGEN },
187 { "vfmt", DEBUG_VFMT },
188 { "vtxf", DEBUG_VFMT },
189 { "verb", DEBUG_VERBOSE },
190 { "dri", DEBUG_DRI },
191 { "dma", DEBUG_DMA },
192 { "san", DEBUG_SANITY },
193 { "sync", DEBUG_SYNC },
194 { NULL, 0 }
195 };
196
197 static void r100_get_lock(radeonContextPtr radeon)
198 {
199 r100ContextPtr rmesa = (r100ContextPtr)radeon;
200 drm_radeon_sarea_t *sarea = radeon->sarea;
201
202 RADEON_STATECHANGE(rmesa, ctx);
203 if (rmesa->radeon.sarea->tiling_enabled) {
204 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
205 RADEON_COLOR_TILE_ENABLE;
206 } else {
207 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
208 ~RADEON_COLOR_TILE_ENABLE;
209 }
210
211 if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
212 int i;
213 sarea->ctx_owner = rmesa->radeon.dri.hwContext;
214
215 for (i = 0; i < rmesa->radeon.nr_heaps; i++) {
216 DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]);
217 }
218 }
219 }
220
221 static void r100_init_vtbl(radeonContextPtr radeon)
222 {
223 radeon->vtbl.get_lock = r100_get_lock;
224 radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
225 }
226
227 /* Create the device specific context.
228 */
229 GLboolean
230 radeonCreateContext( const __GLcontextModes *glVisual,
231 __DRIcontextPrivate *driContextPriv,
232 void *sharedContextPrivate)
233 {
234 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
235 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
236 struct dd_function_table functions;
237 r100ContextPtr rmesa;
238 GLcontext *ctx, *shareCtx;
239 int i;
240 int tcl_mode, fthrottle_mode;
241
242 assert(glVisual);
243 assert(driContextPriv);
244 assert(screen);
245
246 /* Allocate the Radeon context */
247 rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
248 if ( !rmesa )
249 return GL_FALSE;
250
251 r100_init_vtbl(&rmesa->radeon);
252
253 /* init exp fog table data */
254 radeonInitStaticFogData();
255
256 /* Parse configuration files.
257 * Do this here so that initialMaxAnisotropy is set before we create
258 * the default textures.
259 */
260 driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
261 screen->driScreen->myNum, "radeon");
262 rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
263 "def_max_anisotropy");
264
265 if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
266 if ( sPriv->drm_version.minor < 13 )
267 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
268 "disabling.\n", sPriv->drm_version.minor );
269 else
270 rmesa->using_hyperz = GL_TRUE;
271 }
272
273 if ( sPriv->drm_version.minor >= 15 )
274 rmesa->texmicrotile = GL_TRUE;
275
276 /* Init default driver functions then plug in our Radeon-specific functions
277 * (the texture functions are especially important)
278 */
279 _mesa_init_driver_functions( &functions );
280 radeonInitDriverFuncs( &functions );
281 radeonInitTextureFuncs( &functions );
282
283 /* Allocate the Mesa context */
284 if (sharedContextPrivate)
285 shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
286 else
287 shareCtx = NULL;
288 rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx,
289 &functions, (void *) rmesa);
290 if (!rmesa->radeon.glCtx) {
291 FREE(rmesa);
292 return GL_FALSE;
293 }
294 driContextPriv->driverPrivate = rmesa;
295
296 /* Init radeon context data */
297 rmesa->radeon.dri.context = driContextPriv;
298 rmesa->radeon.dri.screen = sPriv;
299 rmesa->radeon.dri.drawable = NULL;
300 rmesa->radeon.dri.readable = NULL;
301 rmesa->radeon.dri.hwContext = driContextPriv->hHWContext;
302 rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock;
303 rmesa->radeon.dri.fd = sPriv->fd;
304 rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor;
305
306 rmesa->radeon.radeonScreen = screen;
307 rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
308 screen->sarea_priv_offset);
309
310
311 rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address;
312
313 (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
314 make_empty_list( & rmesa->radeon.swapped );
315
316 rmesa->radeon.nr_heaps = screen->numTexHeaps;
317 for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
318 rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
319 screen->texSize[i],
320 12,
321 RADEON_NR_TEX_REGIONS,
322 (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
323 & rmesa->radeon.sarea->tex_age[i],
324 & rmesa->radeon.swapped,
325 sizeof( radeonTexObj ),
326 (destroy_texture_object_t *) radeonDestroyTexObj );
327
328 driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i],
329 & rmesa->c_textureSwaps );
330 }
331 rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
332 "texture_depth");
333 if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
334 rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ?
335 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
336
337 rmesa->swtcl.RenderIndex = ~0;
338 rmesa->hw.all_dirty = GL_TRUE;
339
340 /* Set the maximum texture size small enough that we can guarentee that
341 * all texture units can bind a maximal texture and have all of them in
342 * texturable memory at once. Depending on the allow_large_textures driconf
343 * setting allow larger textures.
344 */
345
346 ctx = rmesa->radeon.glCtx;
347 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
348 "texture_units");
349 ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
350 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
351
352 i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
353
354 driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
355 rmesa->radeon.nr_heaps,
356 & ctx->Const,
357 4,
358 11, /* max 2D texture size is 2048x2048 */
359 8, /* 256^3 */
360 9, /* \todo: max cube texture size seems to be 512x512(x6) */
361 11, /* max rect texture size is 2048x2048. */
362 12,
363 GL_FALSE,
364 i );
365
366
367 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
368
369 /* No wide points.
370 */
371 ctx->Const.MinPointSize = 1.0;
372 ctx->Const.MinPointSizeAA = 1.0;
373 ctx->Const.MaxPointSize = 1.0;
374 ctx->Const.MaxPointSizeAA = 1.0;
375
376 ctx->Const.MinLineWidth = 1.0;
377 ctx->Const.MinLineWidthAA = 1.0;
378 ctx->Const.MaxLineWidth = 10.0;
379 ctx->Const.MaxLineWidthAA = 10.0;
380 ctx->Const.LineWidthGranularity = 0.0625;
381
382 /* Set maxlocksize (and hence vb size) small enough to avoid
383 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
384 * fit in a single dma buffer for indexed rendering of quad strips,
385 * etc.
386 */
387 ctx->Const.MaxArrayLockSize =
388 MIN2( ctx->Const.MaxArrayLockSize,
389 RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
390
391 rmesa->boxes = 0;
392
393 /* Initialize the software rasterizer and helper modules.
394 */
395 _swrast_CreateContext( ctx );
396 _vbo_CreateContext( ctx );
397 _tnl_CreateContext( ctx );
398 _swsetup_CreateContext( ctx );
399 _ae_create_context( ctx );
400
401 /* Install the customized pipeline:
402 */
403 _tnl_destroy_pipeline( ctx );
404 _tnl_install_pipeline( ctx, radeon_pipeline );
405
406 /* Try and keep materials and vertices separate:
407 */
408 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
409
410 /* Configure swrast and T&L to match hardware characteristics:
411 */
412 _swrast_allow_pixel_fog( ctx, GL_FALSE );
413 _swrast_allow_vertex_fog( ctx, GL_TRUE );
414 _tnl_allow_pixel_fog( ctx, GL_FALSE );
415 _tnl_allow_vertex_fog( ctx, GL_TRUE );
416
417
418 for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
419 _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
420 _math_matrix_ctr( &rmesa->tmpmat[i] );
421 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
422 _math_matrix_set_identity( &rmesa->tmpmat[i] );
423 }
424
425 driInitExtensions( ctx, card_extensions, GL_TRUE );
426 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
427 _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
428 if (rmesa->radeon.glCtx->Mesa_DXTn) {
429 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
430 _mesa_enable_extension( ctx, "GL_S3_s3tc" );
431 }
432 else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
433 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
434 }
435
436 if (rmesa->radeon.dri.drmMinor >= 9)
437 _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
438
439 /* XXX these should really go right after _mesa_init_driver_functions() */
440 radeonInitIoctlFuncs( ctx );
441 radeonInitStateFuncs( ctx );
442 radeonInitSpanFuncs( ctx );
443 radeonInitState( rmesa );
444 radeonInitSwtcl( ctx );
445
446 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
447 ctx->Const.MaxArrayLockSize, 32 );
448
449 fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
450 rmesa->radeon.iw.irq_seq = -1;
451 rmesa->radeon.irqsEmitted = 0;
452 rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
453 fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
454
455 rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
456
457 (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
458
459
460 #if DO_DEBUG
461 RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
462 debug_control );
463 #endif
464
465 tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
466 if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
467 fprintf(stderr, "disabling 3D acceleration\n");
468 FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
469 } else if (tcl_mode == DRI_CONF_TCL_SW ||
470 !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
471 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
472 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
473 fprintf(stderr, "Disabling HW TCL support\n");
474 }
475 TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
476 }
477
478 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
479 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
480 }
481 return GL_TRUE;
482 }
483
484
485 /* Destroy the device specific context.
486 */
487 /* Destroy the Mesa and driver specific context data.
488 */
489 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
490 {
491 GET_CURRENT_CONTEXT(ctx);
492 r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
493 r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL;
494
495 /* check if we're deleting the currently bound context */
496 if (rmesa == current) {
497 RADEON_FIREVERTICES( rmesa );
498 _mesa_make_current(NULL, NULL, NULL);
499 }
500
501 /* Free radeon context resources */
502 assert(rmesa); /* should never be null */
503 if ( rmesa ) {
504 GLboolean release_texture_heaps;
505
506
507 release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
508 _swsetup_DestroyContext( rmesa->radeon.glCtx );
509 _tnl_DestroyContext( rmesa->radeon.glCtx );
510 _vbo_DestroyContext( rmesa->radeon.glCtx );
511 _swrast_DestroyContext( rmesa->radeon.glCtx );
512
513 radeonDestroySwtcl( rmesa->radeon.glCtx );
514 radeonReleaseArrays( rmesa->radeon.glCtx, ~0 );
515 if (rmesa->dma.current.buf) {
516 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
517 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
518 }
519
520 _mesa_vector4f_free( &rmesa->tcl.ObjClean );
521
522 if (rmesa->radeon.state.scissor.pClipRects) {
523 FREE(rmesa->radeon.state.scissor.pClipRects);
524 rmesa->radeon.state.scissor.pClipRects = NULL;
525 }
526
527 if ( release_texture_heaps ) {
528 /* This share group is about to go away, free our private
529 * texture object data.
530 */
531 int i;
532
533 for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
534 driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
535 rmesa->radeon.texture_heaps[ i ] = NULL;
536 }
537
538 assert( is_empty_list( & rmesa->radeon.swapped ) );
539 }
540
541 /* free the Mesa context */
542 rmesa->radeon.glCtx->DriverCtx = NULL;
543 _mesa_destroy_context( rmesa->radeon.glCtx );
544
545 /* free the option cache */
546 driDestroyOptionCache (&rmesa->radeon.optionCache);
547
548 FREE( rmesa );
549 }
550 }
551
552
553
554
555 void
556 radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
557 {
558
559 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
560 r100ContextPtr rmesa;
561 GLcontext *ctx;
562 rmesa = (r100ContextPtr) dPriv->driContextPriv->driverPrivate;
563 ctx = rmesa->radeon.glCtx;
564 if (ctx->Visual.doubleBufferMode) {
565 _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */
566
567 if ( rmesa->radeon.doPageFlip ) {
568 radeonPageFlip( dPriv );
569 }
570 else {
571 radeonCopyBuffer( dPriv, NULL );
572 }
573 }
574 }
575 else {
576 /* XXX this shouldn't be an error but we can't handle it for now */
577 _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__);
578 }
579 }
580
581 void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
582 int x, int y, int w, int h )
583 {
584 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
585 radeonContextPtr radeon;
586 GLcontext *ctx;
587
588 radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
589 ctx = radeon->glCtx;
590
591 if (ctx->Visual.doubleBufferMode) {
592 drm_clip_rect_t rect;
593 rect.x1 = x + dPriv->x;
594 rect.y1 = (dPriv->h - y - h) + dPriv->y;
595 rect.x2 = rect.x1 + w;
596 rect.y2 = rect.y1 + h;
597 _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
598 radeonCopyBuffer(dPriv, &rect);
599 }
600 } else {
601 /* XXX this shouldn't be an error but we can't handle it for now */
602 _mesa_problem(NULL, "%s: drawable has no context!",
603 __FUNCTION__);
604 }
605 }
606
607 /* Make context `c' the current context and bind it to the given
608 * drawing and reading surfaces.
609 */
610 GLboolean
611 radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
612 __DRIdrawablePrivate *driDrawPriv,
613 __DRIdrawablePrivate *driReadPriv )
614 {
615 if ( driContextPriv ) {
616 radeonContextPtr newCtx =
617 (radeonContextPtr) driContextPriv->driverPrivate;
618
619 if (RADEON_DEBUG & DEBUG_DRI)
620 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
621
622 newCtx->dri.readable = driReadPriv;
623
624 if ( (newCtx->dri.drawable != driDrawPriv) ||
625 newCtx->lastStamp != driDrawPriv->lastStamp ) {
626 if (driDrawPriv->swap_interval == (unsigned)-1) {
627 driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0)
628 ? driGetDefaultVBlankFlags(&newCtx->optionCache)
629 : VBLANK_FLAG_NO_IRQ;
630
631 driDrawableInitVBlank( driDrawPriv );
632 }
633
634 newCtx->dri.drawable = driDrawPriv;
635
636 radeonSetCliprects(newCtx);
637 radeonUpdateViewportOffset( newCtx->glCtx );
638 }
639
640 _mesa_make_current( newCtx->glCtx,
641 (GLframebuffer *) driDrawPriv->driverPrivate,
642 (GLframebuffer *) driReadPriv->driverPrivate );
643
644 _mesa_update_state( newCtx->glCtx );
645 } else {
646 if (RADEON_DEBUG & DEBUG_DRI)
647 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
648 _mesa_make_current( NULL, NULL, NULL );
649 }
650
651 if (RADEON_DEBUG & DEBUG_DRI)
652 fprintf(stderr, "End %s\n", __FUNCTION__);
653 return GL_TRUE;
654 }
655
656 /* Force the context `c' to be unbound from its buffer.
657 */
658 GLboolean
659 radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
660 {
661 r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
662
663 if (RADEON_DEBUG & DEBUG_DRI)
664 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx);
665
666 return GL_TRUE;
667 }