src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keithw@vmware.com>
  35  */
  36
  37 #include <stdbool.h>
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/api_exec.h"
  41 #include "main/context.h"
  42 #include "main/simple_list.h"
  43 #include "main/imports.h"
  44 #include "main/extensions.h"
  45 #include "main/version.h"
  46 #include "main/vtxfmt.h"
  47
  48 #include "swrast/swrast.h"
  49 #include "swrast_setup/swrast_setup.h"
  50 #include "vbo/vbo.h"
  51
  52 #include "tnl/tnl.h"
  53 #include "tnl/t_pipeline.h"
  54
  55 #include "drivers/common/driverfuncs.h"
  56
  57 #include "radeon_common.h"
  58 #include "radeon_context.h"
  59 #include "radeon_ioctl.h"
  60 #include "radeon_state.h"
  61 #include "radeon_span.h"
  62 #include "radeon_tex.h"
  63 #include "radeon_swtcl.h"
  64 #include "radeon_tcl.h"
  65 #include "radeon_queryobj.h"
  66 #include "radeon_blit.h"
  67 #include "radeon_fog.h"
  68
  69 #include "utils.h"
  70 #include "xmlpool.h" /* for symbolic values of enum-type options */
  71
  72 extern const struct tnl_pipeline_stage _radeon_render_stage;
  73 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
  74
  75 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
  76
  77    /* Try and go straight to t&l
  78     */
  79    &_radeon_tcl_stage,
  80
  81    /* Catch any t&l fallbacks
  82     */
  83    &_tnl_vertex_transform_stage,
  84    &_tnl_normal_transform_stage,
  85    &_tnl_lighting_stage,
  86    &_tnl_fog_coordinate_stage,
  87    &_tnl_texgen_stage,
  88    &_tnl_texture_transform_stage,
  89
  90    &_radeon_render_stage,
  91    &_tnl_render_stage,          /* FALLBACK:  */
  92    NULL,
  93 };
  94
  95 static void r100_get_lock(radeonContextPtr radeon)
  96 {
  97    r100ContextPtr rmesa = (r100ContextPtr)radeon;
  98    drm_radeon_sarea_t *sarea = radeon->sarea;
  99
 100    RADEON_STATECHANGE(rmesa, ctx);
 101    if (rmesa->radeon.sarea->tiling_enabled) {
 102       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 103          RADEON_COLOR_TILE_ENABLE;
 104    } else {
 105       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 106          ~RADEON_COLOR_TILE_ENABLE;
 107    }
 108
 109    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 110       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 111    }
 112 }
 113
 114 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 115 {
 116 }
 117
 118 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 119 {
 120    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 121
 122    /* r100 always needs to emit ZBS to avoid TCL lockups */
 123    rmesa->hw.zbs.dirty = 1;
 124    radeon->hw.is_dirty = 1;
 125 }
 126
 127 static void r100_vtbl_free_context(struct gl_context *ctx)
 128 {
 129    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 130    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 131 }
 132
 133 static void r100_emit_query_finish(radeonContextPtr radeon)
 134 {
 135    BATCH_LOCALS(radeon);
 136    struct radeon_query_object *query = radeon->query.current;
 137
 138    BEGIN_BATCH(4);
 139    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 140    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 141    END_BATCH();
 142    query->curr_offset += sizeof(uint32_t);
 143    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 144    query->emitted_begin = GL_FALSE;
 145 }
 146
 147 static void r100_init_vtbl(radeonContextPtr radeon)
 148 {
 149    radeon->vtbl.get_lock = r100_get_lock;
 150    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 151    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 152    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 153    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 154    radeon->vtbl.fallback = radeonFallback;
 155    radeon->vtbl.free_context = r100_vtbl_free_context;
 156    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 157    radeon->vtbl.check_blit = r100_check_blit;
 158    radeon->vtbl.blit = r100_blit;
 159    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 160    radeon->vtbl.revalidate_all_buffers = r100ValidateBuffers;
 161 }
 162
 163 /* Create the device specific context.
 164  */
 165 GLboolean
 166 r100CreateContext( gl_api api,
 167                    const struct gl_config *glVisual,
 168                    __DRIcontext *driContextPriv,
 169                    unsigned major_version,
 170                    unsigned minor_version,
 171                    uint32_t flags,
 172                    bool notify_reset,
 173                    unsigned *error,
 174                    void *sharedContextPrivate)
 175 {
 176    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 177    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
 178    struct dd_function_table functions;
 179    r100ContextPtr rmesa;
 180    struct gl_context *ctx;
 181    int i;
 182    int tcl_mode, fthrottle_mode;
 183
 184    if (flags & ~__DRI_CTX_FLAG_DEBUG) {
 185       *error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
 186       return false;
 187    }
 188
 189    if (notify_reset) {
 190       *error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
 191       return false;
 192    }
 193
 194    assert(glVisual);
 195    assert(driContextPriv);
 196    assert(screen);
 197
 198    /* Allocate the Radeon context */
 199    rmesa = calloc(1, sizeof(*rmesa));
 200    if ( !rmesa ) {
 201       *error = __DRI_CTX_ERROR_NO_MEMORY;
 202       return GL_FALSE;
 203    }
 204
 205    rmesa->radeon.radeonScreen = screen;
 206    r100_init_vtbl(&rmesa->radeon);
 207
 208    /* init exp fog table data */
 209    radeonInitStaticFogData();
 210
 211    /* Parse configuration files.
 212     * Do this here so that initialMaxAnisotropy is set before we create
 213     * the default textures.
 214     */
 215    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 216                         screen->driScreen->myNum, "radeon");
 217    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 218                                                  "def_max_anisotropy");
 219
 220    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 221       if ( sPriv->drm_version.minor < 13 )
 222          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 223                           "disabling.\n", sPriv->drm_version.minor );
 224       else
 225          rmesa->using_hyperz = GL_TRUE;
 226    }
 227
 228    if ( sPriv->drm_version.minor >= 15 )
 229       rmesa->texmicrotile = GL_TRUE;
 230
 231    /* Init default driver functions then plug in our Radeon-specific functions
 232     * (the texture functions are especially important)
 233     */
 234    _mesa_init_driver_functions( &functions );
 235    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 236    radeonInitQueryObjFunctions(&functions);
 237
 238    if (!radeonInitContext(&rmesa->radeon, api, &functions,
 239                           glVisual, driContextPriv,
 240                           sharedContextPrivate)) {
 241      free(rmesa);
 242      *error = __DRI_CTX_ERROR_NO_MEMORY;
 243      return GL_FALSE;
 244    }
 245
 246    rmesa->radeon.swtcl.RenderIndex = ~0;
 247    rmesa->radeon.hw.all_dirty = GL_TRUE;
 248
 249    ctx = &rmesa->radeon.glCtx;
 250
 251    driContextSetFlags(ctx, flags);
 252
 253    /* Initialize the software rasterizer and helper modules.
 254     */
 255    _swrast_CreateContext( ctx );
 256    _vbo_CreateContext( ctx );
 257    _tnl_CreateContext( ctx );
 258    _swsetup_CreateContext( ctx );
 259    _ae_create_context( ctx );
 260
 261    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 262                                                  "texture_units");
 263    ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 264    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 265    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 266
 267    ctx->Const.StripTextureBorder = GL_TRUE;
 268
 269    /* FIXME: When no memory manager is available we should set this
 270     * to some reasonable value based on texture memory pool size */
 271    ctx->Const.MaxTextureLevels = 12;
 272    ctx->Const.Max3DTextureLevels = 9;
 273    ctx->Const.MaxCubeTextureLevels = 12;
 274    ctx->Const.MaxTextureRectSize = 2048;
 275
 276    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 277
 278    /* No wide points.
 279     */
 280    ctx->Const.MinPointSize = 1.0;
 281    ctx->Const.MinPointSizeAA = 1.0;
 282    ctx->Const.MaxPointSize = 1.0;
 283    ctx->Const.MaxPointSizeAA = 1.0;
 284
 285    ctx->Const.MinLineWidth = 1.0;
 286    ctx->Const.MinLineWidthAA = 1.0;
 287    ctx->Const.MaxLineWidth = 10.0;
 288    ctx->Const.MaxLineWidthAA = 10.0;
 289    ctx->Const.LineWidthGranularity = 0.0625;
 290
 291    /* Set maxlocksize (and hence vb size) small enough to avoid
 292     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 293     * fit in a single dma buffer for indexed rendering of quad strips,
 294     * etc.
 295     */
 296    ctx->Const.MaxArrayLockSize =
 297       MIN2( ctx->Const.MaxArrayLockSize,
 298             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 299
 300    rmesa->boxes = 0;
 301
 302    ctx->Const.MaxDrawBuffers = 1;
 303    ctx->Const.MaxColorAttachments = 1;
 304    ctx->Const.MaxRenderbufferSize = 2048;
 305
 306    ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = true;
 307
 308    /* Install the customized pipeline:
 309     */
 310    _tnl_destroy_pipeline( ctx );
 311    _tnl_install_pipeline( ctx, radeon_pipeline );
 312
 313    /* Try and keep materials and vertices separate:
 314     */
 315 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 316
 317    /* Configure swrast and T&L to match hardware characteristics:
 318     */
 319    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 320    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 321    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 322    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 323
 324
 325    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 326       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 327       _math_matrix_ctr( &rmesa->tmpmat[i] );
 328       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 329       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 330    }
 331
 332    ctx->Extensions.ARB_occlusion_query = true;
 333    ctx->Extensions.ARB_texture_border_clamp = true;
 334    ctx->Extensions.ARB_texture_cube_map = true;
 335    ctx->Extensions.ARB_texture_env_combine = true;
 336    ctx->Extensions.ARB_texture_env_crossbar = true;
 337    ctx->Extensions.ARB_texture_env_dot3 = true;
 338    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
 339    ctx->Extensions.ATI_texture_env_combine3 = true;
 340    ctx->Extensions.ATI_texture_mirror_once = true;
 341    ctx->Extensions.EXT_texture_env_dot3 = true;
 342    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 343    ctx->Extensions.EXT_texture_mirror_clamp = true;
 344    ctx->Extensions.MESA_ycbcr_texture = true;
 345    ctx->Extensions.NV_texture_rectangle = true;
 346    ctx->Extensions.OES_EGL_image = true;
 347
 348    if (rmesa->radeon.glCtx.Mesa_DXTn) {
 349       ctx->Extensions.EXT_texture_compression_s3tc = true;
 350       ctx->Extensions.ANGLE_texture_compression_dxt = true;
 351    }
 352    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 353       ctx->Extensions.EXT_texture_compression_s3tc = true;
 354       ctx->Extensions.ANGLE_texture_compression_dxt = true;
 355    }
 356
 357    /* XXX these should really go right after _mesa_init_driver_functions() */
 358    radeon_fbo_init(&rmesa->radeon);
 359    radeonInitSpanFuncs( ctx );
 360    radeonInitIoctlFuncs( ctx );
 361    radeonInitStateFuncs( ctx );
 362    radeonInitState( rmesa );
 363    radeonInitSwtcl( ctx );
 364
 365    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 366                          ctx->Const.MaxArrayLockSize, 32 );
 367
 368    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 369    rmesa->radeon.iw.irq_seq = -1;
 370    rmesa->radeon.irqsEmitted = 0;
 371    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 372                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 373
 374    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 375
 376
 377 #if DO_DEBUG
 378    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 379                                        debug_control );
 380 #endif
 381
 382    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 383    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 384       fprintf(stderr, "disabling 3D acceleration\n");
 385       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 386    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 387               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 388       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 389          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 390          fprintf(stderr, "Disabling HW TCL support\n");
 391       }
 392       TCL_FALLBACK(&rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 393    }
 394
 395    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 396 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 397    }
 398
 399    _mesa_compute_version(ctx);
 400
 401    /* Exec table initialization requires the version to be computed */
 402    _mesa_initialize_dispatch_tables(ctx);
 403    _mesa_initialize_vbo_vtxfmt(ctx);
 404
 405    *error = __DRI_CTX_ERROR_SUCCESS;
 406    return GL_TRUE;
 407 }