More vblank cleanups.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.c
1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */
2 /**************************************************************************
3
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
6
7 All Rights Reserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29 **************************************************************************/
30
31 /*
32 * Authors:
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
36 */
37
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/matrix.h"
44 #include "main/extensions.h"
45 #include "main/framebuffer.h"
46 #include "main/state.h"
47
48 #include "swrast/swrast.h"
49 #include "swrast_setup/swrast_setup.h"
50 #include "vbo/vbo.h"
51
52 #include "tnl/tnl.h"
53 #include "tnl/t_pipeline.h"
54
55 #include "drivers/common/driverfuncs.h"
56
57 #include "radeon_context.h"
58 #include "radeon_ioctl.h"
59 #include "radeon_state.h"
60 #include "radeon_span.h"
61 #include "radeon_tex.h"
62 #include "radeon_swtcl.h"
63 #include "radeon_tcl.h"
64 #include "radeon_maos.h"
65
66 #define need_GL_ARB_multisample
67 #define need_GL_ARB_texture_compression
68 #define need_GL_ARB_vertex_buffer_object
69 #define need_GL_EXT_blend_minmax
70 #define need_GL_EXT_fog_coord
71 #define need_GL_EXT_secondary_color
72 #include "extension_helper.h"
73
74 #define DRIVER_DATE "20061018"
75
76 #include "vblank.h"
77 #include "utils.h"
78 #include "xmlpool.h" /* for symbolic values of enum-type options */
79 #ifndef RADEON_DEBUG
80 int RADEON_DEBUG = (0);
81 #endif
82
83
84 /* Return various strings for glGetString().
85 */
86 static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
87 {
88 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
89 static char buffer[128];
90 unsigned offset;
91 GLuint agp_mode = (rmesa->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
92 rmesa->radeonScreen->AGPMode;
93
94 switch ( name ) {
95 case GL_VENDOR:
96 return (GLubyte *)"Tungsten Graphics, Inc.";
97
98 case GL_RENDERER:
99 offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
100 agp_mode );
101
102 sprintf( & buffer[ offset ], " %sTCL",
103 !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
104 ? "" : "NO-" );
105
106 return (GLubyte *)buffer;
107
108 default:
109 return NULL;
110 }
111 }
112
113
114 /* Extension strings exported by the R100 driver.
115 */
116 const struct dri_extension card_extensions[] =
117 {
118 { "GL_ARB_multisample", GL_ARB_multisample_functions },
119 { "GL_ARB_multitexture", NULL },
120 { "GL_ARB_texture_border_clamp", NULL },
121 { "GL_ARB_texture_compression", GL_ARB_texture_compression_functions },
122 { "GL_ARB_texture_env_add", NULL },
123 { "GL_ARB_texture_env_combine", NULL },
124 { "GL_ARB_texture_env_crossbar", NULL },
125 { "GL_ARB_texture_env_dot3", NULL },
126 { "GL_ARB_texture_mirrored_repeat", NULL },
127 { "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
128 { "GL_EXT_blend_logic_op", NULL },
129 { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions },
130 { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
131 { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions },
132 { "GL_EXT_stencil_wrap", NULL },
133 { "GL_EXT_texture_edge_clamp", NULL },
134 { "GL_EXT_texture_env_combine", NULL },
135 { "GL_EXT_texture_env_dot3", NULL },
136 { "GL_EXT_texture_filter_anisotropic", NULL },
137 { "GL_EXT_texture_lod_bias", NULL },
138 { "GL_EXT_texture_mirror_clamp", NULL },
139 { "GL_ATI_texture_env_combine3", NULL },
140 { "GL_ATI_texture_mirror_once", NULL },
141 { "GL_MESA_ycbcr_texture", NULL },
142 { "GL_NV_blend_square", NULL },
143 { "GL_SGIS_generate_mipmap", NULL },
144 { NULL, NULL }
145 };
146
147 extern const struct tnl_pipeline_stage _radeon_render_stage;
148 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
149
150 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
151
152 /* Try and go straight to t&l
153 */
154 &_radeon_tcl_stage,
155
156 /* Catch any t&l fallbacks
157 */
158 &_tnl_vertex_transform_stage,
159 &_tnl_normal_transform_stage,
160 &_tnl_lighting_stage,
161 &_tnl_fog_coordinate_stage,
162 &_tnl_texgen_stage,
163 &_tnl_texture_transform_stage,
164
165 &_radeon_render_stage,
166 &_tnl_render_stage, /* FALLBACK: */
167 NULL,
168 };
169
170
171
172 /* Initialize the driver's misc functions.
173 */
174 static void radeonInitDriverFuncs( struct dd_function_table *functions )
175 {
176 functions->GetString = radeonGetString;
177 }
178
179 static const struct dri_debug_control debug_control[] =
180 {
181 { "fall", DEBUG_FALLBACKS },
182 { "tex", DEBUG_TEXTURE },
183 { "ioctl", DEBUG_IOCTL },
184 { "prim", DEBUG_PRIMS },
185 { "vert", DEBUG_VERTS },
186 { "state", DEBUG_STATE },
187 { "code", DEBUG_CODEGEN },
188 { "vfmt", DEBUG_VFMT },
189 { "vtxf", DEBUG_VFMT },
190 { "verb", DEBUG_VERBOSE },
191 { "dri", DEBUG_DRI },
192 { "dma", DEBUG_DMA },
193 { "san", DEBUG_SANITY },
194 { "sync", DEBUG_SYNC },
195 { NULL, 0 }
196 };
197
198
199 /* Create the device specific context.
200 */
201 GLboolean
202 radeonCreateContext( const __GLcontextModes *glVisual,
203 __DRIcontextPrivate *driContextPriv,
204 void *sharedContextPrivate)
205 {
206 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
207 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
208 struct dd_function_table functions;
209 radeonContextPtr rmesa;
210 GLcontext *ctx, *shareCtx;
211 int i;
212 int tcl_mode, fthrottle_mode;
213
214 assert(glVisual);
215 assert(driContextPriv);
216 assert(screen);
217
218 /* Allocate the Radeon context */
219 rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
220 if ( !rmesa )
221 return GL_FALSE;
222
223 /* init exp fog table data */
224 radeonInitStaticFogData();
225
226 /* Parse configuration files.
227 * Do this here so that initialMaxAnisotropy is set before we create
228 * the default textures.
229 */
230 driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
231 screen->driScreen->myNum, "radeon");
232 rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
233 "def_max_anisotropy");
234
235 if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
236 if ( sPriv->drm_version.minor < 13 )
237 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
238 "disabling.\n", sPriv->drm_version.minor );
239 else
240 rmesa->using_hyperz = GL_TRUE;
241 }
242
243 if ( sPriv->drm_version.minor >= 15 )
244 rmesa->texmicrotile = GL_TRUE;
245
246 /* Init default driver functions then plug in our Radeon-specific functions
247 * (the texture functions are especially important)
248 */
249 _mesa_init_driver_functions( &functions );
250 radeonInitDriverFuncs( &functions );
251 radeonInitTextureFuncs( &functions );
252
253 /* Allocate the Mesa context */
254 if (sharedContextPrivate)
255 shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
256 else
257 shareCtx = NULL;
258 rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
259 &functions, (void *) rmesa);
260 if (!rmesa->glCtx) {
261 FREE(rmesa);
262 return GL_FALSE;
263 }
264 driContextPriv->driverPrivate = rmesa;
265
266 /* Init radeon context data */
267 rmesa->dri.context = driContextPriv;
268 rmesa->dri.screen = sPriv;
269 rmesa->dri.drawable = NULL;
270 rmesa->dri.readable = NULL;
271 rmesa->dri.hwContext = driContextPriv->hHWContext;
272 rmesa->dri.hwLock = &sPriv->pSAREA->lock;
273 rmesa->dri.fd = sPriv->fd;
274 rmesa->dri.drmMinor = sPriv->drm_version.minor;
275
276 rmesa->radeonScreen = screen;
277 rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
278 screen->sarea_priv_offset);
279
280
281 rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
282
283 (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
284 make_empty_list( & rmesa->swapped );
285
286 rmesa->nr_heaps = screen->numTexHeaps;
287 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
288 rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
289 screen->texSize[i],
290 12,
291 RADEON_NR_TEX_REGIONS,
292 (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
293 & rmesa->sarea->tex_age[i],
294 & rmesa->swapped,
295 sizeof( radeonTexObj ),
296 (destroy_texture_object_t *) radeonDestroyTexObj );
297
298 driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
299 & rmesa->c_textureSwaps );
300 }
301 rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
302 "texture_depth");
303 if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
304 rmesa->texture_depth = ( screen->cpp == 4 ) ?
305 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
306
307 rmesa->swtcl.RenderIndex = ~0;
308 rmesa->hw.all_dirty = GL_TRUE;
309
310 /* Set the maximum texture size small enough that we can guarentee that
311 * all texture units can bind a maximal texture and have all of them in
312 * texturable memory at once. Depending on the allow_large_textures driconf
313 * setting allow larger textures.
314 */
315
316 ctx = rmesa->glCtx;
317 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
318 "texture_units");
319 ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
320 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
321
322 i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures");
323
324 driCalculateMaxTextureLevels( rmesa->texture_heaps,
325 rmesa->nr_heaps,
326 & ctx->Const,
327 4,
328 11, /* max 2D texture size is 2048x2048 */
329 8, /* 256^3 */
330 9, /* \todo: max cube texture size seems to be 512x512(x6) */
331 11, /* max rect texture size is 2048x2048. */
332 12,
333 GL_FALSE,
334 i );
335
336
337 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
338
339 /* No wide points.
340 */
341 ctx->Const.MinPointSize = 1.0;
342 ctx->Const.MinPointSizeAA = 1.0;
343 ctx->Const.MaxPointSize = 1.0;
344 ctx->Const.MaxPointSizeAA = 1.0;
345
346 ctx->Const.MinLineWidth = 1.0;
347 ctx->Const.MinLineWidthAA = 1.0;
348 ctx->Const.MaxLineWidth = 10.0;
349 ctx->Const.MaxLineWidthAA = 10.0;
350 ctx->Const.LineWidthGranularity = 0.0625;
351
352 /* Set maxlocksize (and hence vb size) small enough to avoid
353 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
354 * fit in a single dma buffer for indexed rendering of quad strips,
355 * etc.
356 */
357 ctx->Const.MaxArrayLockSize =
358 MIN2( ctx->Const.MaxArrayLockSize,
359 RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
360
361 rmesa->boxes = 0;
362
363 /* Initialize the software rasterizer and helper modules.
364 */
365 _swrast_CreateContext( ctx );
366 _vbo_CreateContext( ctx );
367 _tnl_CreateContext( ctx );
368 _swsetup_CreateContext( ctx );
369 _ae_create_context( ctx );
370
371 /* Install the customized pipeline:
372 */
373 _tnl_destroy_pipeline( ctx );
374 _tnl_install_pipeline( ctx, radeon_pipeline );
375
376 /* Try and keep materials and vertices separate:
377 */
378 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
379
380 /* Configure swrast and T&L to match hardware characteristics:
381 */
382 _swrast_allow_pixel_fog( ctx, GL_FALSE );
383 _swrast_allow_vertex_fog( ctx, GL_TRUE );
384 _tnl_allow_pixel_fog( ctx, GL_FALSE );
385 _tnl_allow_vertex_fog( ctx, GL_TRUE );
386
387
388 for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
389 _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
390 _math_matrix_ctr( &rmesa->tmpmat[i] );
391 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
392 _math_matrix_set_identity( &rmesa->tmpmat[i] );
393 }
394
395 driInitExtensions( ctx, card_extensions, GL_TRUE );
396 if (rmesa->radeonScreen->drmSupportsCubeMapsR100)
397 _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
398 if (rmesa->glCtx->Mesa_DXTn) {
399 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
400 _mesa_enable_extension( ctx, "GL_S3_s3tc" );
401 }
402 else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
403 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
404 }
405
406 if (rmesa->dri.drmMinor >= 9)
407 _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
408
409 /* XXX these should really go right after _mesa_init_driver_functions() */
410 radeonInitIoctlFuncs( ctx );
411 radeonInitStateFuncs( ctx );
412 radeonInitSpanFuncs( ctx );
413 radeonInitState( rmesa );
414 radeonInitSwtcl( ctx );
415
416 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
417 ctx->Const.MaxArrayLockSize, 32 );
418
419 fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
420 rmesa->iw.irq_seq = -1;
421 rmesa->irqsEmitted = 0;
422 rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
423 fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
424
425 rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
426
427 (*dri_interface->getUST)( & rmesa->swap_ust );
428
429
430 #if DO_DEBUG
431 RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
432 debug_control );
433 #endif
434
435 tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
436 if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
437 fprintf(stderr, "disabling 3D acceleration\n");
438 FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
439 } else if (tcl_mode == DRI_CONF_TCL_SW ||
440 !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
441 if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
442 rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
443 fprintf(stderr, "Disabling HW TCL support\n");
444 }
445 TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
446 }
447
448 if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
449 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
450 }
451 return GL_TRUE;
452 }
453
454
455 /* Destroy the device specific context.
456 */
457 /* Destroy the Mesa and driver specific context data.
458 */
459 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
460 {
461 GET_CURRENT_CONTEXT(ctx);
462 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
463 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
464
465 /* check if we're deleting the currently bound context */
466 if (rmesa == current) {
467 RADEON_FIREVERTICES( rmesa );
468 _mesa_make_current(NULL, NULL, NULL);
469 }
470
471 /* Free radeon context resources */
472 assert(rmesa); /* should never be null */
473 if ( rmesa ) {
474 GLboolean release_texture_heaps;
475
476
477 release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
478 _swsetup_DestroyContext( rmesa->glCtx );
479 _tnl_DestroyContext( rmesa->glCtx );
480 _vbo_DestroyContext( rmesa->glCtx );
481 _swrast_DestroyContext( rmesa->glCtx );
482
483 radeonDestroySwtcl( rmesa->glCtx );
484 radeonReleaseArrays( rmesa->glCtx, ~0 );
485 if (rmesa->dma.current.buf) {
486 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
487 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
488 }
489
490 _mesa_vector4f_free( &rmesa->tcl.ObjClean );
491
492 if (rmesa->state.scissor.pClipRects) {
493 FREE(rmesa->state.scissor.pClipRects);
494 rmesa->state.scissor.pClipRects = NULL;
495 }
496
497 if ( release_texture_heaps ) {
498 /* This share group is about to go away, free our private
499 * texture object data.
500 */
501 int i;
502
503 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
504 driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
505 rmesa->texture_heaps[ i ] = NULL;
506 }
507
508 assert( is_empty_list( & rmesa->swapped ) );
509 }
510
511 /* free the Mesa context */
512 rmesa->glCtx->DriverCtx = NULL;
513 _mesa_destroy_context( rmesa->glCtx );
514
515 /* free the option cache */
516 driDestroyOptionCache (&rmesa->optionCache);
517
518 FREE( rmesa );
519 }
520 }
521
522
523
524
525 void
526 radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
527 {
528
529 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
530 radeonContextPtr rmesa;
531 GLcontext *ctx;
532 rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
533 ctx = rmesa->glCtx;
534 if (ctx->Visual.doubleBufferMode) {
535 _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */
536
537 if ( rmesa->doPageFlip ) {
538 radeonPageFlip( dPriv );
539 }
540 else {
541 radeonCopyBuffer( dPriv, NULL );
542 }
543 }
544 }
545 else {
546 /* XXX this shouldn't be an error but we can't handle it for now */
547 _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__);
548 }
549 }
550
551 void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
552 int x, int y, int w, int h )
553 {
554 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
555 radeonContextPtr radeon;
556 GLcontext *ctx;
557
558 radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
559 ctx = radeon->glCtx;
560
561 if (ctx->Visual.doubleBufferMode) {
562 drm_clip_rect_t rect;
563 rect.x1 = x + dPriv->x;
564 rect.y1 = (dPriv->h - y - h) + dPriv->y;
565 rect.x2 = rect.x1 + w;
566 rect.y2 = rect.y1 + h;
567 _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
568 radeonCopyBuffer(dPriv, &rect);
569 }
570 } else {
571 /* XXX this shouldn't be an error but we can't handle it for now */
572 _mesa_problem(NULL, "%s: drawable has no context!",
573 __FUNCTION__);
574 }
575 }
576
577 /* Make context `c' the current context and bind it to the given
578 * drawing and reading surfaces.
579 */
580 GLboolean
581 radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
582 __DRIdrawablePrivate *driDrawPriv,
583 __DRIdrawablePrivate *driReadPriv )
584 {
585 if ( driContextPriv ) {
586 radeonContextPtr newCtx =
587 (radeonContextPtr) driContextPriv->driverPrivate;
588
589 if (RADEON_DEBUG & DEBUG_DRI)
590 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
591
592 newCtx->dri.readable = driReadPriv;
593
594 if ( (newCtx->dri.drawable != driDrawPriv) ||
595 newCtx->lastStamp != driDrawPriv->lastStamp ) {
596 if (driDrawPriv->swap_interval == (unsigned)-1) {
597 driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0)
598 ? driGetDefaultVBlankFlags(&newCtx->optionCache)
599 : VBLANK_FLAG_NO_IRQ;
600
601 driDrawableInitVBlank( driDrawPriv );
602 }
603
604 newCtx->dri.drawable = driDrawPriv;
605
606 radeonSetCliprects(newCtx);
607 radeonUpdateViewportOffset( newCtx->glCtx );
608 }
609
610 _mesa_make_current( newCtx->glCtx,
611 (GLframebuffer *) driDrawPriv->driverPrivate,
612 (GLframebuffer *) driReadPriv->driverPrivate );
613
614 _mesa_update_state( newCtx->glCtx );
615 } else {
616 if (RADEON_DEBUG & DEBUG_DRI)
617 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
618 _mesa_make_current( NULL, NULL, NULL );
619 }
620
621 if (RADEON_DEBUG & DEBUG_DRI)
622 fprintf(stderr, "End %s\n", __FUNCTION__);
623 return GL_TRUE;
624 }
625
626 /* Force the context `c' to be unbound from its buffer.
627 */
628 GLboolean
629 radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
630 {
631 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
632
633 if (RADEON_DEBUG & DEBUG_DRI)
634 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
635
636 return GL_TRUE;
637 }