src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/matrix.h"
  43 #include "main/extensions.h"
  44 #include "main/framebuffer.h"
  45 #include "main/state.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55
  56 #include "radeon_common.h"
  57 #include "radeon_context.h"
  58 #include "radeon_ioctl.h"
  59 #include "radeon_state.h"
  60 #include "radeon_span.h"
  61 #include "radeon_tex.h"
  62 #include "radeon_swtcl.h"
  63 #include "radeon_tcl.h"
  64 #include "radeon_maos.h"
  65 #include "radeon_queryobj.h"
  66
  67 #define need_GL_ARB_occlusion_query
  68 #define need_GL_EXT_blend_minmax
  69 #define need_GL_EXT_fog_coord
  70 #define need_GL_EXT_secondary_color
  71 #define need_GL_EXT_framebuffer_object
  72 #include "extension_helper.h"
  73
  74 #define DRIVER_DATE     "20061018"
  75
  76 #include "vblank.h"
  77 #include "utils.h"
  78 #include "xmlpool.h" /* for symbolic values of enum-type options */
  79
  80 /* Extension strings exported by the R100 driver.
  81  */
  82 const struct dri_extension card_extensions[] =
  83 {
  84     { "GL_ARB_multitexture",               NULL },
  85     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  86     { "GL_ARB_texture_border_clamp",       NULL },
  87     { "GL_ARB_texture_env_add",            NULL },
  88     { "GL_ARB_texture_env_combine",        NULL },
  89     { "GL_ARB_texture_env_crossbar",       NULL },
  90     { "GL_ARB_texture_env_dot3",           NULL },
  91     { "GL_ARB_texture_mirrored_repeat",    NULL },
  92     { "GL_EXT_blend_logic_op",             NULL },
  93     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  94     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  95     { "GL_EXT_packed_depth_stencil",       NULL},
  96     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  97     { "GL_EXT_stencil_wrap",               NULL },
  98     { "GL_EXT_texture_edge_clamp",         NULL },
  99     { "GL_EXT_texture_env_combine",        NULL },
 100     { "GL_EXT_texture_env_dot3",           NULL },
 101     { "GL_EXT_texture_filter_anisotropic", NULL },
 102     { "GL_EXT_texture_lod_bias",           NULL },
 103     { "GL_EXT_texture_mirror_clamp",       NULL },
 104     { "GL_ATI_texture_env_combine3",       NULL },
 105     { "GL_ATI_texture_mirror_once",        NULL },
 106     { "GL_MESA_ycbcr_texture",             NULL },
 107     { "GL_NV_blend_square",                NULL },
 108     { "GL_SGIS_generate_mipmap",           NULL },
 109     { NULL,                                NULL }
 110 };
 111
 112 const struct dri_extension mm_extensions[] = {
 113   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 114   { NULL, NULL }
 115 };
 116
 117 extern const struct tnl_pipeline_stage _radeon_render_stage;
 118 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 119
 120 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 121
 122    /* Try and go straight to t&l
 123     */
 124    &_radeon_tcl_stage,
 125
 126    /* Catch any t&l fallbacks
 127     */
 128    &_tnl_vertex_transform_stage,
 129    &_tnl_normal_transform_stage,
 130    &_tnl_lighting_stage,
 131    &_tnl_fog_coordinate_stage,
 132    &_tnl_texgen_stage,
 133    &_tnl_texture_transform_stage,
 134
 135    &_radeon_render_stage,
 136    &_tnl_render_stage,          /* FALLBACK:  */
 137    NULL,
 138 };
 139
 140 static const struct dri_debug_control debug_control[] =
 141 {
 142     { "fall",  DEBUG_FALLBACKS },
 143     { "tex",   DEBUG_TEXTURE },
 144     { "ioctl", DEBUG_IOCTL },
 145     { "prim",  DEBUG_PRIMS },
 146     { "vert",  DEBUG_VERTS },
 147     { "state", DEBUG_STATE },
 148     { "code",  DEBUG_CODEGEN },
 149     { "vfmt",  DEBUG_VFMT },
 150     { "vtxf",  DEBUG_VFMT },
 151     { "verb",  DEBUG_VERBOSE },
 152     { "dri",   DEBUG_DRI },
 153     { "dma",   DEBUG_DMA },
 154     { "san",   DEBUG_SANITY },
 155     { "sync",  DEBUG_SYNC },
 156     { NULL,    0 }
 157 };
 158
 159 static void r100_get_lock(radeonContextPtr radeon)
 160 {
 161    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 162    drm_radeon_sarea_t *sarea = radeon->sarea;
 163
 164    RADEON_STATECHANGE(rmesa, ctx);
 165    if (rmesa->radeon.sarea->tiling_enabled) {
 166       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 167          RADEON_COLOR_TILE_ENABLE;
 168    } else {
 169       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 170          ~RADEON_COLOR_TILE_ENABLE;
 171    }
 172
 173    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 174       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 175
 176       if (!radeon->radeonScreen->kernel_mm)
 177          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 178    }
 179 }
 180
 181 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 182 {
 183 }
 184
 185 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 186 {
 187    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 188
 189    /* r100 always needs to emit ZBS to avoid TCL lockups */
 190    rmesa->hw.zbs.dirty = 1;
 191    radeon->hw.is_dirty = 1;
 192 }
 193
 194 static void r100_vtbl_free_context(GLcontext *ctx)
 195 {
 196    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 197    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 198 }
 199
 200 static void r100_emit_query_finish(radeonContextPtr radeon)
 201 {
 202    BATCH_LOCALS(radeon);
 203    struct radeon_query_object *query = radeon->query.current;
 204
 205    BEGIN_BATCH_NO_AUTOSTATE(4);
 206    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 207    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 208    END_BATCH();
 209    query->curr_offset += sizeof(uint32_t);
 210    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 211    query->emitted_begin = GL_FALSE;
 212 }
 213
 214 static void r100_init_vtbl(radeonContextPtr radeon)
 215 {
 216    radeon->vtbl.get_lock = r100_get_lock;
 217    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 218    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 219    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 220    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 221    radeon->vtbl.fallback = radeonFallback;
 222    radeon->vtbl.free_context = r100_vtbl_free_context;
 223    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 224 }
 225
 226 /* Create the device specific context.
 227  */
 228 GLboolean
 229 r100CreateContext( const __GLcontextModes *glVisual,
 230                      __DRIcontextPrivate *driContextPriv,
 231                      void *sharedContextPrivate)
 232 {
 233    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 234    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 235    struct dd_function_table functions;
 236    r100ContextPtr rmesa;
 237    GLcontext *ctx;
 238    int i;
 239    int tcl_mode, fthrottle_mode;
 240
 241    assert(glVisual);
 242    assert(driContextPriv);
 243    assert(screen);
 244
 245    /* Allocate the Radeon context */
 246    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 247    if ( !rmesa )
 248       return GL_FALSE;
 249
 250    r100_init_vtbl(&rmesa->radeon);
 251
 252    /* init exp fog table data */
 253    radeonInitStaticFogData();
 254
 255    /* Parse configuration files.
 256     * Do this here so that initialMaxAnisotropy is set before we create
 257     * the default textures.
 258     */
 259    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 260                         screen->driScreen->myNum, "radeon");
 261    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 262                                                  "def_max_anisotropy");
 263
 264    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 265       if ( sPriv->drm_version.minor < 13 )
 266          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 267                           "disabling.\n", sPriv->drm_version.minor );
 268       else
 269          rmesa->using_hyperz = GL_TRUE;
 270    }
 271
 272    if ( sPriv->drm_version.minor >= 15 )
 273       rmesa->texmicrotile = GL_TRUE;
 274
 275    /* Init default driver functions then plug in our Radeon-specific functions
 276     * (the texture functions are especially important)
 277     */
 278    _mesa_init_driver_functions( &functions );
 279    radeonInitTextureFuncs( &functions );
 280    radeonInitQueryObjFunctions(&functions);
 281
 282    if (!radeonInitContext(&rmesa->radeon, &functions,
 283                           glVisual, driContextPriv,
 284                           sharedContextPrivate)) {
 285      FREE(rmesa);
 286      return GL_FALSE;
 287    }
 288
 289    rmesa->radeon.swtcl.RenderIndex = ~0;
 290    rmesa->radeon.hw.all_dirty = GL_TRUE;
 291
 292    /* Set the maximum texture size small enough that we can guarentee that
 293     * all texture units can bind a maximal texture and have all of them in
 294     * texturable memory at once. Depending on the allow_large_textures driconf
 295     * setting allow larger textures.
 296     */
 297
 298    ctx = rmesa->radeon.glCtx;
 299    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 300                                                  "texture_units");
 301    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 302    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 303
 304    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 305
 306    /* FIXME: When no memory manager is available we should set this
 307     * to some reasonable value based on texture memory pool size */
 308    ctx->Const.MaxTextureLevels = 12;
 309    ctx->Const.Max3DTextureLevels = 9;
 310    ctx->Const.MaxCubeTextureLevels = 12;
 311    ctx->Const.MaxTextureRectSize = 2048;
 312
 313    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 314
 315    /* No wide points.
 316     */
 317    ctx->Const.MinPointSize = 1.0;
 318    ctx->Const.MinPointSizeAA = 1.0;
 319    ctx->Const.MaxPointSize = 1.0;
 320    ctx->Const.MaxPointSizeAA = 1.0;
 321
 322    ctx->Const.MinLineWidth = 1.0;
 323    ctx->Const.MinLineWidthAA = 1.0;
 324    ctx->Const.MaxLineWidth = 10.0;
 325    ctx->Const.MaxLineWidthAA = 10.0;
 326    ctx->Const.LineWidthGranularity = 0.0625;
 327
 328    /* Set maxlocksize (and hence vb size) small enough to avoid
 329     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 330     * fit in a single dma buffer for indexed rendering of quad strips,
 331     * etc.
 332     */
 333    ctx->Const.MaxArrayLockSize =
 334       MIN2( ctx->Const.MaxArrayLockSize,
 335             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 336
 337    rmesa->boxes = 0;
 338
 339    ctx->Const.MaxDrawBuffers = 1;
 340
 341    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 342
 343    /* Initialize the software rasterizer and helper modules.
 344     */
 345    _swrast_CreateContext( ctx );
 346    _vbo_CreateContext( ctx );
 347    _tnl_CreateContext( ctx );
 348    _swsetup_CreateContext( ctx );
 349    _ae_create_context( ctx );
 350
 351    /* Install the customized pipeline:
 352     */
 353    _tnl_destroy_pipeline( ctx );
 354    _tnl_install_pipeline( ctx, radeon_pipeline );
 355
 356    /* Try and keep materials and vertices separate:
 357     */
 358 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 359
 360    /* Configure swrast and T&L to match hardware characteristics:
 361     */
 362    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 363    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 364    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 365    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 366
 367
 368    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 369       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 370       _math_matrix_ctr( &rmesa->tmpmat[i] );
 371       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 372       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 373    }
 374
 375    driInitExtensions( ctx, card_extensions, GL_TRUE );
 376    if (rmesa->radeon.radeonScreen->kernel_mm)
 377      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 378    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 379       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 380    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 381       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 382       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 383    }
 384    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 385       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 386    }
 387
 388    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 389       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 390
 391    if (!rmesa->radeon.radeonScreen->kernel_mm)
 392       _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 393
 394    /* XXX these should really go right after _mesa_init_driver_functions() */
 395    radeon_fbo_init(&rmesa->radeon);
 396    radeonInitSpanFuncs( ctx );
 397    radeonInitIoctlFuncs( ctx );
 398    radeonInitStateFuncs( ctx , rmesa->radeon.radeonScreen->kernel_mm );
 399    radeonInitState( rmesa );
 400    radeonInitSwtcl( ctx );
 401
 402    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 403                          ctx->Const.MaxArrayLockSize, 32 );
 404
 405    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 406    rmesa->radeon.iw.irq_seq = -1;
 407    rmesa->radeon.irqsEmitted = 0;
 408    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 409                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 410
 411    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 412
 413
 414 #if DO_DEBUG
 415    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 416                                        debug_control );
 417 #endif
 418
 419    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 420    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 421       fprintf(stderr, "disabling 3D acceleration\n");
 422       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 423    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 424               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 425       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 426          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 427          fprintf(stderr, "Disabling HW TCL support\n");
 428       }
 429       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 430    }
 431
 432    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 433 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 434    }
 435    return GL_TRUE;
 436 }