src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include <stdbool.h>
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/extensions.h"
  44 #include "main/mfeatures.h"
  45
  46 #include "swrast/swrast.h"
  47 #include "swrast_setup/swrast_setup.h"
  48 #include "vbo/vbo.h"
  49
  50 #include "tnl/tnl.h"
  51 #include "tnl/t_pipeline.h"
  52
  53 #include "drivers/common/driverfuncs.h"
  54
  55 #include "radeon_common.h"
  56 #include "radeon_context.h"
  57 #include "radeon_ioctl.h"
  58 #include "radeon_state.h"
  59 #include "radeon_span.h"
  60 #include "radeon_tex.h"
  61 #include "radeon_swtcl.h"
  62 #include "radeon_tcl.h"
  63 #include "radeon_queryobj.h"
  64 #include "radeon_blit.h"
  65
  66 #include "utils.h"
  67 #include "xmlpool.h" /* for symbolic values of enum-type options */
  68
  69 extern const struct tnl_pipeline_stage _radeon_render_stage;
  70 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
  71
  72 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
  73
  74    /* Try and go straight to t&l
  75     */
  76    &_radeon_tcl_stage,
  77
  78    /* Catch any t&l fallbacks
  79     */
  80    &_tnl_vertex_transform_stage,
  81    &_tnl_normal_transform_stage,
  82    &_tnl_lighting_stage,
  83    &_tnl_fog_coordinate_stage,
  84    &_tnl_texgen_stage,
  85    &_tnl_texture_transform_stage,
  86
  87    &_radeon_render_stage,
  88    &_tnl_render_stage,          /* FALLBACK:  */
  89    NULL,
  90 };
  91
  92 static void r100_get_lock(radeonContextPtr radeon)
  93 {
  94    r100ContextPtr rmesa = (r100ContextPtr)radeon;
  95    drm_radeon_sarea_t *sarea = radeon->sarea;
  96
  97    RADEON_STATECHANGE(rmesa, ctx);
  98    if (rmesa->radeon.sarea->tiling_enabled) {
  99       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 100          RADEON_COLOR_TILE_ENABLE;
 101    } else {
 102       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 103          ~RADEON_COLOR_TILE_ENABLE;
 104    }
 105
 106    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 107       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 108    }
 109 }
 110
 111 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 112 {
 113 }
 114
 115 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 116 {
 117    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 118
 119    /* r100 always needs to emit ZBS to avoid TCL lockups */
 120    rmesa->hw.zbs.dirty = 1;
 121    radeon->hw.is_dirty = 1;
 122 }
 123
 124 static void r100_vtbl_free_context(struct gl_context *ctx)
 125 {
 126    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 127    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 128 }
 129
 130 static void r100_emit_query_finish(radeonContextPtr radeon)
 131 {
 132    BATCH_LOCALS(radeon);
 133    struct radeon_query_object *query = radeon->query.current;
 134
 135    BEGIN_BATCH_NO_AUTOSTATE(4);
 136    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 137    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 138    END_BATCH();
 139    query->curr_offset += sizeof(uint32_t);
 140    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 141    query->emitted_begin = GL_FALSE;
 142 }
 143
 144 static void r100_init_vtbl(radeonContextPtr radeon)
 145 {
 146    radeon->vtbl.get_lock = r100_get_lock;
 147    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 148    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 149    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 150    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 151    radeon->vtbl.fallback = radeonFallback;
 152    radeon->vtbl.free_context = r100_vtbl_free_context;
 153    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 154    radeon->vtbl.check_blit = r100_check_blit;
 155    radeon->vtbl.blit = r100_blit;
 156    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 157 }
 158
 159 /* Create the device specific context.
 160  */
 161 GLboolean
 162 r100CreateContext( gl_api api,
 163                    const struct gl_config *glVisual,
 164                    __DRIcontext *driContextPriv,
 165                    void *sharedContextPrivate)
 166 {
 167    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 168    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 169    struct dd_function_table functions;
 170    r100ContextPtr rmesa;
 171    struct gl_context *ctx;
 172    int i;
 173    int tcl_mode, fthrottle_mode;
 174
 175    assert(glVisual);
 176    assert(driContextPriv);
 177    assert(screen);
 178
 179    /* Allocate the Radeon context */
 180    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 181    if ( !rmesa )
 182       return GL_FALSE;
 183
 184    rmesa->radeon.radeonScreen = screen;
 185    r100_init_vtbl(&rmesa->radeon);
 186
 187    /* init exp fog table data */
 188    radeonInitStaticFogData();
 189
 190    /* Parse configuration files.
 191     * Do this here so that initialMaxAnisotropy is set before we create
 192     * the default textures.
 193     */
 194    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 195                         screen->driScreen->myNum, "radeon");
 196    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 197                                                  "def_max_anisotropy");
 198
 199    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 200       if ( sPriv->drm_version.minor < 13 )
 201          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 202                           "disabling.\n", sPriv->drm_version.minor );
 203       else
 204          rmesa->using_hyperz = GL_TRUE;
 205    }
 206
 207    if ( sPriv->drm_version.minor >= 15 )
 208       rmesa->texmicrotile = GL_TRUE;
 209
 210    /* Init default driver functions then plug in our Radeon-specific functions
 211     * (the texture functions are especially important)
 212     */
 213    _mesa_init_driver_functions( &functions );
 214    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 215    radeonInitQueryObjFunctions(&functions);
 216
 217    if (!radeonInitContext(&rmesa->radeon, &functions,
 218                           glVisual, driContextPriv,
 219                           sharedContextPrivate)) {
 220      FREE(rmesa);
 221      return GL_FALSE;
 222    }
 223
 224    rmesa->radeon.swtcl.RenderIndex = ~0;
 225    rmesa->radeon.hw.all_dirty = GL_TRUE;
 226
 227    /* Set the maximum texture size small enough that we can guarentee that
 228     * all texture units can bind a maximal texture and have all of them in
 229     * texturable memory at once. Depending on the allow_large_textures driconf
 230     * setting allow larger textures.
 231     */
 232
 233    ctx = rmesa->radeon.glCtx;
 234    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 235                                                  "texture_units");
 236    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 237    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 238    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 239
 240    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 241
 242    /* FIXME: When no memory manager is available we should set this
 243     * to some reasonable value based on texture memory pool size */
 244    ctx->Const.MaxTextureLevels = 12;
 245    ctx->Const.Max3DTextureLevels = 9;
 246    ctx->Const.MaxCubeTextureLevels = 12;
 247    ctx->Const.MaxTextureRectSize = 2048;
 248
 249    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 250
 251    /* No wide points.
 252     */
 253    ctx->Const.MinPointSize = 1.0;
 254    ctx->Const.MinPointSizeAA = 1.0;
 255    ctx->Const.MaxPointSize = 1.0;
 256    ctx->Const.MaxPointSizeAA = 1.0;
 257
 258    ctx->Const.MinLineWidth = 1.0;
 259    ctx->Const.MinLineWidthAA = 1.0;
 260    ctx->Const.MaxLineWidth = 10.0;
 261    ctx->Const.MaxLineWidthAA = 10.0;
 262    ctx->Const.LineWidthGranularity = 0.0625;
 263
 264    /* Set maxlocksize (and hence vb size) small enough to avoid
 265     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 266     * fit in a single dma buffer for indexed rendering of quad strips,
 267     * etc.
 268     */
 269    ctx->Const.MaxArrayLockSize =
 270       MIN2( ctx->Const.MaxArrayLockSize,
 271             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 272
 273    rmesa->boxes = 0;
 274
 275    ctx->Const.MaxDrawBuffers = 1;
 276    ctx->Const.MaxColorAttachments = 1;
 277    ctx->Const.MaxRenderbufferSize = 2048;
 278
 279    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 280
 281    /* Initialize the software rasterizer and helper modules.
 282     */
 283    _swrast_CreateContext( ctx );
 284    _vbo_CreateContext( ctx );
 285    _tnl_CreateContext( ctx );
 286    _swsetup_CreateContext( ctx );
 287    _ae_create_context( ctx );
 288
 289    /* Install the customized pipeline:
 290     */
 291    _tnl_destroy_pipeline( ctx );
 292    _tnl_install_pipeline( ctx, radeon_pipeline );
 293
 294    /* Try and keep materials and vertices separate:
 295     */
 296 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 297
 298    /* Configure swrast and T&L to match hardware characteristics:
 299     */
 300    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 301    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 302    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 303    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 304
 305
 306    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 307       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 308       _math_matrix_ctr( &rmesa->tmpmat[i] );
 309       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 310       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 311    }
 312
 313    ctx->Extensions.ARB_texture_border_clamp = true;
 314    ctx->Extensions.ARB_texture_env_combine = true;
 315    ctx->Extensions.ARB_texture_env_crossbar = true;
 316    ctx->Extensions.ARB_texture_env_dot3 = true;
 317    ctx->Extensions.EXT_fog_coord = true;
 318    ctx->Extensions.EXT_packed_depth_stencil = true;
 319    ctx->Extensions.EXT_secondary_color = true;
 320    ctx->Extensions.EXT_texture_env_dot3 = true;
 321    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 322    ctx->Extensions.EXT_texture_mirror_clamp = true;
 323    ctx->Extensions.ATI_texture_env_combine3 = true;
 324    ctx->Extensions.ATI_texture_mirror_once = true;
 325    ctx->Extensions.MESA_ycbcr_texture = true;
 326    ctx->Extensions.NV_blend_square = true;
 327 #if FEATURE_OES_EGL_image
 328    ctx->Extensions.OES_EGL_image = true;
 329 #endif
 330
 331    ctx->Extensions.EXT_framebuffer_object = true;
 332
 333    ctx->Extensions.ARB_texture_cube_map = true;
 334
 335    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 336       ctx->Extensions.EXT_texture_compression_s3tc = true;
 337       ctx->Extensions.S3_s3tc = true;
 338    }
 339    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 340       ctx->Extensions.EXT_texture_compression_s3tc = true;
 341    }
 342
 343    ctx->Extensions.NV_texture_rectangle = true;
 344    ctx->Extensions.ARB_occlusion_query = true;
 345
 346    /* XXX these should really go right after _mesa_init_driver_functions() */
 347    radeon_fbo_init(&rmesa->radeon);
 348    radeonInitSpanFuncs( ctx );
 349    radeonInitIoctlFuncs( ctx );
 350    radeonInitStateFuncs( ctx );
 351    radeonInitState( rmesa );
 352    radeonInitSwtcl( ctx );
 353
 354    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 355                          ctx->Const.MaxArrayLockSize, 32 );
 356
 357    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 358    rmesa->radeon.iw.irq_seq = -1;
 359    rmesa->radeon.irqsEmitted = 0;
 360    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 361                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 362
 363    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 364
 365
 366 #if DO_DEBUG
 367    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 368                                        debug_control );
 369 #endif
 370
 371    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 372    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 373       fprintf(stderr, "disabling 3D acceleration\n");
 374       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 375    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 376               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 377       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 378          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 379          fprintf(stderr, "Disabling HW TCL support\n");
 380       }
 381       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 382    }
 383
 384    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 385 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 386    }
 387    return GL_TRUE;
 388 }