src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include <stdbool.h>
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/api_exec.h"
  41 #include "main/context.h"
  42 #include "main/simple_list.h"
  43 #include "main/imports.h"
  44 #include "main/extensions.h"
  45 #include "main/version.h"
  46 #include "main/vtxfmt.h"
  47
  48 #include "swrast/swrast.h"
  49 #include "swrast_setup/swrast_setup.h"
  50 #include "vbo/vbo.h"
  51
  52 #include "tnl/tnl.h"
  53 #include "tnl/t_pipeline.h"
  54
  55 #include "drivers/common/driverfuncs.h"
  56
  57 #include "radeon_common.h"
  58 #include "radeon_context.h"
  59 #include "radeon_ioctl.h"
  60 #include "radeon_state.h"
  61 #include "radeon_span.h"
  62 #include "radeon_tex.h"
  63 #include "radeon_swtcl.h"
  64 #include "radeon_tcl.h"
  65 #include "radeon_queryobj.h"
  66 #include "radeon_blit.h"
  67 #include "radeon_fog.h"
  68
  69 #include "utils.h"
  70 #include "xmlpool.h" /* for symbolic values of enum-type options */
  71
  72 extern const struct tnl_pipeline_stage _radeon_render_stage;
  73 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
  74
  75 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
  76
  77    /* Try and go straight to t&l
  78     */
  79    &_radeon_tcl_stage,
  80
  81    /* Catch any t&l fallbacks
  82     */
  83    &_tnl_vertex_transform_stage,
  84    &_tnl_normal_transform_stage,
  85    &_tnl_lighting_stage,
  86    &_tnl_fog_coordinate_stage,
  87    &_tnl_texgen_stage,
  88    &_tnl_texture_transform_stage,
  89
  90    &_radeon_render_stage,
  91    &_tnl_render_stage,          /* FALLBACK:  */
  92    NULL,
  93 };
  94
  95 static void r100_get_lock(radeonContextPtr radeon)
  96 {
  97    r100ContextPtr rmesa = (r100ContextPtr)radeon;
  98    drm_radeon_sarea_t *sarea = radeon->sarea;
  99
 100    RADEON_STATECHANGE(rmesa, ctx);
 101    if (rmesa->radeon.sarea->tiling_enabled) {
 102       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 103          RADEON_COLOR_TILE_ENABLE;
 104    } else {
 105       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 106          ~RADEON_COLOR_TILE_ENABLE;
 107    }
 108
 109    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 110       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 111    }
 112 }
 113
 114 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 115 {
 116 }
 117
 118 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 119 {
 120    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 121
 122    /* r100 always needs to emit ZBS to avoid TCL lockups */
 123    rmesa->hw.zbs.dirty = 1;
 124    radeon->hw.is_dirty = 1;
 125 }
 126
 127 static void r100_vtbl_free_context(struct gl_context *ctx)
 128 {
 129    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 130    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 131 }
 132
 133 static void r100_emit_query_finish(radeonContextPtr radeon)
 134 {
 135    BATCH_LOCALS(radeon);
 136    struct radeon_query_object *query = radeon->query.current;
 137
 138    BEGIN_BATCH_NO_AUTOSTATE(4);
 139    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 140    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 141    END_BATCH();
 142    query->curr_offset += sizeof(uint32_t);
 143    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 144    query->emitted_begin = GL_FALSE;
 145 }
 146
 147 static void r100_init_vtbl(radeonContextPtr radeon)
 148 {
 149    radeon->vtbl.get_lock = r100_get_lock;
 150    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 151    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 152    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 153    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 154    radeon->vtbl.fallback = radeonFallback;
 155    radeon->vtbl.free_context = r100_vtbl_free_context;
 156    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 157    radeon->vtbl.check_blit = r100_check_blit;
 158    radeon->vtbl.blit = r100_blit;
 159    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 160 }
 161
 162 /* Create the device specific context.
 163  */
 164 GLboolean
 165 r100CreateContext( gl_api api,
 166                    const struct gl_config *glVisual,
 167                    __DRIcontext *driContextPriv,
 168                    unsigned major_version,
 169                    unsigned minor_version,
 170                    uint32_t flags,
 171                    unsigned *error,
 172                    void *sharedContextPrivate)
 173 {
 174    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 175    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
 176    struct dd_function_table functions;
 177    r100ContextPtr rmesa;
 178    struct gl_context *ctx;
 179    int i;
 180    int tcl_mode, fthrottle_mode;
 181
 182    switch (api) {
 183    case API_OPENGL_COMPAT:
 184       if (major_version > 1 || minor_version > 3) {
 185          *error = __DRI_CTX_ERROR_BAD_VERSION;
 186          return GL_FALSE;
 187       }
 188       break;
 189    case API_OPENGLES:
 190       break;
 191    default:
 192       *error = __DRI_CTX_ERROR_BAD_API;
 193       return GL_FALSE;
 194    }
 195
 196    /* Flag filtering is handled in dri2CreateContextAttribs.
 197     */
 198    (void) flags;
 199
 200    assert(glVisual);
 201    assert(driContextPriv);
 202    assert(screen);
 203
 204    /* Allocate the Radeon context */
 205    rmesa = calloc(1, sizeof(*rmesa));
 206    if ( !rmesa ) {
 207       *error = __DRI_CTX_ERROR_NO_MEMORY;
 208       return GL_FALSE;
 209    }
 210
 211    rmesa->radeon.radeonScreen = screen;
 212    r100_init_vtbl(&rmesa->radeon);
 213
 214    /* init exp fog table data */
 215    radeonInitStaticFogData();
 216
 217    /* Parse configuration files.
 218     * Do this here so that initialMaxAnisotropy is set before we create
 219     * the default textures.
 220     */
 221    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 222                         screen->driScreen->myNum, "radeon");
 223    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 224                                                  "def_max_anisotropy");
 225
 226    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 227       if ( sPriv->drm_version.minor < 13 )
 228          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 229                           "disabling.\n", sPriv->drm_version.minor );
 230       else
 231          rmesa->using_hyperz = GL_TRUE;
 232    }
 233
 234    if ( sPriv->drm_version.minor >= 15 )
 235       rmesa->texmicrotile = GL_TRUE;
 236
 237    /* Init default driver functions then plug in our Radeon-specific functions
 238     * (the texture functions are especially important)
 239     */
 240    _mesa_init_driver_functions( &functions );
 241    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 242    radeonInitQueryObjFunctions(&functions);
 243
 244    if (!radeonInitContext(&rmesa->radeon, &functions,
 245                           glVisual, driContextPriv,
 246                           sharedContextPrivate)) {
 247      free(rmesa);
 248      *error = __DRI_CTX_ERROR_NO_MEMORY;
 249      return GL_FALSE;
 250    }
 251
 252    rmesa->radeon.swtcl.RenderIndex = ~0;
 253    rmesa->radeon.hw.all_dirty = GL_TRUE;
 254
 255    ctx = &rmesa->radeon.glCtx;
 256    /* Initialize the software rasterizer and helper modules.
 257     */
 258    _swrast_CreateContext( ctx );
 259    _vbo_CreateContext( ctx );
 260    _tnl_CreateContext( ctx );
 261    _swsetup_CreateContext( ctx );
 262    _ae_create_context( ctx );
 263
 264    /* Set the maximum texture size small enough that we can guarentee that
 265     * all texture units can bind a maximal texture and have all of them in
 266     * texturable memory at once. Depending on the allow_large_textures driconf
 267     * setting allow larger textures.
 268     */
 269
 270    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 271                                                  "texture_units");
 272    ctx->Const.FragmentProgram.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 273    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 274    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 275
 276    ctx->Const.StripTextureBorder = GL_TRUE;
 277
 278    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 279
 280    /* FIXME: When no memory manager is available we should set this
 281     * to some reasonable value based on texture memory pool size */
 282    ctx->Const.MaxTextureLevels = 12;
 283    ctx->Const.Max3DTextureLevels = 9;
 284    ctx->Const.MaxCubeTextureLevels = 12;
 285    ctx->Const.MaxTextureRectSize = 2048;
 286
 287    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 288
 289    /* No wide points.
 290     */
 291    ctx->Const.MinPointSize = 1.0;
 292    ctx->Const.MinPointSizeAA = 1.0;
 293    ctx->Const.MaxPointSize = 1.0;
 294    ctx->Const.MaxPointSizeAA = 1.0;
 295
 296    ctx->Const.MinLineWidth = 1.0;
 297    ctx->Const.MinLineWidthAA = 1.0;
 298    ctx->Const.MaxLineWidth = 10.0;
 299    ctx->Const.MaxLineWidthAA = 10.0;
 300    ctx->Const.LineWidthGranularity = 0.0625;
 301
 302    /* Set maxlocksize (and hence vb size) small enough to avoid
 303     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 304     * fit in a single dma buffer for indexed rendering of quad strips,
 305     * etc.
 306     */
 307    ctx->Const.MaxArrayLockSize =
 308       MIN2( ctx->Const.MaxArrayLockSize,
 309             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 310
 311    rmesa->boxes = 0;
 312
 313    ctx->Const.MaxDrawBuffers = 1;
 314    ctx->Const.MaxColorAttachments = 1;
 315    ctx->Const.MaxRenderbufferSize = 2048;
 316
 317    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 318
 319    /* Install the customized pipeline:
 320     */
 321    _tnl_destroy_pipeline( ctx );
 322    _tnl_install_pipeline( ctx, radeon_pipeline );
 323
 324    /* Try and keep materials and vertices separate:
 325     */
 326 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 327
 328    /* Configure swrast and T&L to match hardware characteristics:
 329     */
 330    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 331    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 332    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 333    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 334
 335
 336    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 337       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 338       _math_matrix_ctr( &rmesa->tmpmat[i] );
 339       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 340       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 341    }
 342
 343    ctx->Extensions.ARB_texture_border_clamp = true;
 344    ctx->Extensions.ARB_texture_env_combine = true;
 345    ctx->Extensions.ARB_texture_env_crossbar = true;
 346    ctx->Extensions.ARB_texture_env_dot3 = true;
 347    ctx->Extensions.EXT_fog_coord = true;
 348    ctx->Extensions.EXT_packed_depth_stencil = true;
 349    ctx->Extensions.EXT_secondary_color = true;
 350    ctx->Extensions.EXT_texture_env_dot3 = true;
 351    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 352    ctx->Extensions.EXT_texture_mirror_clamp = true;
 353    ctx->Extensions.ATI_texture_env_combine3 = true;
 354    ctx->Extensions.ATI_texture_mirror_once = true;
 355    ctx->Extensions.MESA_ycbcr_texture = true;
 356    ctx->Extensions.NV_blend_square = true;
 357    ctx->Extensions.OES_EGL_image = true;
 358    ctx->Extensions.EXT_framebuffer_object = true;
 359    ctx->Extensions.ARB_texture_cube_map = true;
 360
 361    if (rmesa->radeon.glCtx.Mesa_DXTn) {
 362       ctx->Extensions.EXT_texture_compression_s3tc = true;
 363       ctx->Extensions.ANGLE_texture_compression_dxt = true;
 364    }
 365    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 366       ctx->Extensions.EXT_texture_compression_s3tc = true;
 367       ctx->Extensions.ANGLE_texture_compression_dxt = true;
 368    }
 369
 370    ctx->Extensions.NV_texture_rectangle = true;
 371    ctx->Extensions.ARB_occlusion_query = true;
 372
 373    /* XXX these should really go right after _mesa_init_driver_functions() */
 374    radeon_fbo_init(&rmesa->radeon);
 375    radeonInitSpanFuncs( ctx );
 376    radeonInitIoctlFuncs( ctx );
 377    radeonInitStateFuncs( ctx );
 378    radeonInitState( rmesa );
 379    radeonInitSwtcl( ctx );
 380
 381    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 382                          ctx->Const.MaxArrayLockSize, 32 );
 383
 384    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 385    rmesa->radeon.iw.irq_seq = -1;
 386    rmesa->radeon.irqsEmitted = 0;
 387    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 388                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 389
 390    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 391
 392
 393 #if DO_DEBUG
 394    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 395                                        debug_control );
 396 #endif
 397
 398    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 399    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 400       fprintf(stderr, "disabling 3D acceleration\n");
 401       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 402    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 403               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 404       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 405          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 406          fprintf(stderr, "Disabling HW TCL support\n");
 407       }
 408       TCL_FALLBACK(&rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 409    }
 410
 411    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 412 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 413    }
 414
 415    _mesa_compute_version(ctx);
 416
 417    /* Exec table initialization requires the version to be computed */
 418    _mesa_initialize_dispatch_tables(ctx);
 419    _mesa_initialize_vbo_vtxfmt(ctx);
 420
 421    *error = __DRI_CTX_ERROR_SUCCESS;
 422    return GL_TRUE;
 423 }