src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/extensions.h"
  43 #include "main/mfeatures.h"
  44
  45 #include "swrast/swrast.h"
  46 #include "swrast_setup/swrast_setup.h"
  47 #include "vbo/vbo.h"
  48
  49 #include "tnl/tnl.h"
  50 #include "tnl/t_pipeline.h"
  51
  52 #include "drivers/common/driverfuncs.h"
  53
  54 #include "radeon_common.h"
  55 #include "radeon_context.h"
  56 #include "radeon_ioctl.h"
  57 #include "radeon_state.h"
  58 #include "radeon_span.h"
  59 #include "radeon_tex.h"
  60 #include "radeon_swtcl.h"
  61 #include "radeon_tcl.h"
  62 #include "radeon_queryobj.h"
  63 #include "radeon_blit.h"
  64
  65 #define need_GL_ARB_occlusion_query
  66 #define need_GL_EXT_blend_minmax
  67 #define need_GL_EXT_fog_coord
  68 #define need_GL_EXT_secondary_color
  69 #define need_GL_EXT_framebuffer_object
  70 #define need_GL_OES_EGL_image
  71 #include "main/remap_helper.h"
  72
  73 #define DRIVER_DATE     "20061018"
  74
  75 #include "utils.h"
  76 #include "xmlpool.h" /* for symbolic values of enum-type options */
  77
  78 /* Extension strings exported by the R100 driver.
  79  */
  80 static const struct dri_extension card_extensions[] =
  81 {
  82     { "GL_ARB_multitexture",               NULL },
  83     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  84     { "GL_ARB_texture_border_clamp",       NULL },
  85     { "GL_ARB_texture_env_add",            NULL },
  86     { "GL_ARB_texture_env_combine",        NULL },
  87     { "GL_ARB_texture_env_crossbar",       NULL },
  88     { "GL_ARB_texture_env_dot3",           NULL },
  89     { "GL_ARB_texture_mirrored_repeat",    NULL },
  90     { "GL_EXT_blend_logic_op",             NULL },
  91     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  92     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  93     { "GL_EXT_packed_depth_stencil",       NULL},
  94     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  95     { "GL_EXT_stencil_wrap",               NULL },
  96     { "GL_EXT_texture_edge_clamp",         NULL },
  97     { "GL_EXT_texture_env_combine",        NULL },
  98     { "GL_EXT_texture_env_dot3",           NULL },
  99     { "GL_EXT_texture_filter_anisotropic", NULL },
 100     { "GL_EXT_texture_lod_bias",           NULL },
 101     { "GL_EXT_texture_mirror_clamp",       NULL },
 102     { "GL_ATI_texture_env_combine3",       NULL },
 103     { "GL_ATI_texture_mirror_once",        NULL },
 104     { "GL_MESA_ycbcr_texture",             NULL },
 105     { "GL_NV_blend_square",                NULL },
 106 #if FEATURE_OES_EGL_image
 107     { "GL_OES_EGL_image",                  GL_OES_EGL_image_functions },
 108 #endif
 109     { NULL,                                NULL }
 110 };
 111
 112 static const struct dri_extension mm_extensions[] = {
 113   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 114   { NULL, NULL }
 115 };
 116
 117 extern const struct tnl_pipeline_stage _radeon_render_stage;
 118 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 119
 120 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 121
 122    /* Try and go straight to t&l
 123     */
 124    &_radeon_tcl_stage,
 125
 126    /* Catch any t&l fallbacks
 127     */
 128    &_tnl_vertex_transform_stage,
 129    &_tnl_normal_transform_stage,
 130    &_tnl_lighting_stage,
 131    &_tnl_fog_coordinate_stage,
 132    &_tnl_texgen_stage,
 133    &_tnl_texture_transform_stage,
 134
 135    &_radeon_render_stage,
 136    &_tnl_render_stage,          /* FALLBACK:  */
 137    NULL,
 138 };
 139
 140 static void r100_get_lock(radeonContextPtr radeon)
 141 {
 142    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 143    drm_radeon_sarea_t *sarea = radeon->sarea;
 144
 145    RADEON_STATECHANGE(rmesa, ctx);
 146    if (rmesa->radeon.sarea->tiling_enabled) {
 147       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 148          RADEON_COLOR_TILE_ENABLE;
 149    } else {
 150       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 151          ~RADEON_COLOR_TILE_ENABLE;
 152    }
 153
 154    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 155       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 156
 157       if (!radeon->radeonScreen->kernel_mm)
 158          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 159    }
 160 }
 161
 162 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 163 {
 164 }
 165
 166 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 167 {
 168    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 169
 170    /* r100 always needs to emit ZBS to avoid TCL lockups */
 171    rmesa->hw.zbs.dirty = 1;
 172    radeon->hw.is_dirty = 1;
 173 }
 174
 175 static void r100_vtbl_free_context(struct gl_context *ctx)
 176 {
 177    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 178    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 179 }
 180
 181 static void r100_emit_query_finish(radeonContextPtr radeon)
 182 {
 183    BATCH_LOCALS(radeon);
 184    struct radeon_query_object *query = radeon->query.current;
 185
 186    BEGIN_BATCH_NO_AUTOSTATE(4);
 187    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 188    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 189    END_BATCH();
 190    query->curr_offset += sizeof(uint32_t);
 191    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 192    query->emitted_begin = GL_FALSE;
 193 }
 194
 195 static void r100_init_vtbl(radeonContextPtr radeon)
 196 {
 197    radeon->vtbl.get_lock = r100_get_lock;
 198    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 199    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 200    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 201    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 202    radeon->vtbl.fallback = radeonFallback;
 203    radeon->vtbl.free_context = r100_vtbl_free_context;
 204    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 205    radeon->vtbl.check_blit = r100_check_blit;
 206    radeon->vtbl.blit = r100_blit;
 207    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 208 }
 209
 210 /* Create the device specific context.
 211  */
 212 GLboolean
 213 r100CreateContext( gl_api api,
 214                    const struct gl_config *glVisual,
 215                    __DRIcontext *driContextPriv,
 216                    void *sharedContextPrivate)
 217 {
 218    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 219    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 220    struct dd_function_table functions;
 221    r100ContextPtr rmesa;
 222    struct gl_context *ctx;
 223    int i;
 224    int tcl_mode, fthrottle_mode;
 225
 226    assert(glVisual);
 227    assert(driContextPriv);
 228    assert(screen);
 229
 230    /* Allocate the Radeon context */
 231    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 232    if ( !rmesa )
 233       return GL_FALSE;
 234
 235    rmesa->radeon.radeonScreen = screen;
 236    r100_init_vtbl(&rmesa->radeon);
 237
 238    /* init exp fog table data */
 239    radeonInitStaticFogData();
 240
 241    /* Parse configuration files.
 242     * Do this here so that initialMaxAnisotropy is set before we create
 243     * the default textures.
 244     */
 245    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 246                         screen->driScreen->myNum, "radeon");
 247    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 248                                                  "def_max_anisotropy");
 249
 250    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 251       if ( sPriv->drm_version.minor < 13 )
 252          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 253                           "disabling.\n", sPriv->drm_version.minor );
 254       else
 255          rmesa->using_hyperz = GL_TRUE;
 256    }
 257
 258    if ( sPriv->drm_version.minor >= 15 )
 259       rmesa->texmicrotile = GL_TRUE;
 260
 261    /* Init default driver functions then plug in our Radeon-specific functions
 262     * (the texture functions are especially important)
 263     */
 264    _mesa_init_driver_functions( &functions );
 265    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 266    radeonInitQueryObjFunctions(&functions);
 267
 268    if (!radeonInitContext(&rmesa->radeon, &functions,
 269                           glVisual, driContextPriv,
 270                           sharedContextPrivate)) {
 271      FREE(rmesa);
 272      return GL_FALSE;
 273    }
 274
 275    rmesa->radeon.swtcl.RenderIndex = ~0;
 276    rmesa->radeon.hw.all_dirty = GL_TRUE;
 277
 278    /* Set the maximum texture size small enough that we can guarentee that
 279     * all texture units can bind a maximal texture and have all of them in
 280     * texturable memory at once. Depending on the allow_large_textures driconf
 281     * setting allow larger textures.
 282     */
 283
 284    ctx = rmesa->radeon.glCtx;
 285    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 286                                                  "texture_units");
 287    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 288    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 289    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 290
 291    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 292
 293    /* FIXME: When no memory manager is available we should set this
 294     * to some reasonable value based on texture memory pool size */
 295    ctx->Const.MaxTextureLevels = 12;
 296    ctx->Const.Max3DTextureLevels = 9;
 297    ctx->Const.MaxCubeTextureLevels = 12;
 298    ctx->Const.MaxTextureRectSize = 2048;
 299
 300    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 301
 302    /* No wide points.
 303     */
 304    ctx->Const.MinPointSize = 1.0;
 305    ctx->Const.MinPointSizeAA = 1.0;
 306    ctx->Const.MaxPointSize = 1.0;
 307    ctx->Const.MaxPointSizeAA = 1.0;
 308
 309    ctx->Const.MinLineWidth = 1.0;
 310    ctx->Const.MinLineWidthAA = 1.0;
 311    ctx->Const.MaxLineWidth = 10.0;
 312    ctx->Const.MaxLineWidthAA = 10.0;
 313    ctx->Const.LineWidthGranularity = 0.0625;
 314
 315    /* Set maxlocksize (and hence vb size) small enough to avoid
 316     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 317     * fit in a single dma buffer for indexed rendering of quad strips,
 318     * etc.
 319     */
 320    ctx->Const.MaxArrayLockSize =
 321       MIN2( ctx->Const.MaxArrayLockSize,
 322             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 323
 324    rmesa->boxes = 0;
 325
 326    ctx->Const.MaxDrawBuffers = 1;
 327    ctx->Const.MaxColorAttachments = 1;
 328    ctx->Const.MaxRenderbufferSize = 2048;
 329
 330    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 331
 332    /* Initialize the software rasterizer and helper modules.
 333     */
 334    _swrast_CreateContext( ctx );
 335    _vbo_CreateContext( ctx );
 336    _tnl_CreateContext( ctx );
 337    _swsetup_CreateContext( ctx );
 338    _ae_create_context( ctx );
 339
 340    /* Install the customized pipeline:
 341     */
 342    _tnl_destroy_pipeline( ctx );
 343    _tnl_install_pipeline( ctx, radeon_pipeline );
 344
 345    /* Try and keep materials and vertices separate:
 346     */
 347 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 348
 349    /* Configure swrast and T&L to match hardware characteristics:
 350     */
 351    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 352    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 353    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 354    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 355
 356
 357    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 358       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 359       _math_matrix_ctr( &rmesa->tmpmat[i] );
 360       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 361       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 362    }
 363
 364    driInitExtensions( ctx, card_extensions, GL_TRUE );
 365    if (rmesa->radeon.radeonScreen->kernel_mm)
 366      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 367    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 368       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 369    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 370       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 371       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 372    }
 373    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 374       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 375    }
 376
 377    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 378       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 379
 380    if (!rmesa->radeon.radeonScreen->kernel_mm)
 381       _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 382
 383    /* XXX these should really go right after _mesa_init_driver_functions() */
 384    radeon_fbo_init(&rmesa->radeon);
 385    radeonInitSpanFuncs( ctx );
 386    radeonInitIoctlFuncs( ctx );
 387    radeonInitStateFuncs( ctx , rmesa->radeon.radeonScreen->kernel_mm );
 388    radeonInitState( rmesa );
 389    radeonInitSwtcl( ctx );
 390
 391    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 392                          ctx->Const.MaxArrayLockSize, 32 );
 393
 394    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 395    rmesa->radeon.iw.irq_seq = -1;
 396    rmesa->radeon.irqsEmitted = 0;
 397    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 398                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 399
 400    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 401
 402
 403 #if DO_DEBUG
 404    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 405                                        debug_control );
 406 #endif
 407
 408    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 409    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 410       fprintf(stderr, "disabling 3D acceleration\n");
 411       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 412    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 413               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 414       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 415          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 416          fprintf(stderr, "Disabling HW TCL support\n");
 417       }
 418       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 419    }
 420
 421    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 422 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 423    }
 424    return GL_TRUE;
 425 }