Merge branch 'master' into gallium-0.2
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_context.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
35 */
36
37 #include "main/glheader.h"
38 #include "main/api_arrayelt.h"
39 #include "main/context.h"
40 #include "main/simple_list.h"
41 #include "main/imports.h"
42 #include "main/matrix.h"
43 #include "main/extensions.h"
44 #include "main/framebuffer.h"
45 #include "main/state.h"
46
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
49 #include "vbo/vbo.h"
50
51 #include "tnl/tnl.h"
52 #include "tnl/t_pipeline.h"
53
54 #include "drivers/common/driverfuncs.h"
55
56 #include "radeon_context.h"
57 #include "radeon_ioctl.h"
58 #include "radeon_state.h"
59 #include "radeon_span.h"
60 #include "radeon_tex.h"
61 #include "radeon_swtcl.h"
62 #include "radeon_tcl.h"
63 #include "radeon_maos.h"
64
65 #define need_GL_ARB_multisample
66 #define need_GL_ARB_texture_compression
67 #define need_GL_ARB_vertex_buffer_object
68 #define need_GL_EXT_blend_minmax
69 #define need_GL_EXT_fog_coord
70 #define need_GL_EXT_secondary_color
71 #include "extension_helper.h"
72
73 #define DRIVER_DATE "20061018"
74
75 #include "vblank.h"
76 #include "utils.h"
77 #include "xmlpool.h" /* for symbolic values of enum-type options */
78 #ifndef RADEON_DEBUG
79 int RADEON_DEBUG = (0);
80 #endif
81
82
83 /* Return various strings for glGetString().
84 */
85 static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
86 {
87 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
88 static char buffer[128];
89 unsigned offset;
90 GLuint agp_mode = (rmesa->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
91 rmesa->radeonScreen->AGPMode;
92
93 switch ( name ) {
94 case GL_VENDOR:
95 return (GLubyte *)"Tungsten Graphics, Inc.";
96
97 case GL_RENDERER:
98 offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
99 agp_mode );
100
101 sprintf( & buffer[ offset ], " %sTCL",
102 !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
103 ? "" : "NO-" );
104
105 return (GLubyte *)buffer;
106
107 default:
108 return NULL;
109 }
110 }
111
112
113 /* Extension strings exported by the R100 driver.
114 */
115 const struct dri_extension card_extensions[] =
116 {
117 { "GL_ARB_multisample", GL_ARB_multisample_functions },
118 { "GL_ARB_multitexture", NULL },
119 { "GL_ARB_texture_border_clamp", NULL },
120 { "GL_ARB_texture_compression", GL_ARB_texture_compression_functions },
121 { "GL_ARB_texture_env_add", NULL },
122 { "GL_ARB_texture_env_combine", NULL },
123 { "GL_ARB_texture_env_crossbar", NULL },
124 { "GL_ARB_texture_env_dot3", NULL },
125 { "GL_ARB_texture_mirrored_repeat", NULL },
126 { "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
127 { "GL_EXT_blend_logic_op", NULL },
128 { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions },
129 { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
130 { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions },
131 { "GL_EXT_stencil_wrap", NULL },
132 { "GL_EXT_texture_edge_clamp", NULL },
133 { "GL_EXT_texture_env_combine", NULL },
134 { "GL_EXT_texture_env_dot3", NULL },
135 { "GL_EXT_texture_filter_anisotropic", NULL },
136 { "GL_EXT_texture_lod_bias", NULL },
137 { "GL_EXT_texture_mirror_clamp", NULL },
138 { "GL_ATI_texture_env_combine3", NULL },
139 { "GL_ATI_texture_mirror_once", NULL },
140 { "GL_MESA_ycbcr_texture", NULL },
141 { "GL_NV_blend_square", NULL },
142 { "GL_SGIS_generate_mipmap", NULL },
143 { NULL, NULL }
144 };
145
146 extern const struct tnl_pipeline_stage _radeon_render_stage;
147 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
148
149 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
150
151 /* Try and go straight to t&l
152 */
153 &_radeon_tcl_stage,
154
155 /* Catch any t&l fallbacks
156 */
157 &_tnl_vertex_transform_stage,
158 &_tnl_normal_transform_stage,
159 &_tnl_lighting_stage,
160 &_tnl_fog_coordinate_stage,
161 &_tnl_texgen_stage,
162 &_tnl_texture_transform_stage,
163
164 &_radeon_render_stage,
165 &_tnl_render_stage, /* FALLBACK: */
166 NULL,
167 };
168
169
170
171 /* Initialize the driver's misc functions.
172 */
173 static void radeonInitDriverFuncs( struct dd_function_table *functions )
174 {
175 functions->GetString = radeonGetString;
176 }
177
178 static const struct dri_debug_control debug_control[] =
179 {
180 { "fall", DEBUG_FALLBACKS },
181 { "tex", DEBUG_TEXTURE },
182 { "ioctl", DEBUG_IOCTL },
183 { "prim", DEBUG_PRIMS },
184 { "vert", DEBUG_VERTS },
185 { "state", DEBUG_STATE },
186 { "code", DEBUG_CODEGEN },
187 { "vfmt", DEBUG_VFMT },
188 { "vtxf", DEBUG_VFMT },
189 { "verb", DEBUG_VERBOSE },
190 { "dri", DEBUG_DRI },
191 { "dma", DEBUG_DMA },
192 { "san", DEBUG_SANITY },
193 { "sync", DEBUG_SYNC },
194 { NULL, 0 }
195 };
196
197
198 /* Create the device specific context.
199 */
200 GLboolean
201 radeonCreateContext( const __GLcontextModes *glVisual,
202 __DRIcontextPrivate *driContextPriv,
203 void *sharedContextPrivate)
204 {
205 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
206 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
207 struct dd_function_table functions;
208 radeonContextPtr rmesa;
209 GLcontext *ctx, *shareCtx;
210 int i;
211 int tcl_mode, fthrottle_mode;
212
213 assert(glVisual);
214 assert(driContextPriv);
215 assert(screen);
216
217 /* Allocate the Radeon context */
218 rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
219 if ( !rmesa )
220 return GL_FALSE;
221
222 /* init exp fog table data */
223 radeonInitStaticFogData();
224
225 /* Parse configuration files.
226 * Do this here so that initialMaxAnisotropy is set before we create
227 * the default textures.
228 */
229 driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
230 screen->driScreen->myNum, "radeon");
231 rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
232 "def_max_anisotropy");
233
234 if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
235 if ( sPriv->drm_version.minor < 13 )
236 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
237 "disabling.\n", sPriv->drm_version.minor );
238 else
239 rmesa->using_hyperz = GL_TRUE;
240 }
241
242 if ( sPriv->drm_version.minor >= 15 )
243 rmesa->texmicrotile = GL_TRUE;
244
245 /* Init default driver functions then plug in our Radeon-specific functions
246 * (the texture functions are especially important)
247 */
248 _mesa_init_driver_functions( &functions );
249 radeonInitDriverFuncs( &functions );
250 radeonInitTextureFuncs( &functions );
251
252 /* Allocate the Mesa context */
253 if (sharedContextPrivate)
254 shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
255 else
256 shareCtx = NULL;
257 rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
258 &functions, (void *) rmesa);
259 if (!rmesa->glCtx) {
260 FREE(rmesa);
261 return GL_FALSE;
262 }
263 driContextPriv->driverPrivate = rmesa;
264
265 /* Init radeon context data */
266 rmesa->dri.context = driContextPriv;
267 rmesa->dri.screen = sPriv;
268 rmesa->dri.drawable = NULL;
269 rmesa->dri.readable = NULL;
270 rmesa->dri.hwContext = driContextPriv->hHWContext;
271 rmesa->dri.hwLock = &sPriv->pSAREA->lock;
272 rmesa->dri.fd = sPriv->fd;
273 rmesa->dri.drmMinor = sPriv->drm_version.minor;
274
275 rmesa->radeonScreen = screen;
276 rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
277 screen->sarea_priv_offset);
278
279
280 rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
281
282 (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
283 make_empty_list( & rmesa->swapped );
284
285 rmesa->nr_heaps = screen->numTexHeaps;
286 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
287 rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
288 screen->texSize[i],
289 12,
290 RADEON_NR_TEX_REGIONS,
291 (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
292 & rmesa->sarea->tex_age[i],
293 & rmesa->swapped,
294 sizeof( radeonTexObj ),
295 (destroy_texture_object_t *) radeonDestroyTexObj );
296
297 driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
298 & rmesa->c_textureSwaps );
299 }
300 rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
301 "texture_depth");
302 if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
303 rmesa->texture_depth = ( screen->cpp == 4 ) ?
304 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
305
306 rmesa->swtcl.RenderIndex = ~0;
307 rmesa->hw.all_dirty = GL_TRUE;
308
309 /* Set the maximum texture size small enough that we can guarentee that
310 * all texture units can bind a maximal texture and have all of them in
311 * texturable memory at once. Depending on the allow_large_textures driconf
312 * setting allow larger textures.
313 */
314
315 ctx = rmesa->glCtx;
316 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
317 "texture_units");
318 ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
319 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
320
321 i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures");
322
323 driCalculateMaxTextureLevels( rmesa->texture_heaps,
324 rmesa->nr_heaps,
325 & ctx->Const,
326 4,
327 11, /* max 2D texture size is 2048x2048 */
328 8, /* 256^3 */
329 9, /* \todo: max cube texture size seems to be 512x512(x6) */
330 11, /* max rect texture size is 2048x2048. */
331 12,
332 GL_FALSE,
333 i );
334
335
336 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
337
338 /* No wide points.
339 */
340 ctx->Const.MinPointSize = 1.0;
341 ctx->Const.MinPointSizeAA = 1.0;
342 ctx->Const.MaxPointSize = 1.0;
343 ctx->Const.MaxPointSizeAA = 1.0;
344
345 ctx->Const.MinLineWidth = 1.0;
346 ctx->Const.MinLineWidthAA = 1.0;
347 ctx->Const.MaxLineWidth = 10.0;
348 ctx->Const.MaxLineWidthAA = 10.0;
349 ctx->Const.LineWidthGranularity = 0.0625;
350
351 /* Set maxlocksize (and hence vb size) small enough to avoid
352 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
353 * fit in a single dma buffer for indexed rendering of quad strips,
354 * etc.
355 */
356 ctx->Const.MaxArrayLockSize =
357 MIN2( ctx->Const.MaxArrayLockSize,
358 RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
359
360 rmesa->boxes = 0;
361
362 /* Initialize the software rasterizer and helper modules.
363 */
364 _swrast_CreateContext( ctx );
365 _vbo_CreateContext( ctx );
366 _tnl_CreateContext( ctx );
367 _swsetup_CreateContext( ctx );
368 _ae_create_context( ctx );
369
370 /* Install the customized pipeline:
371 */
372 _tnl_destroy_pipeline( ctx );
373 _tnl_install_pipeline( ctx, radeon_pipeline );
374
375 /* Try and keep materials and vertices separate:
376 */
377 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
378
379 /* Configure swrast and T&L to match hardware characteristics:
380 */
381 _swrast_allow_pixel_fog( ctx, GL_FALSE );
382 _swrast_allow_vertex_fog( ctx, GL_TRUE );
383 _tnl_allow_pixel_fog( ctx, GL_FALSE );
384 _tnl_allow_vertex_fog( ctx, GL_TRUE );
385
386
387 for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
388 _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
389 _math_matrix_ctr( &rmesa->tmpmat[i] );
390 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
391 _math_matrix_set_identity( &rmesa->tmpmat[i] );
392 }
393
394 driInitExtensions( ctx, card_extensions, GL_TRUE );
395 if (rmesa->radeonScreen->drmSupportsCubeMapsR100)
396 _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
397 if (rmesa->glCtx->Mesa_DXTn) {
398 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
399 _mesa_enable_extension( ctx, "GL_S3_s3tc" );
400 }
401 else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
402 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
403 }
404
405 if (rmesa->dri.drmMinor >= 9)
406 _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
407
408 /* XXX these should really go right after _mesa_init_driver_functions() */
409 radeonInitIoctlFuncs( ctx );
410 radeonInitStateFuncs( ctx );
411 radeonInitSpanFuncs( ctx );
412 radeonInitState( rmesa );
413 radeonInitSwtcl( ctx );
414
415 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
416 ctx->Const.MaxArrayLockSize, 32 );
417
418 fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
419 rmesa->iw.irq_seq = -1;
420 rmesa->irqsEmitted = 0;
421 rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
422 fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
423
424 rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
425
426 (*sPriv->systemTime->getUST)( & rmesa->swap_ust );
427
428
429 #if DO_DEBUG
430 RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
431 debug_control );
432 #endif
433
434 tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
435 if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
436 fprintf(stderr, "disabling 3D acceleration\n");
437 FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
438 } else if (tcl_mode == DRI_CONF_TCL_SW ||
439 !(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
440 if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
441 rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
442 fprintf(stderr, "Disabling HW TCL support\n");
443 }
444 TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
445 }
446
447 if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
448 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
449 }
450 return GL_TRUE;
451 }
452
453
454 /* Destroy the device specific context.
455 */
456 /* Destroy the Mesa and driver specific context data.
457 */
458 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
459 {
460 GET_CURRENT_CONTEXT(ctx);
461 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
462 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
463
464 /* check if we're deleting the currently bound context */
465 if (rmesa == current) {
466 RADEON_FIREVERTICES( rmesa );
467 _mesa_make_current(NULL, NULL, NULL);
468 }
469
470 /* Free radeon context resources */
471 assert(rmesa); /* should never be null */
472 if ( rmesa ) {
473 GLboolean release_texture_heaps;
474
475
476 release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
477 _swsetup_DestroyContext( rmesa->glCtx );
478 _tnl_DestroyContext( rmesa->glCtx );
479 _vbo_DestroyContext( rmesa->glCtx );
480 _swrast_DestroyContext( rmesa->glCtx );
481
482 radeonDestroySwtcl( rmesa->glCtx );
483 radeonReleaseArrays( rmesa->glCtx, ~0 );
484 if (rmesa->dma.current.buf) {
485 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
486 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
487 }
488
489 _mesa_vector4f_free( &rmesa->tcl.ObjClean );
490
491 if (rmesa->state.scissor.pClipRects) {
492 FREE(rmesa->state.scissor.pClipRects);
493 rmesa->state.scissor.pClipRects = NULL;
494 }
495
496 if ( release_texture_heaps ) {
497 /* This share group is about to go away, free our private
498 * texture object data.
499 */
500 int i;
501
502 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
503 driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
504 rmesa->texture_heaps[ i ] = NULL;
505 }
506
507 assert( is_empty_list( & rmesa->swapped ) );
508 }
509
510 /* free the Mesa context */
511 rmesa->glCtx->DriverCtx = NULL;
512 _mesa_destroy_context( rmesa->glCtx );
513
514 /* free the option cache */
515 driDestroyOptionCache (&rmesa->optionCache);
516
517 FREE( rmesa );
518 }
519 }
520
521
522
523
524 void
525 radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
526 {
527
528 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
529 radeonContextPtr rmesa;
530 GLcontext *ctx;
531 rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
532 ctx = rmesa->glCtx;
533 if (ctx->Visual.doubleBufferMode) {
534 _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */
535
536 if ( rmesa->doPageFlip ) {
537 radeonPageFlip( dPriv );
538 }
539 else {
540 radeonCopyBuffer( dPriv, NULL );
541 }
542 }
543 }
544 else {
545 /* XXX this shouldn't be an error but we can't handle it for now */
546 _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__);
547 }
548 }
549
550 void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
551 int x, int y, int w, int h )
552 {
553 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
554 radeonContextPtr radeon;
555 GLcontext *ctx;
556
557 radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
558 ctx = radeon->glCtx;
559
560 if (ctx->Visual.doubleBufferMode) {
561 drm_clip_rect_t rect;
562 rect.x1 = x + dPriv->x;
563 rect.y1 = (dPriv->h - y - h) + dPriv->y;
564 rect.x2 = rect.x1 + w;
565 rect.y2 = rect.y1 + h;
566 _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
567 radeonCopyBuffer(dPriv, &rect);
568 }
569 } else {
570 /* XXX this shouldn't be an error but we can't handle it for now */
571 _mesa_problem(NULL, "%s: drawable has no context!",
572 __FUNCTION__);
573 }
574 }
575
576 /* Make context `c' the current context and bind it to the given
577 * drawing and reading surfaces.
578 */
579 GLboolean
580 radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
581 __DRIdrawablePrivate *driDrawPriv,
582 __DRIdrawablePrivate *driReadPriv )
583 {
584 if ( driContextPriv ) {
585 radeonContextPtr newCtx =
586 (radeonContextPtr) driContextPriv->driverPrivate;
587
588 if (RADEON_DEBUG & DEBUG_DRI)
589 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
590
591 newCtx->dri.readable = driReadPriv;
592
593 if ( (newCtx->dri.drawable != driDrawPriv) ||
594 newCtx->lastStamp != driDrawPriv->lastStamp ) {
595 if (driDrawPriv->swap_interval == (unsigned)-1) {
596 driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0)
597 ? driGetDefaultVBlankFlags(&newCtx->optionCache)
598 : VBLANK_FLAG_NO_IRQ;
599
600 driDrawableInitVBlank( driDrawPriv );
601 }
602
603 newCtx->dri.drawable = driDrawPriv;
604
605 radeonSetCliprects(newCtx);
606 radeonUpdateViewportOffset( newCtx->glCtx );
607 }
608
609 _mesa_make_current( newCtx->glCtx,
610 (GLframebuffer *) driDrawPriv->driverPrivate,
611 (GLframebuffer *) driReadPriv->driverPrivate );
612
613 _mesa_update_state( newCtx->glCtx );
614 } else {
615 if (RADEON_DEBUG & DEBUG_DRI)
616 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
617 _mesa_make_current( NULL, NULL, NULL );
618 }
619
620 if (RADEON_DEBUG & DEBUG_DRI)
621 fprintf(stderr, "End %s\n", __FUNCTION__);
622 return GL_TRUE;
623 }
624
625 /* Force the context `c' to be unbound from its buffer.
626 */
627 GLboolean
628 radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
629 {
630 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
631
632 if (RADEON_DEBUG & DEBUG_DRI)
633 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
634
635 return GL_TRUE;
636 }