src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/extensions.h"
  43
  44 #include "swrast/swrast.h"
  45 #include "swrast_setup/swrast_setup.h"
  46 #include "vbo/vbo.h"
  47
  48 #include "tnl/tnl.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "drivers/common/driverfuncs.h"
  52
  53 #include "radeon_common.h"
  54 #include "radeon_context.h"
  55 #include "radeon_ioctl.h"
  56 #include "radeon_state.h"
  57 #include "radeon_span.h"
  58 #include "radeon_tex.h"
  59 #include "radeon_swtcl.h"
  60 #include "radeon_tcl.h"
  61 #include "radeon_queryobj.h"
  62 #include "radeon_blit.h"
  63
  64 #define need_GL_ARB_occlusion_query
  65 #define need_GL_EXT_blend_minmax
  66 #define need_GL_EXT_fog_coord
  67 #define need_GL_EXT_secondary_color
  68 #define need_GL_EXT_framebuffer_object
  69 #define need_GL_OES_EGL_image
  70 #include "main/remap_helper.h"
  71
  72 #define DRIVER_DATE     "20061018"
  73
  74 #include "utils.h"
  75 #include "xmlpool.h" /* for symbolic values of enum-type options */
  76
  77 /* Extension strings exported by the R100 driver.
  78  */
  79 static const struct dri_extension card_extensions[] =
  80 {
  81     { "GL_ARB_multitexture",               NULL },
  82     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  83     { "GL_ARB_texture_border_clamp",       NULL },
  84     { "GL_ARB_texture_env_add",            NULL },
  85     { "GL_ARB_texture_env_combine",        NULL },
  86     { "GL_ARB_texture_env_crossbar",       NULL },
  87     { "GL_ARB_texture_env_dot3",           NULL },
  88     { "GL_ARB_texture_mirrored_repeat",    NULL },
  89     { "GL_EXT_blend_logic_op",             NULL },
  90     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  91     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  92     { "GL_EXT_packed_depth_stencil",       NULL},
  93     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  94     { "GL_EXT_stencil_wrap",               NULL },
  95     { "GL_EXT_texture_edge_clamp",         NULL },
  96     { "GL_EXT_texture_env_combine",        NULL },
  97     { "GL_EXT_texture_env_dot3",           NULL },
  98     { "GL_EXT_texture_filter_anisotropic", NULL },
  99     { "GL_EXT_texture_lod_bias",           NULL },
 100     { "GL_EXT_texture_mirror_clamp",       NULL },
 101     { "GL_ATI_texture_env_combine3",       NULL },
 102     { "GL_ATI_texture_mirror_once",        NULL },
 103     { "GL_MESA_ycbcr_texture",             NULL },
 104     { "GL_NV_blend_square",                NULL },
 105 #if FEATURE_OES_EGL_image
 106     { "GL_OES_EGL_image",                  GL_OES_EGL_image_functions },
 107 #endif
 108     { NULL,                                NULL }
 109 };
 110
 111 static const struct dri_extension mm_extensions[] = {
 112   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 113   { NULL, NULL }
 114 };
 115
 116 extern const struct tnl_pipeline_stage _radeon_render_stage;
 117 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 118
 119 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 120
 121    /* Try and go straight to t&l
 122     */
 123    &_radeon_tcl_stage,
 124
 125    /* Catch any t&l fallbacks
 126     */
 127    &_tnl_vertex_transform_stage,
 128    &_tnl_normal_transform_stage,
 129    &_tnl_lighting_stage,
 130    &_tnl_fog_coordinate_stage,
 131    &_tnl_texgen_stage,
 132    &_tnl_texture_transform_stage,
 133
 134    &_radeon_render_stage,
 135    &_tnl_render_stage,          /* FALLBACK:  */
 136    NULL,
 137 };
 138
 139 static void r100_get_lock(radeonContextPtr radeon)
 140 {
 141    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 142    drm_radeon_sarea_t *sarea = radeon->sarea;
 143
 144    RADEON_STATECHANGE(rmesa, ctx);
 145    if (rmesa->radeon.sarea->tiling_enabled) {
 146       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 147          RADEON_COLOR_TILE_ENABLE;
 148    } else {
 149       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 150          ~RADEON_COLOR_TILE_ENABLE;
 151    }
 152
 153    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 154       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 155
 156       if (!radeon->radeonScreen->kernel_mm)
 157          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 158    }
 159 }
 160
 161 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 162 {
 163 }
 164
 165 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 166 {
 167    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 168
 169    /* r100 always needs to emit ZBS to avoid TCL lockups */
 170    rmesa->hw.zbs.dirty = 1;
 171    radeon->hw.is_dirty = 1;
 172 }
 173
 174 static void r100_vtbl_free_context(struct gl_context *ctx)
 175 {
 176    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 177    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 178 }
 179
 180 static void r100_emit_query_finish(radeonContextPtr radeon)
 181 {
 182    BATCH_LOCALS(radeon);
 183    struct radeon_query_object *query = radeon->query.current;
 184
 185    BEGIN_BATCH_NO_AUTOSTATE(4);
 186    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 187    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 188    END_BATCH();
 189    query->curr_offset += sizeof(uint32_t);
 190    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 191    query->emitted_begin = GL_FALSE;
 192 }
 193
 194 static void r100_init_vtbl(radeonContextPtr radeon)
 195 {
 196    radeon->vtbl.get_lock = r100_get_lock;
 197    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 198    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 199    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 200    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 201    radeon->vtbl.fallback = radeonFallback;
 202    radeon->vtbl.free_context = r100_vtbl_free_context;
 203    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 204    radeon->vtbl.check_blit = r100_check_blit;
 205    radeon->vtbl.blit = r100_blit;
 206    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 207 }
 208
 209 /* Create the device specific context.
 210  */
 211 GLboolean
 212 r100CreateContext( gl_api api,
 213                    const struct gl_config *glVisual,
 214                    __DRIcontext *driContextPriv,
 215                    void *sharedContextPrivate)
 216 {
 217    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 218    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 219    struct dd_function_table functions;
 220    r100ContextPtr rmesa;
 221    struct gl_context *ctx;
 222    int i;
 223    int tcl_mode, fthrottle_mode;
 224
 225    assert(glVisual);
 226    assert(driContextPriv);
 227    assert(screen);
 228
 229    /* Allocate the Radeon context */
 230    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 231    if ( !rmesa )
 232       return GL_FALSE;
 233
 234    rmesa->radeon.radeonScreen = screen;
 235    r100_init_vtbl(&rmesa->radeon);
 236
 237    /* init exp fog table data */
 238    radeonInitStaticFogData();
 239
 240    /* Parse configuration files.
 241     * Do this here so that initialMaxAnisotropy is set before we create
 242     * the default textures.
 243     */
 244    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 245                         screen->driScreen->myNum, "radeon");
 246    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 247                                                  "def_max_anisotropy");
 248
 249    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 250       if ( sPriv->drm_version.minor < 13 )
 251          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 252                           "disabling.\n", sPriv->drm_version.minor );
 253       else
 254          rmesa->using_hyperz = GL_TRUE;
 255    }
 256
 257    if ( sPriv->drm_version.minor >= 15 )
 258       rmesa->texmicrotile = GL_TRUE;
 259
 260    /* Init default driver functions then plug in our Radeon-specific functions
 261     * (the texture functions are especially important)
 262     */
 263    _mesa_init_driver_functions( &functions );
 264    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 265    radeonInitQueryObjFunctions(&functions);
 266
 267    if (!radeonInitContext(&rmesa->radeon, &functions,
 268                           glVisual, driContextPriv,
 269                           sharedContextPrivate)) {
 270      FREE(rmesa);
 271      return GL_FALSE;
 272    }
 273
 274    rmesa->radeon.swtcl.RenderIndex = ~0;
 275    rmesa->radeon.hw.all_dirty = GL_TRUE;
 276
 277    /* Set the maximum texture size small enough that we can guarentee that
 278     * all texture units can bind a maximal texture and have all of them in
 279     * texturable memory at once. Depending on the allow_large_textures driconf
 280     * setting allow larger textures.
 281     */
 282
 283    ctx = rmesa->radeon.glCtx;
 284    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 285                                                  "texture_units");
 286    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 287    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 288    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 289
 290    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 291
 292    /* FIXME: When no memory manager is available we should set this
 293     * to some reasonable value based on texture memory pool size */
 294    ctx->Const.MaxTextureLevels = 12;
 295    ctx->Const.Max3DTextureLevels = 9;
 296    ctx->Const.MaxCubeTextureLevels = 12;
 297    ctx->Const.MaxTextureRectSize = 2048;
 298
 299    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 300
 301    /* No wide points.
 302     */
 303    ctx->Const.MinPointSize = 1.0;
 304    ctx->Const.MinPointSizeAA = 1.0;
 305    ctx->Const.MaxPointSize = 1.0;
 306    ctx->Const.MaxPointSizeAA = 1.0;
 307
 308    ctx->Const.MinLineWidth = 1.0;
 309    ctx->Const.MinLineWidthAA = 1.0;
 310    ctx->Const.MaxLineWidth = 10.0;
 311    ctx->Const.MaxLineWidthAA = 10.0;
 312    ctx->Const.LineWidthGranularity = 0.0625;
 313
 314    /* Set maxlocksize (and hence vb size) small enough to avoid
 315     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 316     * fit in a single dma buffer for indexed rendering of quad strips,
 317     * etc.
 318     */
 319    ctx->Const.MaxArrayLockSize =
 320       MIN2( ctx->Const.MaxArrayLockSize,
 321             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 322
 323    rmesa->boxes = 0;
 324
 325    ctx->Const.MaxDrawBuffers = 1;
 326    ctx->Const.MaxColorAttachments = 1;
 327    ctx->Const.MaxRenderbufferSize = 2048;
 328
 329    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 330
 331    /* Initialize the software rasterizer and helper modules.
 332     */
 333    _swrast_CreateContext( ctx );
 334    _vbo_CreateContext( ctx );
 335    _tnl_CreateContext( ctx );
 336    _swsetup_CreateContext( ctx );
 337    _ae_create_context( ctx );
 338
 339    /* Install the customized pipeline:
 340     */
 341    _tnl_destroy_pipeline( ctx );
 342    _tnl_install_pipeline( ctx, radeon_pipeline );
 343
 344    /* Try and keep materials and vertices separate:
 345     */
 346 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 347
 348    /* Configure swrast and T&L to match hardware characteristics:
 349     */
 350    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 351    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 352    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 353    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 354
 355
 356    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 357       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 358       _math_matrix_ctr( &rmesa->tmpmat[i] );
 359       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 360       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 361    }
 362
 363    driInitExtensions( ctx, card_extensions, GL_TRUE );
 364    if (rmesa->radeon.radeonScreen->kernel_mm)
 365      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 366    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 367       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 368    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 369       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 370       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 371    }
 372    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 373       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 374    }
 375
 376    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 377       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 378
 379    if (!rmesa->radeon.radeonScreen->kernel_mm)
 380       _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 381
 382    /* XXX these should really go right after _mesa_init_driver_functions() */
 383    radeon_fbo_init(&rmesa->radeon);
 384    radeonInitSpanFuncs( ctx );
 385    radeonInitIoctlFuncs( ctx );
 386    radeonInitStateFuncs( ctx , rmesa->radeon.radeonScreen->kernel_mm );
 387    radeonInitState( rmesa );
 388    radeonInitSwtcl( ctx );
 389
 390    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 391                          ctx->Const.MaxArrayLockSize, 32 );
 392
 393    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 394    rmesa->radeon.iw.irq_seq = -1;
 395    rmesa->radeon.irqsEmitted = 0;
 396    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 397                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 398
 399    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 400
 401
 402 #if DO_DEBUG
 403    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 404                                        debug_control );
 405 #endif
 406
 407    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 408    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 409       fprintf(stderr, "disabling 3D acceleration\n");
 410       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 411    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 412               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 413       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 414          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 415          fprintf(stderr, "Disabling HW TCL support\n");
 416       }
 417       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 418    }
 419
 420    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 421 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 422    }
 423    return GL_TRUE;
 424 }