1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/api_exec.h"
41 #include "main/context.h"
42 #include "main/simple_list.h"
43 #include "main/imports.h"
44 #include "main/extensions.h"
45 #include "main/mfeatures.h"
46 #include "main/version.h"
47 #include "main/vtxfmt.h"
49 #include "swrast/swrast.h"
50 #include "swrast_setup/swrast_setup.h"
54 #include "tnl/t_pipeline.h"
56 #include "drivers/common/driverfuncs.h"
58 #include "radeon_common.h"
59 #include "radeon_context.h"
60 #include "radeon_ioctl.h"
61 #include "radeon_state.h"
62 #include "radeon_span.h"
63 #include "radeon_tex.h"
64 #include "radeon_swtcl.h"
65 #include "radeon_tcl.h"
66 #include "radeon_queryobj.h"
67 #include "radeon_blit.h"
68 #include "radeon_fog.h"
71 #include "xmlpool.h" /* for symbolic values of enum-type options */
73 extern const struct tnl_pipeline_stage _radeon_render_stage
;
74 extern const struct tnl_pipeline_stage _radeon_tcl_stage
;
76 static const struct tnl_pipeline_stage
*radeon_pipeline
[] = {
78 /* Try and go straight to t&l
82 /* Catch any t&l fallbacks
84 &_tnl_vertex_transform_stage
,
85 &_tnl_normal_transform_stage
,
87 &_tnl_fog_coordinate_stage
,
89 &_tnl_texture_transform_stage
,
91 &_radeon_render_stage
,
92 &_tnl_render_stage
, /* FALLBACK: */
96 static void r100_get_lock(radeonContextPtr radeon
)
98 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
99 drm_radeon_sarea_t
*sarea
= radeon
->sarea
;
101 RADEON_STATECHANGE(rmesa
, ctx
);
102 if (rmesa
->radeon
.sarea
->tiling_enabled
) {
103 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |=
104 RADEON_COLOR_TILE_ENABLE
;
106 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] &=
107 ~RADEON_COLOR_TILE_ENABLE
;
110 if (sarea
->ctx_owner
!= rmesa
->radeon
.dri
.hwContext
) {
111 sarea
->ctx_owner
= rmesa
->radeon
.dri
.hwContext
;
115 static void r100_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
119 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon
)
121 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
123 /* r100 always needs to emit ZBS to avoid TCL lockups */
124 rmesa
->hw
.zbs
.dirty
= 1;
125 radeon
->hw
.is_dirty
= 1;
128 static void r100_vtbl_free_context(struct gl_context
*ctx
)
130 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
131 _mesa_vector4f_free( &rmesa
->tcl
.ObjClean
);
134 static void r100_emit_query_finish(radeonContextPtr radeon
)
136 BATCH_LOCALS(radeon
);
137 struct radeon_query_object
*query
= radeon
->query
.current
;
139 BEGIN_BATCH_NO_AUTOSTATE(4);
140 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR
, 0));
141 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
143 query
->curr_offset
+= sizeof(uint32_t);
144 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
145 query
->emitted_begin
= GL_FALSE
;
148 static void r100_init_vtbl(radeonContextPtr radeon
)
150 radeon
->vtbl
.get_lock
= r100_get_lock
;
151 radeon
->vtbl
.update_viewport_offset
= radeonUpdateViewportOffset
;
152 radeon
->vtbl
.emit_cs_header
= r100_vtbl_emit_cs_header
;
153 radeon
->vtbl
.swtcl_flush
= r100_swtcl_flush
;
154 radeon
->vtbl
.pre_emit_state
= r100_vtbl_pre_emit_state
;
155 radeon
->vtbl
.fallback
= radeonFallback
;
156 radeon
->vtbl
.free_context
= r100_vtbl_free_context
;
157 radeon
->vtbl
.emit_query_finish
= r100_emit_query_finish
;
158 radeon
->vtbl
.check_blit
= r100_check_blit
;
159 radeon
->vtbl
.blit
= r100_blit
;
160 radeon
->vtbl
.is_format_renderable
= radeonIsFormatRenderable
;
163 /* Create the device specific context.
166 r100CreateContext( gl_api api
,
167 const struct gl_config
*glVisual
,
168 __DRIcontext
*driContextPriv
,
169 unsigned major_version
,
170 unsigned minor_version
,
173 void *sharedContextPrivate
)
175 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
176 radeonScreenPtr screen
= (radeonScreenPtr
)(sPriv
->driverPrivate
);
177 struct dd_function_table functions
;
178 r100ContextPtr rmesa
;
179 struct gl_context
*ctx
;
181 int tcl_mode
, fthrottle_mode
;
184 case API_OPENGL_COMPAT
:
185 if (major_version
> 1 || minor_version
> 3) {
186 *error
= __DRI_CTX_ERROR_BAD_VERSION
;
193 *error
= __DRI_CTX_ERROR_BAD_API
;
197 /* Flag filtering is handled in dri2CreateContextAttribs.
202 assert(driContextPriv
);
205 /* Allocate the Radeon context */
206 rmesa
= calloc(1, sizeof(*rmesa
));
208 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
212 rmesa
->radeon
.radeonScreen
= screen
;
213 r100_init_vtbl(&rmesa
->radeon
);
215 /* init exp fog table data */
216 radeonInitStaticFogData();
218 /* Parse configuration files.
219 * Do this here so that initialMaxAnisotropy is set before we create
220 * the default textures.
222 driParseConfigFiles (&rmesa
->radeon
.optionCache
, &screen
->optionCache
,
223 screen
->driScreen
->myNum
, "radeon");
224 rmesa
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&rmesa
->radeon
.optionCache
,
225 "def_max_anisotropy");
227 if ( driQueryOptionb( &rmesa
->radeon
.optionCache
, "hyperz" ) ) {
228 if ( sPriv
->drm_version
.minor
< 13 )
229 fprintf( stderr
, "DRM version 1.%d too old to support HyperZ, "
230 "disabling.\n", sPriv
->drm_version
.minor
);
232 rmesa
->using_hyperz
= GL_TRUE
;
235 if ( sPriv
->drm_version
.minor
>= 15 )
236 rmesa
->texmicrotile
= GL_TRUE
;
238 /* Init default driver functions then plug in our Radeon-specific functions
239 * (the texture functions are especially important)
241 _mesa_init_driver_functions( &functions
);
242 radeonInitTextureFuncs( &rmesa
->radeon
, &functions
);
243 radeonInitQueryObjFunctions(&functions
);
245 if (!radeonInitContext(&rmesa
->radeon
, &functions
,
246 glVisual
, driContextPriv
,
247 sharedContextPrivate
)) {
249 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
253 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
254 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
256 ctx
= &rmesa
->radeon
.glCtx
;
257 /* Initialize the software rasterizer and helper modules.
259 _swrast_CreateContext( ctx
);
260 _vbo_CreateContext( ctx
);
261 _tnl_CreateContext( ctx
);
262 _swsetup_CreateContext( ctx
);
263 _ae_create_context( ctx
);
265 /* Set the maximum texture size small enough that we can guarentee that
266 * all texture units can bind a maximal texture and have all of them in
267 * texturable memory at once. Depending on the allow_large_textures driconf
268 * setting allow larger textures.
271 ctx
->Const
.MaxTextureUnits
= driQueryOptioni (&rmesa
->radeon
.optionCache
,
273 ctx
->Const
.MaxTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
274 ctx
->Const
.MaxTextureCoordUnits
= ctx
->Const
.MaxTextureUnits
;
275 ctx
->Const
.MaxCombinedTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
277 ctx
->Const
.StripTextureBorder
= GL_TRUE
;
279 i
= driQueryOptioni( &rmesa
->radeon
.optionCache
, "allow_large_textures");
281 /* FIXME: When no memory manager is available we should set this
282 * to some reasonable value based on texture memory pool size */
283 ctx
->Const
.MaxTextureLevels
= 12;
284 ctx
->Const
.Max3DTextureLevels
= 9;
285 ctx
->Const
.MaxCubeTextureLevels
= 12;
286 ctx
->Const
.MaxTextureRectSize
= 2048;
288 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
292 ctx
->Const
.MinPointSize
= 1.0;
293 ctx
->Const
.MinPointSizeAA
= 1.0;
294 ctx
->Const
.MaxPointSize
= 1.0;
295 ctx
->Const
.MaxPointSizeAA
= 1.0;
297 ctx
->Const
.MinLineWidth
= 1.0;
298 ctx
->Const
.MinLineWidthAA
= 1.0;
299 ctx
->Const
.MaxLineWidth
= 10.0;
300 ctx
->Const
.MaxLineWidthAA
= 10.0;
301 ctx
->Const
.LineWidthGranularity
= 0.0625;
303 /* Set maxlocksize (and hence vb size) small enough to avoid
304 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
305 * fit in a single dma buffer for indexed rendering of quad strips,
308 ctx
->Const
.MaxArrayLockSize
=
309 MIN2( ctx
->Const
.MaxArrayLockSize
,
310 RADEON_BUFFER_SIZE
/ RADEON_MAX_TCL_VERTSIZE
);
314 ctx
->Const
.MaxDrawBuffers
= 1;
315 ctx
->Const
.MaxColorAttachments
= 1;
316 ctx
->Const
.MaxRenderbufferSize
= 2048;
318 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
320 /* Install the customized pipeline:
322 _tnl_destroy_pipeline( ctx
);
323 _tnl_install_pipeline( ctx
, radeon_pipeline
);
325 /* Try and keep materials and vertices separate:
327 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
329 /* Configure swrast and T&L to match hardware characteristics:
331 _swrast_allow_pixel_fog( ctx
, GL_FALSE
);
332 _swrast_allow_vertex_fog( ctx
, GL_TRUE
);
333 _tnl_allow_pixel_fog( ctx
, GL_FALSE
);
334 _tnl_allow_vertex_fog( ctx
, GL_TRUE
);
337 for ( i
= 0 ; i
< RADEON_MAX_TEXTURE_UNITS
; i
++ ) {
338 _math_matrix_ctr( &rmesa
->TexGenMatrix
[i
] );
339 _math_matrix_ctr( &rmesa
->tmpmat
[i
] );
340 _math_matrix_set_identity( &rmesa
->TexGenMatrix
[i
] );
341 _math_matrix_set_identity( &rmesa
->tmpmat
[i
] );
344 ctx
->Extensions
.ARB_texture_border_clamp
= true;
345 ctx
->Extensions
.ARB_texture_env_combine
= true;
346 ctx
->Extensions
.ARB_texture_env_crossbar
= true;
347 ctx
->Extensions
.ARB_texture_env_dot3
= true;
348 ctx
->Extensions
.EXT_fog_coord
= true;
349 ctx
->Extensions
.EXT_packed_depth_stencil
= true;
350 ctx
->Extensions
.EXT_secondary_color
= true;
351 ctx
->Extensions
.EXT_texture_env_dot3
= true;
352 ctx
->Extensions
.EXT_texture_filter_anisotropic
= true;
353 ctx
->Extensions
.EXT_texture_mirror_clamp
= true;
354 ctx
->Extensions
.ATI_texture_env_combine3
= true;
355 ctx
->Extensions
.ATI_texture_mirror_once
= true;
356 ctx
->Extensions
.MESA_ycbcr_texture
= true;
357 ctx
->Extensions
.NV_blend_square
= true;
358 ctx
->Extensions
.OES_EGL_image
= true;
359 ctx
->Extensions
.EXT_framebuffer_object
= true;
360 ctx
->Extensions
.ARB_texture_cube_map
= true;
362 if (rmesa
->radeon
.glCtx
.Mesa_DXTn
) {
363 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
364 ctx
->Extensions
.ANGLE_texture_compression_dxt
= true;
366 else if (driQueryOptionb (&rmesa
->radeon
.optionCache
, "force_s3tc_enable")) {
367 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
368 ctx
->Extensions
.ANGLE_texture_compression_dxt
= true;
371 ctx
->Extensions
.NV_texture_rectangle
= true;
372 ctx
->Extensions
.ARB_occlusion_query
= true;
374 /* XXX these should really go right after _mesa_init_driver_functions() */
375 radeon_fbo_init(&rmesa
->radeon
);
376 radeonInitSpanFuncs( ctx
);
377 radeonInitIoctlFuncs( ctx
);
378 radeonInitStateFuncs( ctx
);
379 radeonInitState( rmesa
);
380 radeonInitSwtcl( ctx
);
382 _mesa_vector4f_alloc( &rmesa
->tcl
.ObjClean
, 0,
383 ctx
->Const
.MaxArrayLockSize
, 32 );
385 fthrottle_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "fthrottle_mode");
386 rmesa
->radeon
.iw
.irq_seq
= -1;
387 rmesa
->radeon
.irqsEmitted
= 0;
388 rmesa
->radeon
.do_irqs
= (rmesa
->radeon
.radeonScreen
->irq
!= 0 &&
389 fthrottle_mode
== DRI_CONF_FTHROTTLE_IRQS
);
391 rmesa
->radeon
.do_usleeps
= (fthrottle_mode
== DRI_CONF_FTHROTTLE_USLEEPS
);
395 RADEON_DEBUG
= driParseDebugString( getenv( "RADEON_DEBUG" ),
399 tcl_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "tcl_mode");
400 if (driQueryOptionb(&rmesa
->radeon
.optionCache
, "no_rast")) {
401 fprintf(stderr
, "disabling 3D acceleration\n");
402 FALLBACK(rmesa
, RADEON_FALLBACK_DISABLE
, 1);
403 } else if (tcl_mode
== DRI_CONF_TCL_SW
||
404 !(rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
405 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
406 rmesa
->radeon
.radeonScreen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
407 fprintf(stderr
, "Disabling HW TCL support\n");
409 TCL_FALLBACK(&rmesa
->radeon
.glCtx
, RADEON_TCL_FALLBACK_TCL_DISABLE
, 1);
412 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
413 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
416 _mesa_compute_version(ctx
);
418 /* Exec table initialization requires the version to be computed */
419 _mesa_initialize_dispatch_tables(ctx
);
420 _mesa_initialize_vbo_vtxfmt(ctx
);
422 *error
= __DRI_CTX_ERROR_SUCCESS
;