1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/extensions.h"
44 #include "main/mfeatures.h"
46 #include "swrast/swrast.h"
47 #include "swrast_setup/swrast_setup.h"
51 #include "tnl/t_pipeline.h"
53 #include "drivers/common/driverfuncs.h"
55 #include "radeon_common.h"
56 #include "radeon_context.h"
57 #include "radeon_ioctl.h"
58 #include "radeon_state.h"
59 #include "radeon_span.h"
60 #include "radeon_tex.h"
61 #include "radeon_swtcl.h"
62 #include "radeon_tcl.h"
63 #include "radeon_queryobj.h"
64 #include "radeon_blit.h"
67 #include "xmlpool.h" /* for symbolic values of enum-type options */
69 extern const struct tnl_pipeline_stage _radeon_render_stage
;
70 extern const struct tnl_pipeline_stage _radeon_tcl_stage
;
72 static const struct tnl_pipeline_stage
*radeon_pipeline
[] = {
74 /* Try and go straight to t&l
78 /* Catch any t&l fallbacks
80 &_tnl_vertex_transform_stage
,
81 &_tnl_normal_transform_stage
,
83 &_tnl_fog_coordinate_stage
,
85 &_tnl_texture_transform_stage
,
87 &_radeon_render_stage
,
88 &_tnl_render_stage
, /* FALLBACK: */
92 static void r100_get_lock(radeonContextPtr radeon
)
94 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
95 drm_radeon_sarea_t
*sarea
= radeon
->sarea
;
97 RADEON_STATECHANGE(rmesa
, ctx
);
98 if (rmesa
->radeon
.sarea
->tiling_enabled
) {
99 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |=
100 RADEON_COLOR_TILE_ENABLE
;
102 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] &=
103 ~RADEON_COLOR_TILE_ENABLE
;
106 if (sarea
->ctx_owner
!= rmesa
->radeon
.dri
.hwContext
) {
107 sarea
->ctx_owner
= rmesa
->radeon
.dri
.hwContext
;
109 if (!radeon
->radeonScreen
->kernel_mm
)
110 radeon_bo_legacy_texture_age(radeon
->radeonScreen
->bom
);
114 static void r100_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
118 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon
)
120 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
122 /* r100 always needs to emit ZBS to avoid TCL lockups */
123 rmesa
->hw
.zbs
.dirty
= 1;
124 radeon
->hw
.is_dirty
= 1;
127 static void r100_vtbl_free_context(struct gl_context
*ctx
)
129 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
130 _mesa_vector4f_free( &rmesa
->tcl
.ObjClean
);
133 static void r100_emit_query_finish(radeonContextPtr radeon
)
135 BATCH_LOCALS(radeon
);
136 struct radeon_query_object
*query
= radeon
->query
.current
;
138 BEGIN_BATCH_NO_AUTOSTATE(4);
139 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR
, 0));
140 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
142 query
->curr_offset
+= sizeof(uint32_t);
143 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
144 query
->emitted_begin
= GL_FALSE
;
147 static void r100_init_vtbl(radeonContextPtr radeon
)
149 radeon
->vtbl
.get_lock
= r100_get_lock
;
150 radeon
->vtbl
.update_viewport_offset
= radeonUpdateViewportOffset
;
151 radeon
->vtbl
.emit_cs_header
= r100_vtbl_emit_cs_header
;
152 radeon
->vtbl
.swtcl_flush
= r100_swtcl_flush
;
153 radeon
->vtbl
.pre_emit_state
= r100_vtbl_pre_emit_state
;
154 radeon
->vtbl
.fallback
= radeonFallback
;
155 radeon
->vtbl
.free_context
= r100_vtbl_free_context
;
156 radeon
->vtbl
.emit_query_finish
= r100_emit_query_finish
;
157 radeon
->vtbl
.check_blit
= r100_check_blit
;
158 radeon
->vtbl
.blit
= r100_blit
;
159 radeon
->vtbl
.is_format_renderable
= radeonIsFormatRenderable
;
162 /* Create the device specific context.
165 r100CreateContext( gl_api api
,
166 const struct gl_config
*glVisual
,
167 __DRIcontext
*driContextPriv
,
168 void *sharedContextPrivate
)
170 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
171 radeonScreenPtr screen
= (radeonScreenPtr
)(sPriv
->private);
172 struct dd_function_table functions
;
173 r100ContextPtr rmesa
;
174 struct gl_context
*ctx
;
176 int tcl_mode
, fthrottle_mode
;
179 assert(driContextPriv
);
182 /* Allocate the Radeon context */
183 rmesa
= (r100ContextPtr
) CALLOC( sizeof(*rmesa
) );
187 rmesa
->radeon
.radeonScreen
= screen
;
188 r100_init_vtbl(&rmesa
->radeon
);
190 /* init exp fog table data */
191 radeonInitStaticFogData();
193 /* Parse configuration files.
194 * Do this here so that initialMaxAnisotropy is set before we create
195 * the default textures.
197 driParseConfigFiles (&rmesa
->radeon
.optionCache
, &screen
->optionCache
,
198 screen
->driScreen
->myNum
, "radeon");
199 rmesa
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&rmesa
->radeon
.optionCache
,
200 "def_max_anisotropy");
202 if ( driQueryOptionb( &rmesa
->radeon
.optionCache
, "hyperz" ) ) {
203 if ( sPriv
->drm_version
.minor
< 13 )
204 fprintf( stderr
, "DRM version 1.%d too old to support HyperZ, "
205 "disabling.\n", sPriv
->drm_version
.minor
);
207 rmesa
->using_hyperz
= GL_TRUE
;
210 if ( sPriv
->drm_version
.minor
>= 15 )
211 rmesa
->texmicrotile
= GL_TRUE
;
213 /* Init default driver functions then plug in our Radeon-specific functions
214 * (the texture functions are especially important)
216 _mesa_init_driver_functions( &functions
);
217 radeonInitTextureFuncs( &rmesa
->radeon
, &functions
);
218 radeonInitQueryObjFunctions(&functions
);
220 if (!radeonInitContext(&rmesa
->radeon
, &functions
,
221 glVisual
, driContextPriv
,
222 sharedContextPrivate
)) {
227 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
228 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
230 /* Set the maximum texture size small enough that we can guarentee that
231 * all texture units can bind a maximal texture and have all of them in
232 * texturable memory at once. Depending on the allow_large_textures driconf
233 * setting allow larger textures.
236 ctx
= rmesa
->radeon
.glCtx
;
237 ctx
->Const
.MaxTextureUnits
= driQueryOptioni (&rmesa
->radeon
.optionCache
,
239 ctx
->Const
.MaxTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
240 ctx
->Const
.MaxTextureCoordUnits
= ctx
->Const
.MaxTextureUnits
;
241 ctx
->Const
.MaxCombinedTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
243 i
= driQueryOptioni( &rmesa
->radeon
.optionCache
, "allow_large_textures");
245 /* FIXME: When no memory manager is available we should set this
246 * to some reasonable value based on texture memory pool size */
247 ctx
->Const
.MaxTextureLevels
= 12;
248 ctx
->Const
.Max3DTextureLevels
= 9;
249 ctx
->Const
.MaxCubeTextureLevels
= 12;
250 ctx
->Const
.MaxTextureRectSize
= 2048;
252 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
256 ctx
->Const
.MinPointSize
= 1.0;
257 ctx
->Const
.MinPointSizeAA
= 1.0;
258 ctx
->Const
.MaxPointSize
= 1.0;
259 ctx
->Const
.MaxPointSizeAA
= 1.0;
261 ctx
->Const
.MinLineWidth
= 1.0;
262 ctx
->Const
.MinLineWidthAA
= 1.0;
263 ctx
->Const
.MaxLineWidth
= 10.0;
264 ctx
->Const
.MaxLineWidthAA
= 10.0;
265 ctx
->Const
.LineWidthGranularity
= 0.0625;
267 /* Set maxlocksize (and hence vb size) small enough to avoid
268 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
269 * fit in a single dma buffer for indexed rendering of quad strips,
272 ctx
->Const
.MaxArrayLockSize
=
273 MIN2( ctx
->Const
.MaxArrayLockSize
,
274 RADEON_BUFFER_SIZE
/ RADEON_MAX_TCL_VERTSIZE
);
278 ctx
->Const
.MaxDrawBuffers
= 1;
279 ctx
->Const
.MaxColorAttachments
= 1;
280 ctx
->Const
.MaxRenderbufferSize
= 2048;
282 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
284 /* Initialize the software rasterizer and helper modules.
286 _swrast_CreateContext( ctx
);
287 _vbo_CreateContext( ctx
);
288 _tnl_CreateContext( ctx
);
289 _swsetup_CreateContext( ctx
);
290 _ae_create_context( ctx
);
292 /* Install the customized pipeline:
294 _tnl_destroy_pipeline( ctx
);
295 _tnl_install_pipeline( ctx
, radeon_pipeline
);
297 /* Try and keep materials and vertices separate:
299 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
301 /* Configure swrast and T&L to match hardware characteristics:
303 _swrast_allow_pixel_fog( ctx
, GL_FALSE
);
304 _swrast_allow_vertex_fog( ctx
, GL_TRUE
);
305 _tnl_allow_pixel_fog( ctx
, GL_FALSE
);
306 _tnl_allow_vertex_fog( ctx
, GL_TRUE
);
309 for ( i
= 0 ; i
< RADEON_MAX_TEXTURE_UNITS
; i
++ ) {
310 _math_matrix_ctr( &rmesa
->TexGenMatrix
[i
] );
311 _math_matrix_ctr( &rmesa
->tmpmat
[i
] );
312 _math_matrix_set_identity( &rmesa
->TexGenMatrix
[i
] );
313 _math_matrix_set_identity( &rmesa
->tmpmat
[i
] );
316 ctx
->Extensions
.ARB_texture_border_clamp
= true;
317 ctx
->Extensions
.ARB_texture_env_combine
= true;
318 ctx
->Extensions
.ARB_texture_env_crossbar
= true;
319 ctx
->Extensions
.ARB_texture_env_dot3
= true;
320 ctx
->Extensions
.ARB_texture_mirrored_repeat
= true;
321 ctx
->Extensions
.EXT_blend_subtract
= true;
322 ctx
->Extensions
.EXT_fog_coord
= true;
323 ctx
->Extensions
.EXT_packed_depth_stencil
= true;
324 ctx
->Extensions
.EXT_secondary_color
= true;
325 ctx
->Extensions
.EXT_stencil_wrap
= true;
326 ctx
->Extensions
.EXT_texture_env_dot3
= true;
327 ctx
->Extensions
.EXT_texture_filter_anisotropic
= true;
328 ctx
->Extensions
.EXT_texture_lod_bias
= true;
329 ctx
->Extensions
.EXT_texture_mirror_clamp
= true;
330 ctx
->Extensions
.ATI_texture_env_combine3
= true;
331 ctx
->Extensions
.ATI_texture_mirror_once
= true;
332 ctx
->Extensions
.MESA_ycbcr_texture
= true;
333 ctx
->Extensions
.NV_blend_square
= true;
334 #if FEATURE_OES_EGL_image
335 ctx
->Extensions
.OES_EGL_image
= true;
338 ctx
->Extensions
.EXT_framebuffer_object
=
339 rmesa
->radeon
.radeonScreen
->kernel_mm
;
341 ctx
->Extensions
.ARB_texture_cube_map
=
342 rmesa
->radeon
.radeonScreen
->drmSupportsCubeMapsR100
;
344 if (rmesa
->radeon
.glCtx
->Mesa_DXTn
) {
345 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
346 ctx
->Extensions
.S3_s3tc
= true;
348 else if (driQueryOptionb (&rmesa
->radeon
.optionCache
, "force_s3tc_enable")) {
349 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
352 ctx
->Extensions
.NV_texture_rectangle
= rmesa
->radeon
.radeonScreen
->kernel_mm
353 || rmesa
->radeon
.dri
.drmMinor
>= 9;
355 ctx
->Extensions
.ARB_occlusion_query
= rmesa
->radeon
.radeonScreen
->kernel_mm
;
357 /* XXX these should really go right after _mesa_init_driver_functions() */
358 radeon_fbo_init(&rmesa
->radeon
);
359 radeonInitSpanFuncs( ctx
);
360 radeonInitIoctlFuncs( ctx
);
361 radeonInitStateFuncs( ctx
, rmesa
->radeon
.radeonScreen
->kernel_mm
);
362 radeonInitState( rmesa
);
363 radeonInitSwtcl( ctx
);
365 _mesa_vector4f_alloc( &rmesa
->tcl
.ObjClean
, 0,
366 ctx
->Const
.MaxArrayLockSize
, 32 );
368 fthrottle_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "fthrottle_mode");
369 rmesa
->radeon
.iw
.irq_seq
= -1;
370 rmesa
->radeon
.irqsEmitted
= 0;
371 rmesa
->radeon
.do_irqs
= (rmesa
->radeon
.radeonScreen
->irq
!= 0 &&
372 fthrottle_mode
== DRI_CONF_FTHROTTLE_IRQS
);
374 rmesa
->radeon
.do_usleeps
= (fthrottle_mode
== DRI_CONF_FTHROTTLE_USLEEPS
);
378 RADEON_DEBUG
= driParseDebugString( getenv( "RADEON_DEBUG" ),
382 tcl_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "tcl_mode");
383 if (driQueryOptionb(&rmesa
->radeon
.optionCache
, "no_rast")) {
384 fprintf(stderr
, "disabling 3D acceleration\n");
385 FALLBACK(rmesa
, RADEON_FALLBACK_DISABLE
, 1);
386 } else if (tcl_mode
== DRI_CONF_TCL_SW
||
387 !(rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
388 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
389 rmesa
->radeon
.radeonScreen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
390 fprintf(stderr
, "Disabling HW TCL support\n");
392 TCL_FALLBACK(rmesa
->radeon
.glCtx
, RADEON_TCL_FALLBACK_TCL_DISABLE
, 1);
395 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
396 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */