src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include <stdbool.h>
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/api_exec.h"
  41 #include "main/context.h"
  42 #include "main/simple_list.h"
  43 #include "main/imports.h"
  44 #include "main/extensions.h"
  45 #include "main/mfeatures.h"
  46 #include "main/version.h"
  47 #include "main/vtxfmt.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55
  56 #include "drivers/common/driverfuncs.h"
  57
  58 #include "radeon_common.h"
  59 #include "radeon_context.h"
  60 #include "radeon_ioctl.h"
  61 #include "radeon_state.h"
  62 #include "radeon_span.h"
  63 #include "radeon_tex.h"
  64 #include "radeon_swtcl.h"
  65 #include "radeon_tcl.h"
  66 #include "radeon_queryobj.h"
  67 #include "radeon_blit.h"
  68 #include "radeon_fog.h"
  69
  70 #include "utils.h"
  71 #include "xmlpool.h" /* for symbolic values of enum-type options */
  72
  73 extern const struct tnl_pipeline_stage _radeon_render_stage;
  74 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
  75
  76 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
  77
  78    /* Try and go straight to t&l
  79     */
  80    &_radeon_tcl_stage,
  81
  82    /* Catch any t&l fallbacks
  83     */
  84    &_tnl_vertex_transform_stage,
  85    &_tnl_normal_transform_stage,
  86    &_tnl_lighting_stage,
  87    &_tnl_fog_coordinate_stage,
  88    &_tnl_texgen_stage,
  89    &_tnl_texture_transform_stage,
  90
  91    &_radeon_render_stage,
  92    &_tnl_render_stage,          /* FALLBACK:  */
  93    NULL,
  94 };
  95
  96 static void r100_get_lock(radeonContextPtr radeon)
  97 {
  98    r100ContextPtr rmesa = (r100ContextPtr)radeon;
  99    drm_radeon_sarea_t *sarea = radeon->sarea;
 100
 101    RADEON_STATECHANGE(rmesa, ctx);
 102    if (rmesa->radeon.sarea->tiling_enabled) {
 103       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 104          RADEON_COLOR_TILE_ENABLE;
 105    } else {
 106       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 107          ~RADEON_COLOR_TILE_ENABLE;
 108    }
 109
 110    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 111       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 112    }
 113 }
 114
 115 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 116 {
 117 }
 118
 119 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 120 {
 121    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 122
 123    /* r100 always needs to emit ZBS to avoid TCL lockups */
 124    rmesa->hw.zbs.dirty = 1;
 125    radeon->hw.is_dirty = 1;
 126 }
 127
 128 static void r100_vtbl_free_context(struct gl_context *ctx)
 129 {
 130    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 131    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 132 }
 133
 134 static void r100_emit_query_finish(radeonContextPtr radeon)
 135 {
 136    BATCH_LOCALS(radeon);
 137    struct radeon_query_object *query = radeon->query.current;
 138
 139    BEGIN_BATCH_NO_AUTOSTATE(4);
 140    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 141    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 142    END_BATCH();
 143    query->curr_offset += sizeof(uint32_t);
 144    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 145    query->emitted_begin = GL_FALSE;
 146 }
 147
 148 static void r100_init_vtbl(radeonContextPtr radeon)
 149 {
 150    radeon->vtbl.get_lock = r100_get_lock;
 151    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 152    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 153    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 154    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 155    radeon->vtbl.fallback = radeonFallback;
 156    radeon->vtbl.free_context = r100_vtbl_free_context;
 157    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 158    radeon->vtbl.check_blit = r100_check_blit;
 159    radeon->vtbl.blit = r100_blit;
 160    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 161 }
 162
 163 /* Create the device specific context.
 164  */
 165 GLboolean
 166 r100CreateContext( gl_api api,
 167                    const struct gl_config *glVisual,
 168                    __DRIcontext *driContextPriv,
 169                    unsigned major_version,
 170                    unsigned minor_version,
 171                    uint32_t flags,
 172                    unsigned *error,
 173                    void *sharedContextPrivate)
 174 {
 175    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 176    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
 177    struct dd_function_table functions;
 178    r100ContextPtr rmesa;
 179    struct gl_context *ctx;
 180    int i;
 181    int tcl_mode, fthrottle_mode;
 182
 183    switch (api) {
 184    case API_OPENGL_COMPAT:
 185       if (major_version > 1 || minor_version > 3) {
 186          *error = __DRI_CTX_ERROR_BAD_VERSION;
 187          return GL_FALSE;
 188       }
 189       break;
 190    case API_OPENGLES:
 191       break;
 192    default:
 193       *error = __DRI_CTX_ERROR_BAD_API;
 194       return GL_FALSE;
 195    }
 196
 197    /* Flag filtering is handled in dri2CreateContextAttribs.
 198     */
 199    (void) flags;
 200
 201    assert(glVisual);
 202    assert(driContextPriv);
 203    assert(screen);
 204
 205    /* Allocate the Radeon context */
 206    rmesa = calloc(1, sizeof(*rmesa));
 207    if ( !rmesa ) {
 208       *error = __DRI_CTX_ERROR_NO_MEMORY;
 209       return GL_FALSE;
 210    }
 211
 212    rmesa->radeon.radeonScreen = screen;
 213    r100_init_vtbl(&rmesa->radeon);
 214
 215    /* init exp fog table data */
 216    radeonInitStaticFogData();
 217
 218    /* Parse configuration files.
 219     * Do this here so that initialMaxAnisotropy is set before we create
 220     * the default textures.
 221     */
 222    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 223                         screen->driScreen->myNum, "radeon");
 224    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 225                                                  "def_max_anisotropy");
 226
 227    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 228       if ( sPriv->drm_version.minor < 13 )
 229          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 230                           "disabling.\n", sPriv->drm_version.minor );
 231       else
 232          rmesa->using_hyperz = GL_TRUE;
 233    }
 234
 235    if ( sPriv->drm_version.minor >= 15 )
 236       rmesa->texmicrotile = GL_TRUE;
 237
 238    /* Init default driver functions then plug in our Radeon-specific functions
 239     * (the texture functions are especially important)
 240     */
 241    _mesa_init_driver_functions( &functions );
 242    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 243    radeonInitQueryObjFunctions(&functions);
 244
 245    if (!radeonInitContext(&rmesa->radeon, &functions,
 246                           glVisual, driContextPriv,
 247                           sharedContextPrivate)) {
 248      free(rmesa);
 249      *error = __DRI_CTX_ERROR_NO_MEMORY;
 250      return GL_FALSE;
 251    }
 252
 253    rmesa->radeon.swtcl.RenderIndex = ~0;
 254    rmesa->radeon.hw.all_dirty = GL_TRUE;
 255
 256    ctx = &rmesa->radeon.glCtx;
 257    /* Initialize the software rasterizer and helper modules.
 258     */
 259    _swrast_CreateContext( ctx );
 260    _vbo_CreateContext( ctx );
 261    _tnl_CreateContext( ctx );
 262    _swsetup_CreateContext( ctx );
 263    _ae_create_context( ctx );
 264
 265    /* Set the maximum texture size small enough that we can guarentee that
 266     * all texture units can bind a maximal texture and have all of them in
 267     * texturable memory at once. Depending on the allow_large_textures driconf
 268     * setting allow larger textures.
 269     */
 270
 271    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 272                                                  "texture_units");
 273    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 274    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 275    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 276
 277    ctx->Const.StripTextureBorder = GL_TRUE;
 278
 279    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 280
 281    /* FIXME: When no memory manager is available we should set this
 282     * to some reasonable value based on texture memory pool size */
 283    ctx->Const.MaxTextureLevels = 12;
 284    ctx->Const.Max3DTextureLevels = 9;
 285    ctx->Const.MaxCubeTextureLevels = 12;
 286    ctx->Const.MaxTextureRectSize = 2048;
 287
 288    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 289
 290    /* No wide points.
 291     */
 292    ctx->Const.MinPointSize = 1.0;
 293    ctx->Const.MinPointSizeAA = 1.0;
 294    ctx->Const.MaxPointSize = 1.0;
 295    ctx->Const.MaxPointSizeAA = 1.0;
 296
 297    ctx->Const.MinLineWidth = 1.0;
 298    ctx->Const.MinLineWidthAA = 1.0;
 299    ctx->Const.MaxLineWidth = 10.0;
 300    ctx->Const.MaxLineWidthAA = 10.0;
 301    ctx->Const.LineWidthGranularity = 0.0625;
 302
 303    /* Set maxlocksize (and hence vb size) small enough to avoid
 304     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 305     * fit in a single dma buffer for indexed rendering of quad strips,
 306     * etc.
 307     */
 308    ctx->Const.MaxArrayLockSize =
 309       MIN2( ctx->Const.MaxArrayLockSize,
 310             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 311
 312    rmesa->boxes = 0;
 313
 314    ctx->Const.MaxDrawBuffers = 1;
 315    ctx->Const.MaxColorAttachments = 1;
 316    ctx->Const.MaxRenderbufferSize = 2048;
 317
 318    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 319
 320    /* Install the customized pipeline:
 321     */
 322    _tnl_destroy_pipeline( ctx );
 323    _tnl_install_pipeline( ctx, radeon_pipeline );
 324
 325    /* Try and keep materials and vertices separate:
 326     */
 327 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 328
 329    /* Configure swrast and T&L to match hardware characteristics:
 330     */
 331    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 332    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 333    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 334    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 335
 336
 337    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 338       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 339       _math_matrix_ctr( &rmesa->tmpmat[i] );
 340       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 341       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 342    }
 343
 344    ctx->Extensions.ARB_texture_border_clamp = true;
 345    ctx->Extensions.ARB_texture_env_combine = true;
 346    ctx->Extensions.ARB_texture_env_crossbar = true;
 347    ctx->Extensions.ARB_texture_env_dot3 = true;
 348    ctx->Extensions.EXT_fog_coord = true;
 349    ctx->Extensions.EXT_packed_depth_stencil = true;
 350    ctx->Extensions.EXT_secondary_color = true;
 351    ctx->Extensions.EXT_texture_env_dot3 = true;
 352    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 353    ctx->Extensions.EXT_texture_mirror_clamp = true;
 354    ctx->Extensions.ATI_texture_env_combine3 = true;
 355    ctx->Extensions.ATI_texture_mirror_once = true;
 356    ctx->Extensions.MESA_ycbcr_texture = true;
 357    ctx->Extensions.NV_blend_square = true;
 358    ctx->Extensions.OES_EGL_image = true;
 359    ctx->Extensions.EXT_framebuffer_object = true;
 360    ctx->Extensions.ARB_texture_cube_map = true;
 361
 362    if (rmesa->radeon.glCtx.Mesa_DXTn) {
 363       ctx->Extensions.EXT_texture_compression_s3tc = true;
 364       ctx->Extensions.S3_s3tc = true;
 365    }
 366    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 367       ctx->Extensions.EXT_texture_compression_s3tc = true;
 368    }
 369
 370    ctx->Extensions.NV_texture_rectangle = true;
 371    ctx->Extensions.ARB_occlusion_query = true;
 372
 373    /* XXX these should really go right after _mesa_init_driver_functions() */
 374    radeon_fbo_init(&rmesa->radeon);
 375    radeonInitSpanFuncs( ctx );
 376    radeonInitIoctlFuncs( ctx );
 377    radeonInitStateFuncs( ctx );
 378    radeonInitState( rmesa );
 379    radeonInitSwtcl( ctx );
 380
 381    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 382                          ctx->Const.MaxArrayLockSize, 32 );
 383
 384    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 385    rmesa->radeon.iw.irq_seq = -1;
 386    rmesa->radeon.irqsEmitted = 0;
 387    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 388                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 389
 390    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 391
 392
 393 #if DO_DEBUG
 394    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 395                                        debug_control );
 396 #endif
 397
 398    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 399    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 400       fprintf(stderr, "disabling 3D acceleration\n");
 401       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 402    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 403               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 404       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 405          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 406          fprintf(stderr, "Disabling HW TCL support\n");
 407       }
 408       TCL_FALLBACK(&rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 409    }
 410
 411    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 412 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 413    }
 414
 415    _mesa_compute_version(ctx);
 416
 417    /* Exec table initialization requires the version to be computed */
 418    _mesa_initialize_dispatch_tables(ctx);
 419    _mesa_initialize_vbo_vtxfmt(ctx);
 420
 421    *error = __DRI_CTX_ERROR_SUCCESS;
 422    return GL_TRUE;
 423 }