1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
38 #ifndef __RADEON_CONTEXT_H__
39 #define __RADEON_CONTEXT_H__
41 #ifdef GLX_DIRECT_RENDERING
45 #include "radeon_drm.h"
52 struct radeon_context
;
53 typedef struct radeon_context radeonContextRec
;
54 typedef struct radeon_context
*radeonContextPtr
;
56 #include "radeon_lock.h"
57 #include "radeon_screen.h"
60 #include "math/m_vector.h"
62 /* Flags for software fallback cases */
63 /* See correponding strings in radeon_swtcl.c */
64 #define RADEON_FALLBACK_TEXTURE 0x0001
65 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
66 #define RADEON_FALLBACK_STENCIL 0x0004
67 #define RADEON_FALLBACK_RENDER_MODE 0x0008
68 #define RADEON_FALLBACK_BLEND_EQ 0x0010
69 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
70 #define RADEON_FALLBACK_DISABLE 0x0040
71 #define RADEON_FALLBACK_BORDER_MODE 0x0080
73 /* The blit width for texture uploads
75 #define BLIT_WIDTH_BYTES 1024
77 /* Use the templated vertex format:
80 #define TAG(x) radeon##x
81 #include "tnl_dd/t_dd_vertex.h"
84 typedef void (*radeon_tri_func
)( radeonContextPtr
,
89 typedef void (*radeon_line_func
)( radeonContextPtr
,
93 typedef void (*radeon_point_func
)( radeonContextPtr
,
97 struct radeon_colorbuffer_state
{
99 GLint drawOffset
, drawPitch
;
104 struct radeon_depthbuffer_state
{
109 struct radeon_pixel_state
{
110 GLint readOffset
, readPitch
;
113 struct radeon_scissor_state
{
114 drm_clip_rect_t rect
;
117 GLuint numClipRects
; /* Cliprects active */
118 GLuint numAllocedClipRects
; /* Cliprects available */
119 drm_clip_rect_t
*pClipRects
;
122 struct radeon_stencilbuffer_state
{
124 GLuint clear
; /* rb3d_stencilrefmask value */
127 struct radeon_stipple_state
{
137 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
139 /* Texture object in locally shared texture space.
141 struct radeon_tex_obj
{
142 driTextureObject base
;
144 GLuint bufAddr
; /* Offset to start of locally
145 shared texture block */
147 GLuint dirty_state
; /* Flags (1 per texunit) for
148 whether or not this texobj
149 has dirty hardware state
150 (pp_*) that needs to be
154 drm_radeon_tex_image_t image
[6][RADEON_MAX_TEXTURE_LEVELS
];
155 /* Six, for the cube faces */
157 GLuint pp_txfilter
; /* hardware register values */
159 GLuint pp_txoffset
; /* Image location in texmem.
160 All cube faces follow. */
161 GLuint pp_txsize
; /* npot only */
162 GLuint pp_txpitch
; /* npot only */
163 GLuint pp_border_color
;
164 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
166 GLboolean border_fallback
;
170 struct radeon_texture_env_state
{
171 radeonTexObjPtr texobj
;
176 struct radeon_texture_state
{
177 struct radeon_texture_env_state unit
[RADEON_MAX_TEXTURE_UNITS
];
181 struct radeon_state_atom
{
182 struct radeon_state_atom
*next
, *prev
;
183 const char *name
; /* for debug */
184 int cmd_size
; /* size in bytes */
186 int *cmd
; /* one or more cmd's */
187 int *lastcmd
; /* one or more cmd's */
188 GLboolean dirty
; /* dirty-mark in emit_state_list */
189 GLboolean (*check
)( GLcontext
* ); /* is this state active? */
194 /* Trying to keep these relatively short as the variables are becoming
195 * extravagently long. Drop the driver name prefix off the front of
196 * everything - I think we know which driver we're in by now, and keep the
197 * prefix to 3 letters unless absolutely impossible.
201 #define CTX_PP_MISC 1
202 #define CTX_PP_FOG_COLOR 2
203 #define CTX_RE_SOLID_COLOR 3
204 #define CTX_RB3D_BLENDCNTL 4
205 #define CTX_RB3D_DEPTHOFFSET 5
206 #define CTX_RB3D_DEPTHPITCH 6
207 #define CTX_RB3D_ZSTENCILCNTL 7
209 #define CTX_PP_CNTL 9
210 #define CTX_RB3D_CNTL 10
211 #define CTX_RB3D_COLOROFFSET 11
213 #define CTX_RB3D_COLORPITCH 13
214 #define CTX_STATE_SIZE 14
217 #define SET_SE_CNTL 1
218 #define SET_SE_COORDFMT 2
220 #define SET_SE_CNTL_STATUS 4
221 #define SET_STATE_SIZE 5
224 #define LIN_RE_LINE_PATTERN 1
225 #define LIN_RE_LINE_STATE 2
227 #define LIN_SE_LINE_WIDTH 4
228 #define LIN_STATE_SIZE 5
231 #define MSK_RB3D_STENCILREFMASK 1
232 #define MSK_RB3D_ROPCNTL 2
233 #define MSK_RB3D_PLANEMASK 3
234 #define MSK_STATE_SIZE 4
237 #define VPT_SE_VPORT_XSCALE 1
238 #define VPT_SE_VPORT_XOFFSET 2
239 #define VPT_SE_VPORT_YSCALE 3
240 #define VPT_SE_VPORT_YOFFSET 4
241 #define VPT_SE_VPORT_ZSCALE 5
242 #define VPT_SE_VPORT_ZOFFSET 6
243 #define VPT_STATE_SIZE 7
246 #define MSC_RE_MISC 1
247 #define MSC_STATE_SIZE 2
250 #define TEX_PP_TXFILTER 1
251 #define TEX_PP_TXFORMAT 2
252 #define TEX_PP_TXOFFSET 3
253 #define TEX_PP_TXCBLEND 4
254 #define TEX_PP_TXABLEND 5
255 #define TEX_PP_TFACTOR 6
257 #define TEX_PP_BORDER_COLOR 8
258 #define TEX_STATE_SIZE 9
260 #define TXR_CMD_0 0 /* rectangle textures */
261 #define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
262 #define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
263 #define TXR_STATE_SIZE 3
266 #define ZBS_SE_ZBIAS_FACTOR 1
267 #define ZBS_SE_ZBIAS_CONSTANT 2
268 #define ZBS_STATE_SIZE 3
271 #define TCL_OUTPUT_VTXFMT 1
272 #define TCL_OUTPUT_VTXSEL 2
273 #define TCL_MATRIX_SELECT_0 3
274 #define TCL_MATRIX_SELECT_1 4
275 #define TCL_UCP_VERT_BLEND_CTL 5
276 #define TCL_TEXTURE_PROC_CTL 6
277 #define TCL_LIGHT_MODEL_CTL 7
278 #define TCL_PER_LIGHT_CTL_0 8
279 #define TCL_PER_LIGHT_CTL_1 9
280 #define TCL_PER_LIGHT_CTL_2 10
281 #define TCL_PER_LIGHT_CTL_3 11
282 #define TCL_STATE_SIZE 12
285 #define MTL_EMMISSIVE_RED 1
286 #define MTL_EMMISSIVE_GREEN 2
287 #define MTL_EMMISSIVE_BLUE 3
288 #define MTL_EMMISSIVE_ALPHA 4
289 #define MTL_AMBIENT_RED 5
290 #define MTL_AMBIENT_GREEN 6
291 #define MTL_AMBIENT_BLUE 7
292 #define MTL_AMBIENT_ALPHA 8
293 #define MTL_DIFFUSE_RED 9
294 #define MTL_DIFFUSE_GREEN 10
295 #define MTL_DIFFUSE_BLUE 11
296 #define MTL_DIFFUSE_ALPHA 12
297 #define MTL_SPECULAR_RED 13
298 #define MTL_SPECULAR_GREEN 14
299 #define MTL_SPECULAR_BLUE 15
300 #define MTL_SPECULAR_ALPHA 16
301 #define MTL_SHININESS 17
302 #define MTL_STATE_SIZE 18
305 #define VTX_SE_COORD_FMT 1
306 #define VTX_STATE_SIZE 2
310 #define MAT_STATE_SIZE 17
313 #define GRD_VERT_GUARD_CLIP_ADJ 1
314 #define GRD_VERT_GUARD_DISCARD_ADJ 2
315 #define GRD_HORZ_GUARD_CLIP_ADJ 3
316 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
317 #define GRD_STATE_SIZE 5
319 /* position changes frequently when lighting in modelpos - separate
320 * out to new state item?
323 #define LIT_AMBIENT_RED 1
324 #define LIT_AMBIENT_GREEN 2
325 #define LIT_AMBIENT_BLUE 3
326 #define LIT_AMBIENT_ALPHA 4
327 #define LIT_DIFFUSE_RED 5
328 #define LIT_DIFFUSE_GREEN 6
329 #define LIT_DIFFUSE_BLUE 7
330 #define LIT_DIFFUSE_ALPHA 8
331 #define LIT_SPECULAR_RED 9
332 #define LIT_SPECULAR_GREEN 10
333 #define LIT_SPECULAR_BLUE 11
334 #define LIT_SPECULAR_ALPHA 12
335 #define LIT_POSITION_X 13
336 #define LIT_POSITION_Y 14
337 #define LIT_POSITION_Z 15
338 #define LIT_POSITION_W 16
339 #define LIT_DIRECTION_X 17
340 #define LIT_DIRECTION_Y 18
341 #define LIT_DIRECTION_Z 19
342 #define LIT_DIRECTION_W 20
343 #define LIT_ATTEN_QUADRATIC 21
344 #define LIT_ATTEN_LINEAR 22
345 #define LIT_ATTEN_CONST 23
346 #define LIT_ATTEN_XXX 24
348 #define LIT_SPOT_DCD 26
349 #define LIT_SPOT_EXPONENT 27
350 #define LIT_SPOT_CUTOFF 28
351 #define LIT_SPECULAR_THRESH 29
352 #define LIT_RANGE_CUTOFF 30 /* ? */
353 #define LIT_ATTEN_CONST_INV 31
354 #define LIT_STATE_SIZE 32
363 #define FOG_STATE_SIZE 5
372 #define UCP_STATE_SIZE 5
374 /* GLT - Global ambient
381 #define GLT_STATE_SIZE 5
389 #define EYE_RESCALE_FACTOR 4
390 #define EYE_STATE_SIZE 5
393 #define SHN_SHININESS 1
394 #define SHN_STATE_SIZE 2
400 struct radeon_hw_state
{
401 /* All state should be on one of these lists:
403 struct radeon_state_atom dirty
; /* dirty list head placeholder */
404 struct radeon_state_atom clean
; /* clean list head placeholder */
406 /* Hardware state, stored as cmdbuf commands:
407 * -- Need to doublebuffer for
408 * - reviving state after loss of context
409 * - eliding noop statechange loops? (except line stipple count)
411 struct radeon_state_atom ctx
;
412 struct radeon_state_atom set
;
413 struct radeon_state_atom lin
;
414 struct radeon_state_atom msk
;
415 struct radeon_state_atom vpt
;
416 struct radeon_state_atom tcl
;
417 struct radeon_state_atom msc
;
418 struct radeon_state_atom tex
[2];
419 struct radeon_state_atom zbs
;
420 struct radeon_state_atom mtl
;
421 struct radeon_state_atom mat
[5];
422 struct radeon_state_atom lit
[8]; /* includes vec, scl commands */
423 struct radeon_state_atom ucp
[6];
424 struct radeon_state_atom eye
; /* eye pos */
425 struct radeon_state_atom grd
; /* guard band clipping */
426 struct radeon_state_atom fog
;
427 struct radeon_state_atom glt
;
428 struct radeon_state_atom txr
[2]; /* for NPOT */
430 int max_state_size
; /* Number of bytes necessary for a full state emit. */
433 struct radeon_state
{
434 /* Derived state for internal purposes:
436 struct radeon_colorbuffer_state color
;
437 struct radeon_depthbuffer_state depth
;
438 struct radeon_pixel_state pixel
;
439 struct radeon_scissor_state scissor
;
440 struct radeon_stencilbuffer_state stencil
;
441 struct radeon_stipple_state stipple
;
442 struct radeon_texture_state texture
;
446 /* Need refcounting on dma buffers:
448 struct radeon_dma_buffer
{
449 int refcount
; /* the number of retained regions in buf */
453 #define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
454 (rvb)->address - rmesa->dma.buf0_address + \
457 /* A retained region, eg vertices for indexed vertices.
459 struct radeon_dma_region
{
460 struct radeon_dma_buffer
*buf
;
461 char *address
; /* == buf->address */
462 int start
, end
, ptr
; /* offsets from start of buf */
470 /* Active dma region. Allocations for vertices and retained
471 * regions come from here. Also used for emitting random vertices,
472 * these may be flushed by calling flush_current();
474 struct radeon_dma_region current
;
476 void (*flush
)( radeonContextPtr
);
478 char *buf0_address
; /* start of buf[0], for index calcs */
479 GLuint nr_released_bufs
; /* flush after so many buffers released */
482 struct radeon_dri_mirror
{
483 __DRIcontextPrivate
*context
; /* DRI context */
484 __DRIscreenPrivate
*screen
; /* DRI screen */
485 __DRIdrawablePrivate
*drawable
; /* DRI drawable bound to this ctx */
487 drm_context_t hwContext
;
488 drm_hw_lock_t
*hwLock
;
494 #define RADEON_CMD_BUF_SZ (8*1024)
496 struct radeon_store
{
499 char cmd_buf
[RADEON_CMD_BUF_SZ
];
507 struct radeon_tcl_info
{
508 GLuint vertex_format
;
512 /* Temporary for cases where incoming vertex data is incompatible
517 struct radeon_dma_region
*aos_components
[8];
518 GLuint nr_aos_components
;
522 struct radeon_dma_region indexed_verts
;
523 struct radeon_dma_region obj
;
524 struct radeon_dma_region rgba
;
525 struct radeon_dma_region spec
;
526 struct radeon_dma_region fog
;
527 struct radeon_dma_region tex
[RADEON_MAX_TEXTURE_UNITS
];
528 struct radeon_dma_region norm
;
534 struct radeon_swtcl_info
{
536 GLuint SetupNewInputs
;
539 GLuint vertex_stride_shift
;
540 GLuint vertex_format
;
543 /* Fallback rasterization functions
545 radeon_point_func draw_point
;
546 radeon_line_func draw_line
;
547 radeon_tri_func draw_tri
;
550 GLenum render_primitive
;
553 struct radeon_dma_region indexed_verts
;
557 struct radeon_ioctl
{
558 GLuint vertex_offset
;
564 #define RADEON_MAX_PRIMS 64
567 /* Want to keep a cache of these around. Each is parameterized by
568 * only a single value which has only a small range. Only expect a
569 * few, so just rescan the list each time?
572 struct dynfn
*next
, *prev
;
578 struct dynfn Vertex2f
;
579 struct dynfn Vertex2fv
;
580 struct dynfn Vertex3f
;
581 struct dynfn Vertex3fv
;
582 struct dynfn Color4ub
;
583 struct dynfn Color4ubv
;
584 struct dynfn Color3ub
;
585 struct dynfn Color3ubv
;
586 struct dynfn Color4f
;
587 struct dynfn Color4fv
;
588 struct dynfn Color3f
;
589 struct dynfn Color3fv
;
590 struct dynfn SecondaryColor3ubEXT
;
591 struct dynfn SecondaryColor3ubvEXT
;
592 struct dynfn SecondaryColor3fEXT
;
593 struct dynfn SecondaryColor3fvEXT
;
594 struct dynfn Normal3f
;
595 struct dynfn Normal3fv
;
596 struct dynfn TexCoord2f
;
597 struct dynfn TexCoord2fv
;
598 struct dynfn TexCoord1f
;
599 struct dynfn TexCoord1fv
;
600 struct dynfn MultiTexCoord2fARB
;
601 struct dynfn MultiTexCoord2fvARB
;
602 struct dynfn MultiTexCoord1fARB
;
603 struct dynfn MultiTexCoord1fvARB
;
606 struct dfn_generators
{
607 struct dynfn
*(*Vertex2f
)( GLcontext
*, int );
608 struct dynfn
*(*Vertex2fv
)( GLcontext
*, int );
609 struct dynfn
*(*Vertex3f
)( GLcontext
*, int );
610 struct dynfn
*(*Vertex3fv
)( GLcontext
*, int );
611 struct dynfn
*(*Color4ub
)( GLcontext
*, int );
612 struct dynfn
*(*Color4ubv
)( GLcontext
*, int );
613 struct dynfn
*(*Color3ub
)( GLcontext
*, int );
614 struct dynfn
*(*Color3ubv
)( GLcontext
*, int );
615 struct dynfn
*(*Color4f
)( GLcontext
*, int );
616 struct dynfn
*(*Color4fv
)( GLcontext
*, int );
617 struct dynfn
*(*Color3f
)( GLcontext
*, int );
618 struct dynfn
*(*Color3fv
)( GLcontext
*, int );
619 struct dynfn
*(*SecondaryColor3ubEXT
)( GLcontext
*, int );
620 struct dynfn
*(*SecondaryColor3ubvEXT
)( GLcontext
*, int );
621 struct dynfn
*(*SecondaryColor3fEXT
)( GLcontext
*, int );
622 struct dynfn
*(*SecondaryColor3fvEXT
)( GLcontext
*, int );
623 struct dynfn
*(*Normal3f
)( GLcontext
*, int );
624 struct dynfn
*(*Normal3fv
)( GLcontext
*, int );
625 struct dynfn
*(*TexCoord2f
)( GLcontext
*, int );
626 struct dynfn
*(*TexCoord2fv
)( GLcontext
*, int );
627 struct dynfn
*(*TexCoord1f
)( GLcontext
*, int );
628 struct dynfn
*(*TexCoord1fv
)( GLcontext
*, int );
629 struct dynfn
*(*MultiTexCoord2fARB
)( GLcontext
*, int );
630 struct dynfn
*(*MultiTexCoord2fvARB
)( GLcontext
*, int );
631 struct dynfn
*(*MultiTexCoord1fARB
)( GLcontext
*, int );
632 struct dynfn
*(*MultiTexCoord1fvARB
)( GLcontext
*, int );
643 struct radeon_vbinfo
{
644 GLint counter
, initial_counter
;
646 void (*notify
)( void );
649 /* A maximum total of 15 elements per vertex: 3 floats for position, 3
650 * floats for normal, 4 floats for color, 4 bytes for secondary color,
651 * 2 floats for each texture unit (4 floats total).
653 * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are
654 * supported, this value will grow.
656 * The position data is never actually stored here, so 3 elements could be
657 * trimmed out of the buffer.
659 union { float f
; int i
; radeon_color_t color
; } vertex
[15];
662 GLfloat
*floatcolorptr
;
663 radeon_color_t
*colorptr
;
664 GLfloat
*floatspecptr
;
665 radeon_color_t
*specptr
;
666 GLfloat
*texcoordptr
[2];
668 GLenum
*prim
; /* &ctx->Driver.CurrentExecPrimitive */
670 GLboolean enabled
; /* *_NO_VTXFMT / *_NO_TCL env vars */
675 GLuint vertex_format
;
677 GLuint installed_vertex_format
;
678 GLuint installed_color_3f_sz
;
680 struct radeon_prim primlist
[RADEON_MAX_PRIMS
];
683 struct dfn_lists dfn_cache
;
684 struct dfn_generators codegen
;
685 GLvertexformat vtxfmt
;
691 struct radeon_context
{
692 GLcontext
*glCtx
; /* Mesa context */
694 /* Driver and hardware state management
696 struct radeon_hw_state hw
;
697 struct radeon_state state
;
699 /* Texture object bookkeeping
702 driTexHeap
* texture_heaps
[ RADEON_NR_TEX_HEAPS
];
703 driTextureObject swapped
;
705 float initialMaxAnisotropy
;
707 /* Rasterization and vertex state:
715 struct radeon_ioctl ioctl
;
716 struct radeon_dma dma
;
717 struct radeon_store store
;
728 drm_radeon_irq_wait_t iw
;
730 /* Drawable, cliprect and scissor information
732 GLuint numClipRects
; /* Cliprects for the draw buffer */
733 drm_clip_rect_t
*pClipRects
;
734 unsigned int lastStamp
;
735 GLboolean lost_context
;
736 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
737 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
741 GLmatrix TexGenMatrix
[RADEON_MAX_TEXTURE_UNITS
];
742 GLboolean recheck_texgen
[RADEON_MAX_TEXTURE_UNITS
];
743 GLboolean TexGenNeedNormals
[RADEON_MAX_TEXTURE_UNITS
];
744 GLuint TexMatEnabled
;
745 GLuint TexGenEnabled
;
747 GLuint last_ReallyEnabled
;
755 int64_t swap_missed_ust
;
758 GLuint swap_missed_count
;
760 PFNGLXGETUSTPROC get_ust
;
764 struct radeon_tcl_info tcl
;
768 struct radeon_swtcl_info swtcl
;
772 struct radeon_vbinfo vb
;
774 /* Mirrors of some DRI state
776 struct radeon_dri_mirror dri
;
778 /* Configuration cache
780 driOptionCache optionCache
;
783 /* Performance counters
785 GLuint boxes
; /* Draw performance boxes */
786 GLuint hardwareWentIdle
;
789 GLuint c_textureSwaps
;
790 GLuint c_textureBytes
;
791 GLuint c_vertexBuffers
;
794 #define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
797 static __inline GLuint
radeonPackColor( GLuint cpp
,
798 GLubyte r
, GLubyte g
,
799 GLubyte b
, GLubyte a
)
803 return PACK_COLOR_565( r
, g
, b
);
805 return PACK_COLOR_8888( a
, r
, g
, b
);
811 #define RADEON_OLD_PACKETS 1
814 extern void radeonDestroyContext( __DRIcontextPrivate
*driContextPriv
);
815 extern GLboolean
radeonCreateContext(const __GLcontextModes
*glVisual
,
816 __DRIcontextPrivate
*driContextPriv
,
817 void *sharedContextPrivate
);
818 extern void radeonSwapBuffers( __DRIdrawablePrivate
*dPriv
);
819 extern GLboolean
radeonMakeCurrent( __DRIcontextPrivate
*driContextPriv
,
820 __DRIdrawablePrivate
*driDrawPriv
,
821 __DRIdrawablePrivate
*driReadPriv
);
822 extern GLboolean
radeonUnbindContext( __DRIcontextPrivate
*driContextPriv
);
824 /* ================================================================
830 extern int RADEON_DEBUG
;
832 #define RADEON_DEBUG 0
835 #define DEBUG_TEXTURE 0x001
836 #define DEBUG_STATE 0x002
837 #define DEBUG_IOCTL 0x004
838 #define DEBUG_PRIMS 0x008
839 #define DEBUG_VERTS 0x010
840 #define DEBUG_FALLBACKS 0x020
841 #define DEBUG_VFMT 0x040
842 #define DEBUG_CODEGEN 0x080
843 #define DEBUG_VERBOSE 0x100
844 #define DEBUG_DRI 0x200
845 #define DEBUG_DMA 0x400
846 #define DEBUG_SANITY 0x800
849 #endif /* __RADEON_CONTEXT_H__ */