1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
38 #ifndef __RADEON_CONTEXT_H__
39 #define __RADEON_CONTEXT_H__
41 #include "tnl/t_vertex.h"
44 #include "radeon_drm.h"
51 struct radeon_context
;
52 typedef struct radeon_context radeonContextRec
;
53 typedef struct radeon_context
*radeonContextPtr
;
55 #include "radeon_lock.h"
56 #include "radeon_screen.h"
59 #include "math/m_vector.h"
61 /* Flags for software fallback cases */
62 /* See correponding strings in radeon_swtcl.c */
63 #define RADEON_FALLBACK_TEXTURE 0x0001
64 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
65 #define RADEON_FALLBACK_STENCIL 0x0004
66 #define RADEON_FALLBACK_RENDER_MODE 0x0008
67 #define RADEON_FALLBACK_BLEND_EQ 0x0010
68 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
69 #define RADEON_FALLBACK_DISABLE 0x0040
70 #define RADEON_FALLBACK_BORDER_MODE 0x0080
72 /* The blit width for texture uploads
74 #define BLIT_WIDTH_BYTES 1024
76 /* Use the templated vertex format:
79 #define TAG(x) radeon##x
80 #include "tnl_dd/t_dd_vertex.h"
83 typedef void (*radeon_tri_func
)( radeonContextPtr
,
88 typedef void (*radeon_line_func
)( radeonContextPtr
,
92 typedef void (*radeon_point_func
)( radeonContextPtr
,
96 struct radeon_colorbuffer_state
{
98 GLint drawOffset
, drawPitch
;
103 struct radeon_depthbuffer_state
{
108 struct radeon_pixel_state
{
109 GLint readOffset
, readPitch
;
112 struct radeon_scissor_state
{
113 drm_clip_rect_t rect
;
116 GLuint numClipRects
; /* Cliprects active */
117 GLuint numAllocedClipRects
; /* Cliprects available */
118 drm_clip_rect_t
*pClipRects
;
121 struct radeon_stencilbuffer_state
{
123 GLuint clear
; /* rb3d_stencilrefmask value */
126 struct radeon_stipple_state
{
136 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
138 /* Texture object in locally shared texture space.
140 struct radeon_tex_obj
{
141 driTextureObject base
;
143 GLuint bufAddr
; /* Offset to start of locally
144 shared texture block */
146 GLuint dirty_state
; /* Flags (1 per texunit) for
147 whether or not this texobj
148 has dirty hardware state
149 (pp_*) that needs to be
153 drm_radeon_tex_image_t image
[6][RADEON_MAX_TEXTURE_LEVELS
];
154 /* Six, for the cube faces */
156 GLuint pp_txfilter
; /* hardware register values */
158 GLuint pp_txoffset
; /* Image location in texmem.
159 All cube faces follow. */
160 GLuint pp_txsize
; /* npot only */
161 GLuint pp_txpitch
; /* npot only */
162 GLuint pp_border_color
;
163 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
165 GLboolean border_fallback
;
167 GLuint tile_bits
; /* hw texture tile bits used on this texture */
171 struct radeon_texture_env_state
{
172 radeonTexObjPtr texobj
;
177 struct radeon_texture_state
{
178 struct radeon_texture_env_state unit
[RADEON_MAX_TEXTURE_UNITS
];
182 struct radeon_state_atom
{
183 struct radeon_state_atom
*next
, *prev
;
184 const char *name
; /* for debug */
185 int cmd_size
; /* size in bytes */
187 int *cmd
; /* one or more cmd's */
188 int *lastcmd
; /* one or more cmd's */
189 GLboolean dirty
; /* dirty-mark in emit_state_list */
190 GLboolean (*check
)( GLcontext
* ); /* is this state active? */
195 /* Trying to keep these relatively short as the variables are becoming
196 * extravagently long. Drop the driver name prefix off the front of
197 * everything - I think we know which driver we're in by now, and keep the
198 * prefix to 3 letters unless absolutely impossible.
202 #define CTX_PP_MISC 1
203 #define CTX_PP_FOG_COLOR 2
204 #define CTX_RE_SOLID_COLOR 3
205 #define CTX_RB3D_BLENDCNTL 4
206 #define CTX_RB3D_DEPTHOFFSET 5
207 #define CTX_RB3D_DEPTHPITCH 6
208 #define CTX_RB3D_ZSTENCILCNTL 7
210 #define CTX_PP_CNTL 9
211 #define CTX_RB3D_CNTL 10
212 #define CTX_RB3D_COLOROFFSET 11
214 #define CTX_RB3D_COLORPITCH 13
215 #define CTX_STATE_SIZE 14
218 #define SET_SE_CNTL 1
219 #define SET_SE_COORDFMT 2
221 #define SET_SE_CNTL_STATUS 4
222 #define SET_STATE_SIZE 5
225 #define LIN_RE_LINE_PATTERN 1
226 #define LIN_RE_LINE_STATE 2
228 #define LIN_SE_LINE_WIDTH 4
229 #define LIN_STATE_SIZE 5
232 #define MSK_RB3D_STENCILREFMASK 1
233 #define MSK_RB3D_ROPCNTL 2
234 #define MSK_RB3D_PLANEMASK 3
235 #define MSK_STATE_SIZE 4
238 #define VPT_SE_VPORT_XSCALE 1
239 #define VPT_SE_VPORT_XOFFSET 2
240 #define VPT_SE_VPORT_YSCALE 3
241 #define VPT_SE_VPORT_YOFFSET 4
242 #define VPT_SE_VPORT_ZSCALE 5
243 #define VPT_SE_VPORT_ZOFFSET 6
244 #define VPT_STATE_SIZE 7
247 #define MSC_RE_MISC 1
248 #define MSC_STATE_SIZE 2
251 #define TEX_PP_TXFILTER 1
252 #define TEX_PP_TXFORMAT 2
253 #define TEX_PP_TXOFFSET 3
254 #define TEX_PP_TXCBLEND 4
255 #define TEX_PP_TXABLEND 5
256 #define TEX_PP_TFACTOR 6
258 #define TEX_PP_BORDER_COLOR 8
259 #define TEX_STATE_SIZE 9
261 #define TXR_CMD_0 0 /* rectangle textures */
262 #define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
263 #define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
264 #define TXR_STATE_SIZE 3
267 #define ZBS_SE_ZBIAS_FACTOR 1
268 #define ZBS_SE_ZBIAS_CONSTANT 2
269 #define ZBS_STATE_SIZE 3
272 #define TCL_OUTPUT_VTXFMT 1
273 #define TCL_OUTPUT_VTXSEL 2
274 #define TCL_MATRIX_SELECT_0 3
275 #define TCL_MATRIX_SELECT_1 4
276 #define TCL_UCP_VERT_BLEND_CTL 5
277 #define TCL_TEXTURE_PROC_CTL 6
278 #define TCL_LIGHT_MODEL_CTL 7
279 #define TCL_PER_LIGHT_CTL_0 8
280 #define TCL_PER_LIGHT_CTL_1 9
281 #define TCL_PER_LIGHT_CTL_2 10
282 #define TCL_PER_LIGHT_CTL_3 11
283 #define TCL_STATE_SIZE 12
286 #define MTL_EMMISSIVE_RED 1
287 #define MTL_EMMISSIVE_GREEN 2
288 #define MTL_EMMISSIVE_BLUE 3
289 #define MTL_EMMISSIVE_ALPHA 4
290 #define MTL_AMBIENT_RED 5
291 #define MTL_AMBIENT_GREEN 6
292 #define MTL_AMBIENT_BLUE 7
293 #define MTL_AMBIENT_ALPHA 8
294 #define MTL_DIFFUSE_RED 9
295 #define MTL_DIFFUSE_GREEN 10
296 #define MTL_DIFFUSE_BLUE 11
297 #define MTL_DIFFUSE_ALPHA 12
298 #define MTL_SPECULAR_RED 13
299 #define MTL_SPECULAR_GREEN 14
300 #define MTL_SPECULAR_BLUE 15
301 #define MTL_SPECULAR_ALPHA 16
302 #define MTL_SHININESS 17
303 #define MTL_STATE_SIZE 18
306 #define VTX_SE_COORD_FMT 1
307 #define VTX_STATE_SIZE 2
311 #define MAT_STATE_SIZE 17
314 #define GRD_VERT_GUARD_CLIP_ADJ 1
315 #define GRD_VERT_GUARD_DISCARD_ADJ 2
316 #define GRD_HORZ_GUARD_CLIP_ADJ 3
317 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
318 #define GRD_STATE_SIZE 5
320 /* position changes frequently when lighting in modelpos - separate
321 * out to new state item?
324 #define LIT_AMBIENT_RED 1
325 #define LIT_AMBIENT_GREEN 2
326 #define LIT_AMBIENT_BLUE 3
327 #define LIT_AMBIENT_ALPHA 4
328 #define LIT_DIFFUSE_RED 5
329 #define LIT_DIFFUSE_GREEN 6
330 #define LIT_DIFFUSE_BLUE 7
331 #define LIT_DIFFUSE_ALPHA 8
332 #define LIT_SPECULAR_RED 9
333 #define LIT_SPECULAR_GREEN 10
334 #define LIT_SPECULAR_BLUE 11
335 #define LIT_SPECULAR_ALPHA 12
336 #define LIT_POSITION_X 13
337 #define LIT_POSITION_Y 14
338 #define LIT_POSITION_Z 15
339 #define LIT_POSITION_W 16
340 #define LIT_DIRECTION_X 17
341 #define LIT_DIRECTION_Y 18
342 #define LIT_DIRECTION_Z 19
343 #define LIT_DIRECTION_W 20
344 #define LIT_ATTEN_QUADRATIC 21
345 #define LIT_ATTEN_LINEAR 22
346 #define LIT_ATTEN_CONST 23
347 #define LIT_ATTEN_XXX 24
349 #define LIT_SPOT_DCD 26
350 #define LIT_SPOT_EXPONENT 27
351 #define LIT_SPOT_CUTOFF 28
352 #define LIT_SPECULAR_THRESH 29
353 #define LIT_RANGE_CUTOFF 30 /* ? */
354 #define LIT_ATTEN_CONST_INV 31
355 #define LIT_STATE_SIZE 32
364 #define FOG_STATE_SIZE 5
373 #define UCP_STATE_SIZE 5
375 /* GLT - Global ambient
382 #define GLT_STATE_SIZE 5
390 #define EYE_RESCALE_FACTOR 4
391 #define EYE_STATE_SIZE 5
394 #define SHN_SHININESS 1
395 #define SHN_STATE_SIZE 2
401 struct radeon_hw_state
{
402 /* Head of the linked list of state atoms. */
403 struct radeon_state_atom atomlist
;
405 /* Hardware state, stored as cmdbuf commands:
406 * -- Need to doublebuffer for
407 * - eliding noop statechange loops? (except line stipple count)
409 struct radeon_state_atom ctx
;
410 struct radeon_state_atom set
;
411 struct radeon_state_atom lin
;
412 struct radeon_state_atom msk
;
413 struct radeon_state_atom vpt
;
414 struct radeon_state_atom tcl
;
415 struct radeon_state_atom msc
;
416 struct radeon_state_atom tex
[2];
417 struct radeon_state_atom zbs
;
418 struct radeon_state_atom mtl
;
419 struct radeon_state_atom mat
[5];
420 struct radeon_state_atom lit
[8]; /* includes vec, scl commands */
421 struct radeon_state_atom ucp
[6];
422 struct radeon_state_atom eye
; /* eye pos */
423 struct radeon_state_atom grd
; /* guard band clipping */
424 struct radeon_state_atom fog
;
425 struct radeon_state_atom glt
;
426 struct radeon_state_atom txr
[2]; /* for NPOT */
428 int max_state_size
; /* Number of bytes necessary for a full state emit. */
429 GLboolean is_dirty
, all_dirty
;
432 struct radeon_state
{
433 /* Derived state for internal purposes:
435 struct radeon_colorbuffer_state color
;
436 struct radeon_depthbuffer_state depth
;
437 struct radeon_pixel_state pixel
;
438 struct radeon_scissor_state scissor
;
439 struct radeon_stencilbuffer_state stencil
;
440 struct radeon_stipple_state stipple
;
441 struct radeon_texture_state texture
;
445 /* Need refcounting on dma buffers:
447 struct radeon_dma_buffer
{
448 int refcount
; /* the number of retained regions in buf */
452 #define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
453 (rvb)->address - rmesa->dma.buf0_address + \
456 /* A retained region, eg vertices for indexed vertices.
458 struct radeon_dma_region
{
459 struct radeon_dma_buffer
*buf
;
460 char *address
; /* == buf->address */
461 int start
, end
, ptr
; /* offsets from start of buf */
469 /* Active dma region. Allocations for vertices and retained
470 * regions come from here. Also used for emitting random vertices,
471 * these may be flushed by calling flush_current();
473 struct radeon_dma_region current
;
475 void (*flush
)( radeonContextPtr
);
477 char *buf0_address
; /* start of buf[0], for index calcs */
478 GLuint nr_released_bufs
; /* flush after so many buffers released */
481 struct radeon_dri_mirror
{
482 __DRIcontextPrivate
*context
; /* DRI context */
483 __DRIscreenPrivate
*screen
; /* DRI screen */
484 __DRIdrawablePrivate
*drawable
; /* DRI drawable bound to this ctx */
486 drm_context_t hwContext
;
487 drm_hw_lock_t
*hwLock
;
493 #define RADEON_CMD_BUF_SZ (8*1024)
495 struct radeon_store
{
498 char cmd_buf
[RADEON_CMD_BUF_SZ
];
506 struct radeon_tcl_info
{
507 GLuint vertex_format
;
511 /* Temporary for cases where incoming vertex data is incompatible
516 struct radeon_dma_region
*aos_components
[8];
517 GLuint nr_aos_components
;
521 struct radeon_dma_region indexed_verts
;
522 struct radeon_dma_region obj
;
523 struct radeon_dma_region rgba
;
524 struct radeon_dma_region spec
;
525 struct radeon_dma_region fog
;
526 struct radeon_dma_region tex
[RADEON_MAX_TEXTURE_UNITS
];
527 struct radeon_dma_region norm
;
533 struct radeon_swtcl_info
{
536 GLuint vertex_format
;
538 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
539 GLuint vertex_attr_count
;
543 /* Fallback rasterization functions
545 radeon_point_func draw_point
;
546 radeon_line_func draw_line
;
547 radeon_tri_func draw_tri
;
550 GLenum render_primitive
;
554 * Offset of the 4UB color data within a hardware (swtcl) vertex.
559 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
565 struct radeon_dma_region indexed_verts
;
569 struct radeon_ioctl
{
570 GLuint vertex_offset
;
576 #define RADEON_MAX_PRIMS 64
579 /* Want to keep a cache of these around. Each is parameterized by
580 * only a single value which has only a small range. Only expect a
581 * few, so just rescan the list each time?
584 struct dynfn
*next
, *prev
;
590 struct dynfn Vertex2f
;
591 struct dynfn Vertex2fv
;
592 struct dynfn Vertex3f
;
593 struct dynfn Vertex3fv
;
594 struct dynfn Color4ub
;
595 struct dynfn Color4ubv
;
596 struct dynfn Color3ub
;
597 struct dynfn Color3ubv
;
598 struct dynfn Color4f
;
599 struct dynfn Color4fv
;
600 struct dynfn Color3f
;
601 struct dynfn Color3fv
;
602 struct dynfn SecondaryColor3ubEXT
;
603 struct dynfn SecondaryColor3ubvEXT
;
604 struct dynfn SecondaryColor3fEXT
;
605 struct dynfn SecondaryColor3fvEXT
;
606 struct dynfn Normal3f
;
607 struct dynfn Normal3fv
;
608 struct dynfn TexCoord2f
;
609 struct dynfn TexCoord2fv
;
610 struct dynfn TexCoord1f
;
611 struct dynfn TexCoord1fv
;
612 struct dynfn MultiTexCoord2fARB
;
613 struct dynfn MultiTexCoord2fvARB
;
614 struct dynfn MultiTexCoord1fARB
;
615 struct dynfn MultiTexCoord1fvARB
;
618 struct dfn_generators
{
619 struct dynfn
*(*Vertex2f
)( GLcontext
*, int );
620 struct dynfn
*(*Vertex2fv
)( GLcontext
*, int );
621 struct dynfn
*(*Vertex3f
)( GLcontext
*, int );
622 struct dynfn
*(*Vertex3fv
)( GLcontext
*, int );
623 struct dynfn
*(*Color4ub
)( GLcontext
*, int );
624 struct dynfn
*(*Color4ubv
)( GLcontext
*, int );
625 struct dynfn
*(*Color3ub
)( GLcontext
*, int );
626 struct dynfn
*(*Color3ubv
)( GLcontext
*, int );
627 struct dynfn
*(*Color4f
)( GLcontext
*, int );
628 struct dynfn
*(*Color4fv
)( GLcontext
*, int );
629 struct dynfn
*(*Color3f
)( GLcontext
*, int );
630 struct dynfn
*(*Color3fv
)( GLcontext
*, int );
631 struct dynfn
*(*SecondaryColor3ubEXT
)( GLcontext
*, int );
632 struct dynfn
*(*SecondaryColor3ubvEXT
)( GLcontext
*, int );
633 struct dynfn
*(*SecondaryColor3fEXT
)( GLcontext
*, int );
634 struct dynfn
*(*SecondaryColor3fvEXT
)( GLcontext
*, int );
635 struct dynfn
*(*Normal3f
)( GLcontext
*, int );
636 struct dynfn
*(*Normal3fv
)( GLcontext
*, int );
637 struct dynfn
*(*TexCoord2f
)( GLcontext
*, int );
638 struct dynfn
*(*TexCoord2fv
)( GLcontext
*, int );
639 struct dynfn
*(*TexCoord1f
)( GLcontext
*, int );
640 struct dynfn
*(*TexCoord1fv
)( GLcontext
*, int );
641 struct dynfn
*(*MultiTexCoord2fARB
)( GLcontext
*, int );
642 struct dynfn
*(*MultiTexCoord2fvARB
)( GLcontext
*, int );
643 struct dynfn
*(*MultiTexCoord1fARB
)( GLcontext
*, int );
644 struct dynfn
*(*MultiTexCoord1fvARB
)( GLcontext
*, int );
655 struct radeon_vbinfo
{
656 GLint counter
, initial_counter
;
658 void (*notify
)( void );
661 /* A maximum total of 15 elements per vertex: 3 floats for position, 3
662 * floats for normal, 4 floats for color, 4 bytes for secondary color,
663 * 2 floats for each texture unit (4 floats total).
665 * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are
666 * supported, this value will grow.
668 * The position data is never actually stored here, so 3 elements could be
669 * trimmed out of the buffer.
671 union { float f
; int i
; radeon_color_t color
; } vertex
[15];
674 GLfloat
*floatcolorptr
;
675 radeon_color_t
*colorptr
;
676 GLfloat
*floatspecptr
;
677 radeon_color_t
*specptr
;
678 GLfloat
*texcoordptr
[2];
680 GLenum
*prim
; /* &ctx->Driver.CurrentExecPrimitive */
682 GLboolean enabled
; /* *_NO_VTXFMT / *_NO_TCL env vars */
687 GLuint vertex_format
;
689 GLuint installed_vertex_format
;
690 GLuint installed_color_3f_sz
;
692 struct radeon_prim primlist
[RADEON_MAX_PRIMS
];
695 struct dfn_lists dfn_cache
;
696 struct dfn_generators codegen
;
697 GLvertexformat vtxfmt
;
703 struct radeon_context
{
704 GLcontext
*glCtx
; /* Mesa context */
706 /* Driver and hardware state management
708 struct radeon_hw_state hw
;
709 struct radeon_state state
;
711 /* Texture object bookkeeping
714 driTexHeap
* texture_heaps
[ RADEON_NR_TEX_HEAPS
];
715 driTextureObject swapped
;
717 float initialMaxAnisotropy
;
719 /* Rasterization and vertex state:
724 GLuint tnl_index
; /* index of bits for last tnl_install_attrs */
728 struct radeon_ioctl ioctl
;
729 struct radeon_dma dma
;
730 struct radeon_store store
;
731 /* A full state emit as of the first state emit in the main store, in case
732 * the context is lost.
734 struct radeon_store backup_store
;
745 drm_radeon_irq_wait_t iw
;
747 /* Drawable, cliprect and scissor information
749 GLuint numClipRects
; /* Cliprects for the draw buffer */
750 drm_clip_rect_t
*pClipRects
;
751 unsigned int lastStamp
;
752 GLboolean lost_context
;
753 GLboolean save_on_next_emit
;
754 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
755 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
759 GLmatrix TexGenMatrix
[RADEON_MAX_TEXTURE_UNITS
];
760 GLboolean recheck_texgen
[RADEON_MAX_TEXTURE_UNITS
];
761 GLboolean TexGenNeedNormals
[RADEON_MAX_TEXTURE_UNITS
];
762 GLuint TexMatEnabled
;
763 GLuint TexGenEnabled
;
765 GLuint last_ReallyEnabled
;
773 int64_t swap_missed_ust
;
776 GLuint swap_missed_count
;
781 struct radeon_tcl_info tcl
;
785 struct radeon_swtcl_info swtcl
;
789 struct radeon_vbinfo vb
;
791 /* Mirrors of some DRI state
793 struct radeon_dri_mirror dri
;
795 /* Configuration cache
797 driOptionCache optionCache
;
799 GLboolean using_hyperz
;
800 GLboolean texmicrotile
;
802 /* Performance counters
804 GLuint boxes
; /* Draw performance boxes */
805 GLuint hardwareWentIdle
;
808 GLuint c_textureSwaps
;
809 GLuint c_textureBytes
;
810 GLuint c_vertexBuffers
;
813 #define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
816 static __inline GLuint
radeonPackColor( GLuint cpp
,
817 GLubyte r
, GLubyte g
,
818 GLubyte b
, GLubyte a
)
822 return PACK_COLOR_565( r
, g
, b
);
824 return PACK_COLOR_8888( a
, r
, g
, b
);
830 #define RADEON_OLD_PACKETS 1
833 extern void radeonDestroyContext( __DRIcontextPrivate
*driContextPriv
);
834 extern GLboolean
radeonCreateContext(const __GLcontextModes
*glVisual
,
835 __DRIcontextPrivate
*driContextPriv
,
836 void *sharedContextPrivate
);
837 extern void radeonSwapBuffers( __DRIdrawablePrivate
*dPriv
);
838 extern GLboolean
radeonMakeCurrent( __DRIcontextPrivate
*driContextPriv
,
839 __DRIdrawablePrivate
*driDrawPriv
,
840 __DRIdrawablePrivate
*driReadPriv
);
841 extern GLboolean
radeonUnbindContext( __DRIcontextPrivate
*driContextPriv
);
843 /* ================================================================
849 extern int RADEON_DEBUG
;
851 #define RADEON_DEBUG 0
854 #define DEBUG_TEXTURE 0x001
855 #define DEBUG_STATE 0x002
856 #define DEBUG_IOCTL 0x004
857 #define DEBUG_PRIMS 0x008
858 #define DEBUG_VERTS 0x010
859 #define DEBUG_FALLBACKS 0x020
860 #define DEBUG_VFMT 0x040
861 #define DEBUG_CODEGEN 0x080
862 #define DEBUG_VERBOSE 0x100
863 #define DEBUG_DRI 0x200
864 #define DEBUG_DMA 0x400
865 #define DEBUG_SANITY 0x800
866 #define DEBUG_SYNC 0x1000
868 #endif /* __RADEON_CONTEXT_H__ */