1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
35 * Keith Whitwell <keith@tungstengraphics.com>
38 #ifndef __RADEON_CONTEXT_H__
39 #define __RADEON_CONTEXT_H__
41 #include "tnl/t_vertex.h"
44 #include "radeon_drm.h"
51 struct radeon_context
;
52 typedef struct radeon_context radeonContextRec
;
53 typedef struct radeon_context
*radeonContextPtr
;
55 #include "radeon_lock.h"
56 #include "radeon_screen.h"
59 #include "math/m_vector.h"
61 /* Flags for software fallback cases */
62 /* See correponding strings in radeon_swtcl.c */
63 #define RADEON_FALLBACK_TEXTURE 0x0001
64 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
65 #define RADEON_FALLBACK_STENCIL 0x0004
66 #define RADEON_FALLBACK_RENDER_MODE 0x0008
67 #define RADEON_FALLBACK_BLEND_EQ 0x0010
68 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
69 #define RADEON_FALLBACK_DISABLE 0x0040
70 #define RADEON_FALLBACK_BORDER_MODE 0x0080
72 /* The blit width for texture uploads
74 #define BLIT_WIDTH_BYTES 1024
76 /* Use the templated vertex format:
79 #define TAG(x) radeon##x
80 #include "tnl_dd/t_dd_vertex.h"
83 typedef void (*radeon_tri_func
)( radeonContextPtr
,
88 typedef void (*radeon_line_func
)( radeonContextPtr
,
92 typedef void (*radeon_point_func
)( radeonContextPtr
,
96 struct radeon_colorbuffer_state
{
102 struct radeon_depthbuffer_state
{
107 struct radeon_scissor_state
{
108 drm_clip_rect_t rect
;
111 GLuint numClipRects
; /* Cliprects active */
112 GLuint numAllocedClipRects
; /* Cliprects available */
113 drm_clip_rect_t
*pClipRects
;
116 struct radeon_stencilbuffer_state
{
118 GLuint clear
; /* rb3d_stencilrefmask value */
121 struct radeon_stipple_state
{
131 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
133 /* Texture object in locally shared texture space.
135 struct radeon_tex_obj
{
136 driTextureObject base
;
138 GLuint bufAddr
; /* Offset to start of locally
139 shared texture block */
141 GLuint dirty_state
; /* Flags (1 per texunit) for
142 whether or not this texobj
143 has dirty hardware state
144 (pp_*) that needs to be
148 drm_radeon_tex_image_t image
[6][RADEON_MAX_TEXTURE_LEVELS
];
149 /* Six, for the cube faces */
151 GLuint pp_txfilter
; /* hardware register values */
153 GLuint pp_txoffset
; /* Image location in texmem.
154 All cube faces follow. */
155 GLuint pp_txsize
; /* npot only */
156 GLuint pp_txpitch
; /* npot only */
157 GLuint pp_border_color
;
158 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
160 GLboolean border_fallback
;
162 GLuint tile_bits
; /* hw texture tile bits used on this texture */
166 struct radeon_texture_env_state
{
167 radeonTexObjPtr texobj
;
172 struct radeon_texture_state
{
173 struct radeon_texture_env_state unit
[RADEON_MAX_TEXTURE_UNITS
];
177 struct radeon_state_atom
{
178 struct radeon_state_atom
*next
, *prev
;
179 const char *name
; /* for debug */
180 int cmd_size
; /* size in bytes */
182 int *cmd
; /* one or more cmd's */
183 int *lastcmd
; /* one or more cmd's */
184 GLboolean dirty
; /* dirty-mark in emit_state_list */
185 GLboolean (*check
)( GLcontext
* ); /* is this state active? */
190 /* Trying to keep these relatively short as the variables are becoming
191 * extravagently long. Drop the driver name prefix off the front of
192 * everything - I think we know which driver we're in by now, and keep the
193 * prefix to 3 letters unless absolutely impossible.
197 #define CTX_PP_MISC 1
198 #define CTX_PP_FOG_COLOR 2
199 #define CTX_RE_SOLID_COLOR 3
200 #define CTX_RB3D_BLENDCNTL 4
201 #define CTX_RB3D_DEPTHOFFSET 5
202 #define CTX_RB3D_DEPTHPITCH 6
203 #define CTX_RB3D_ZSTENCILCNTL 7
205 #define CTX_PP_CNTL 9
206 #define CTX_RB3D_CNTL 10
207 #define CTX_RB3D_COLOROFFSET 11
209 #define CTX_RB3D_COLORPITCH 13
210 #define CTX_STATE_SIZE 14
213 #define SET_SE_CNTL 1
214 #define SET_SE_COORDFMT 2
216 #define SET_SE_CNTL_STATUS 4
217 #define SET_STATE_SIZE 5
220 #define LIN_RE_LINE_PATTERN 1
221 #define LIN_RE_LINE_STATE 2
223 #define LIN_SE_LINE_WIDTH 4
224 #define LIN_STATE_SIZE 5
227 #define MSK_RB3D_STENCILREFMASK 1
228 #define MSK_RB3D_ROPCNTL 2
229 #define MSK_RB3D_PLANEMASK 3
230 #define MSK_STATE_SIZE 4
233 #define VPT_SE_VPORT_XSCALE 1
234 #define VPT_SE_VPORT_XOFFSET 2
235 #define VPT_SE_VPORT_YSCALE 3
236 #define VPT_SE_VPORT_YOFFSET 4
237 #define VPT_SE_VPORT_ZSCALE 5
238 #define VPT_SE_VPORT_ZOFFSET 6
239 #define VPT_STATE_SIZE 7
242 #define MSC_RE_MISC 1
243 #define MSC_STATE_SIZE 2
246 #define TEX_PP_TXFILTER 1
247 #define TEX_PP_TXFORMAT 2
248 #define TEX_PP_TXOFFSET 3
249 #define TEX_PP_TXCBLEND 4
250 #define TEX_PP_TXABLEND 5
251 #define TEX_PP_TFACTOR 6
253 #define TEX_PP_BORDER_COLOR 8
254 #define TEX_STATE_SIZE 9
256 #define TXR_CMD_0 0 /* rectangle textures */
257 #define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
258 #define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
259 #define TXR_STATE_SIZE 3
262 #define ZBS_SE_ZBIAS_FACTOR 1
263 #define ZBS_SE_ZBIAS_CONSTANT 2
264 #define ZBS_STATE_SIZE 3
267 #define TCL_OUTPUT_VTXFMT 1
268 #define TCL_OUTPUT_VTXSEL 2
269 #define TCL_MATRIX_SELECT_0 3
270 #define TCL_MATRIX_SELECT_1 4
271 #define TCL_UCP_VERT_BLEND_CTL 5
272 #define TCL_TEXTURE_PROC_CTL 6
273 #define TCL_LIGHT_MODEL_CTL 7
274 #define TCL_PER_LIGHT_CTL_0 8
275 #define TCL_PER_LIGHT_CTL_1 9
276 #define TCL_PER_LIGHT_CTL_2 10
277 #define TCL_PER_LIGHT_CTL_3 11
278 #define TCL_STATE_SIZE 12
281 #define MTL_EMMISSIVE_RED 1
282 #define MTL_EMMISSIVE_GREEN 2
283 #define MTL_EMMISSIVE_BLUE 3
284 #define MTL_EMMISSIVE_ALPHA 4
285 #define MTL_AMBIENT_RED 5
286 #define MTL_AMBIENT_GREEN 6
287 #define MTL_AMBIENT_BLUE 7
288 #define MTL_AMBIENT_ALPHA 8
289 #define MTL_DIFFUSE_RED 9
290 #define MTL_DIFFUSE_GREEN 10
291 #define MTL_DIFFUSE_BLUE 11
292 #define MTL_DIFFUSE_ALPHA 12
293 #define MTL_SPECULAR_RED 13
294 #define MTL_SPECULAR_GREEN 14
295 #define MTL_SPECULAR_BLUE 15
296 #define MTL_SPECULAR_ALPHA 16
297 #define MTL_SHININESS 17
298 #define MTL_STATE_SIZE 18
301 #define VTX_SE_COORD_FMT 1
302 #define VTX_STATE_SIZE 2
306 #define MAT_STATE_SIZE 17
309 #define GRD_VERT_GUARD_CLIP_ADJ 1
310 #define GRD_VERT_GUARD_DISCARD_ADJ 2
311 #define GRD_HORZ_GUARD_CLIP_ADJ 3
312 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
313 #define GRD_STATE_SIZE 5
315 /* position changes frequently when lighting in modelpos - separate
316 * out to new state item?
319 #define LIT_AMBIENT_RED 1
320 #define LIT_AMBIENT_GREEN 2
321 #define LIT_AMBIENT_BLUE 3
322 #define LIT_AMBIENT_ALPHA 4
323 #define LIT_DIFFUSE_RED 5
324 #define LIT_DIFFUSE_GREEN 6
325 #define LIT_DIFFUSE_BLUE 7
326 #define LIT_DIFFUSE_ALPHA 8
327 #define LIT_SPECULAR_RED 9
328 #define LIT_SPECULAR_GREEN 10
329 #define LIT_SPECULAR_BLUE 11
330 #define LIT_SPECULAR_ALPHA 12
331 #define LIT_POSITION_X 13
332 #define LIT_POSITION_Y 14
333 #define LIT_POSITION_Z 15
334 #define LIT_POSITION_W 16
335 #define LIT_DIRECTION_X 17
336 #define LIT_DIRECTION_Y 18
337 #define LIT_DIRECTION_Z 19
338 #define LIT_DIRECTION_W 20
339 #define LIT_ATTEN_QUADRATIC 21
340 #define LIT_ATTEN_LINEAR 22
341 #define LIT_ATTEN_CONST 23
342 #define LIT_ATTEN_XXX 24
344 #define LIT_SPOT_DCD 26
345 #define LIT_SPOT_EXPONENT 27
346 #define LIT_SPOT_CUTOFF 28
347 #define LIT_SPECULAR_THRESH 29
348 #define LIT_RANGE_CUTOFF 30 /* ? */
349 #define LIT_ATTEN_CONST_INV 31
350 #define LIT_STATE_SIZE 32
359 #define FOG_STATE_SIZE 5
368 #define UCP_STATE_SIZE 5
370 /* GLT - Global ambient
377 #define GLT_STATE_SIZE 5
385 #define EYE_RESCALE_FACTOR 4
386 #define EYE_STATE_SIZE 5
389 #define SHN_SHININESS 1
390 #define SHN_STATE_SIZE 2
396 struct radeon_hw_state
{
397 /* Head of the linked list of state atoms. */
398 struct radeon_state_atom atomlist
;
400 /* Hardware state, stored as cmdbuf commands:
401 * -- Need to doublebuffer for
402 * - eliding noop statechange loops? (except line stipple count)
404 struct radeon_state_atom ctx
;
405 struct radeon_state_atom set
;
406 struct radeon_state_atom lin
;
407 struct radeon_state_atom msk
;
408 struct radeon_state_atom vpt
;
409 struct radeon_state_atom tcl
;
410 struct radeon_state_atom msc
;
411 struct radeon_state_atom tex
[2];
412 struct radeon_state_atom zbs
;
413 struct radeon_state_atom mtl
;
414 struct radeon_state_atom mat
[5];
415 struct radeon_state_atom lit
[8]; /* includes vec, scl commands */
416 struct radeon_state_atom ucp
[6];
417 struct radeon_state_atom eye
; /* eye pos */
418 struct radeon_state_atom grd
; /* guard band clipping */
419 struct radeon_state_atom fog
;
420 struct radeon_state_atom glt
;
421 struct radeon_state_atom txr
[2]; /* for NPOT */
423 int max_state_size
; /* Number of bytes necessary for a full state emit. */
424 GLboolean is_dirty
, all_dirty
;
427 struct radeon_state
{
428 /* Derived state for internal purposes:
430 struct radeon_colorbuffer_state color
;
431 struct radeon_depthbuffer_state depth
;
432 struct radeon_scissor_state scissor
;
433 struct radeon_stencilbuffer_state stencil
;
434 struct radeon_stipple_state stipple
;
435 struct radeon_texture_state texture
;
439 /* Need refcounting on dma buffers:
441 struct radeon_dma_buffer
{
442 int refcount
; /* the number of retained regions in buf */
446 #define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
447 (rvb)->address - rmesa->dma.buf0_address + \
450 /* A retained region, eg vertices for indexed vertices.
452 struct radeon_dma_region
{
453 struct radeon_dma_buffer
*buf
;
454 char *address
; /* == buf->address */
455 int start
, end
, ptr
; /* offsets from start of buf */
463 /* Active dma region. Allocations for vertices and retained
464 * regions come from here. Also used for emitting random vertices,
465 * these may be flushed by calling flush_current();
467 struct radeon_dma_region current
;
469 void (*flush
)( radeonContextPtr
);
471 char *buf0_address
; /* start of buf[0], for index calcs */
472 GLuint nr_released_bufs
; /* flush after so many buffers released */
475 struct radeon_dri_mirror
{
476 __DRIcontextPrivate
*context
; /* DRI context */
477 __DRIscreenPrivate
*screen
; /* DRI screen */
478 __DRIdrawablePrivate
*drawable
; /* DRI drawable bound to this ctx */
480 drm_context_t hwContext
;
481 drm_hw_lock_t
*hwLock
;
487 #define RADEON_CMD_BUF_SZ (8*1024)
489 struct radeon_store
{
492 char cmd_buf
[RADEON_CMD_BUF_SZ
];
500 struct radeon_tcl_info
{
501 GLuint vertex_format
;
505 /* Temporary for cases where incoming vertex data is incompatible
510 struct radeon_dma_region
*aos_components
[8];
511 GLuint nr_aos_components
;
515 struct radeon_dma_region indexed_verts
;
516 struct radeon_dma_region obj
;
517 struct radeon_dma_region rgba
;
518 struct radeon_dma_region spec
;
519 struct radeon_dma_region fog
;
520 struct radeon_dma_region tex
[RADEON_MAX_TEXTURE_UNITS
];
521 struct radeon_dma_region norm
;
527 struct radeon_swtcl_info
{
530 GLuint vertex_format
;
532 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
533 GLuint vertex_attr_count
;
537 /* Fallback rasterization functions
539 radeon_point_func draw_point
;
540 radeon_line_func draw_line
;
541 radeon_tri_func draw_tri
;
544 GLenum render_primitive
;
548 * Offset of the 4UB color data within a hardware (swtcl) vertex.
553 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
559 struct radeon_dma_region indexed_verts
;
563 struct radeon_ioctl
{
564 GLuint vertex_offset
;
570 #define RADEON_MAX_PRIMS 64
573 /* Want to keep a cache of these around. Each is parameterized by
574 * only a single value which has only a small range. Only expect a
575 * few, so just rescan the list each time?
578 struct dynfn
*next
, *prev
;
584 struct dynfn Vertex2f
;
585 struct dynfn Vertex2fv
;
586 struct dynfn Vertex3f
;
587 struct dynfn Vertex3fv
;
588 struct dynfn Color4ub
;
589 struct dynfn Color4ubv
;
590 struct dynfn Color3ub
;
591 struct dynfn Color3ubv
;
592 struct dynfn Color4f
;
593 struct dynfn Color4fv
;
594 struct dynfn Color3f
;
595 struct dynfn Color3fv
;
596 struct dynfn SecondaryColor3ubEXT
;
597 struct dynfn SecondaryColor3ubvEXT
;
598 struct dynfn SecondaryColor3fEXT
;
599 struct dynfn SecondaryColor3fvEXT
;
600 struct dynfn Normal3f
;
601 struct dynfn Normal3fv
;
602 struct dynfn TexCoord2f
;
603 struct dynfn TexCoord2fv
;
604 struct dynfn TexCoord1f
;
605 struct dynfn TexCoord1fv
;
606 struct dynfn MultiTexCoord2fARB
;
607 struct dynfn MultiTexCoord2fvARB
;
608 struct dynfn MultiTexCoord1fARB
;
609 struct dynfn MultiTexCoord1fvARB
;
612 struct dfn_generators
{
613 struct dynfn
*(*Vertex2f
)( GLcontext
*, int );
614 struct dynfn
*(*Vertex2fv
)( GLcontext
*, int );
615 struct dynfn
*(*Vertex3f
)( GLcontext
*, int );
616 struct dynfn
*(*Vertex3fv
)( GLcontext
*, int );
617 struct dynfn
*(*Color4ub
)( GLcontext
*, int );
618 struct dynfn
*(*Color4ubv
)( GLcontext
*, int );
619 struct dynfn
*(*Color3ub
)( GLcontext
*, int );
620 struct dynfn
*(*Color3ubv
)( GLcontext
*, int );
621 struct dynfn
*(*Color4f
)( GLcontext
*, int );
622 struct dynfn
*(*Color4fv
)( GLcontext
*, int );
623 struct dynfn
*(*Color3f
)( GLcontext
*, int );
624 struct dynfn
*(*Color3fv
)( GLcontext
*, int );
625 struct dynfn
*(*SecondaryColor3ubEXT
)( GLcontext
*, int );
626 struct dynfn
*(*SecondaryColor3ubvEXT
)( GLcontext
*, int );
627 struct dynfn
*(*SecondaryColor3fEXT
)( GLcontext
*, int );
628 struct dynfn
*(*SecondaryColor3fvEXT
)( GLcontext
*, int );
629 struct dynfn
*(*Normal3f
)( GLcontext
*, int );
630 struct dynfn
*(*Normal3fv
)( GLcontext
*, int );
631 struct dynfn
*(*TexCoord2f
)( GLcontext
*, int );
632 struct dynfn
*(*TexCoord2fv
)( GLcontext
*, int );
633 struct dynfn
*(*TexCoord1f
)( GLcontext
*, int );
634 struct dynfn
*(*TexCoord1fv
)( GLcontext
*, int );
635 struct dynfn
*(*MultiTexCoord2fARB
)( GLcontext
*, int );
636 struct dynfn
*(*MultiTexCoord2fvARB
)( GLcontext
*, int );
637 struct dynfn
*(*MultiTexCoord1fARB
)( GLcontext
*, int );
638 struct dynfn
*(*MultiTexCoord1fvARB
)( GLcontext
*, int );
649 struct radeon_vbinfo
{
650 GLint counter
, initial_counter
;
652 void (*notify
)( void );
655 /* A maximum total of 15 elements per vertex: 3 floats for position, 3
656 * floats for normal, 4 floats for color, 4 bytes for secondary color,
657 * 2 floats for each texture unit (4 floats total).
659 * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are
660 * supported, this value will grow.
662 * The position data is never actually stored here, so 3 elements could be
663 * trimmed out of the buffer.
665 union { float f
; int i
; radeon_color_t color
; } vertex
[15];
668 GLfloat
*floatcolorptr
;
669 radeon_color_t
*colorptr
;
670 GLfloat
*floatspecptr
;
671 radeon_color_t
*specptr
;
672 GLfloat
*texcoordptr
[2];
674 GLenum
*prim
; /* &ctx->Driver.CurrentExecPrimitive */
676 GLboolean enabled
; /* *_NO_VTXFMT / *_NO_TCL env vars */
681 GLuint vertex_format
;
683 GLuint installed_vertex_format
;
684 GLuint installed_color_3f_sz
;
686 struct radeon_prim primlist
[RADEON_MAX_PRIMS
];
689 struct dfn_lists dfn_cache
;
690 struct dfn_generators codegen
;
691 GLvertexformat vtxfmt
;
697 struct radeon_context
{
698 GLcontext
*glCtx
; /* Mesa context */
700 /* Driver and hardware state management
702 struct radeon_hw_state hw
;
703 struct radeon_state state
;
705 /* Texture object bookkeeping
708 driTexHeap
* texture_heaps
[ RADEON_NR_TEX_HEAPS
];
709 driTextureObject swapped
;
711 float initialMaxAnisotropy
;
713 /* Rasterization and vertex state:
718 GLuint tnl_index
; /* index of bits for last tnl_install_attrs */
722 struct radeon_ioctl ioctl
;
723 struct radeon_dma dma
;
724 struct radeon_store store
;
725 /* A full state emit as of the first state emit in the main store, in case
726 * the context is lost.
728 struct radeon_store backup_store
;
739 drm_radeon_irq_wait_t iw
;
741 /* Drawable, cliprect and scissor information
743 GLuint numClipRects
; /* Cliprects for the draw buffer */
744 drm_clip_rect_t
*pClipRects
;
745 unsigned int lastStamp
;
746 GLboolean lost_context
;
747 GLboolean save_on_next_emit
;
748 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
749 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
753 GLmatrix TexGenMatrix
[RADEON_MAX_TEXTURE_UNITS
];
754 GLboolean recheck_texgen
[RADEON_MAX_TEXTURE_UNITS
];
755 GLboolean TexGenNeedNormals
[RADEON_MAX_TEXTURE_UNITS
];
756 GLuint TexMatEnabled
;
757 GLuint TexGenEnabled
;
759 GLuint last_ReallyEnabled
;
767 int64_t swap_missed_ust
;
770 GLuint swap_missed_count
;
775 struct radeon_tcl_info tcl
;
779 struct radeon_swtcl_info swtcl
;
783 struct radeon_vbinfo vb
;
785 /* Mirrors of some DRI state
787 struct radeon_dri_mirror dri
;
789 /* Configuration cache
791 driOptionCache optionCache
;
793 GLboolean using_hyperz
;
794 GLboolean texmicrotile
;
796 /* Performance counters
798 GLuint boxes
; /* Draw performance boxes */
799 GLuint hardwareWentIdle
;
802 GLuint c_textureSwaps
;
803 GLuint c_textureBytes
;
804 GLuint c_vertexBuffers
;
807 #define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
810 static __inline GLuint
radeonPackColor( GLuint cpp
,
811 GLubyte r
, GLubyte g
,
812 GLubyte b
, GLubyte a
)
816 return PACK_COLOR_565( r
, g
, b
);
818 return PACK_COLOR_8888( a
, r
, g
, b
);
824 #define RADEON_OLD_PACKETS 1
827 extern void radeonDestroyContext( __DRIcontextPrivate
*driContextPriv
);
828 extern GLboolean
radeonCreateContext(const __GLcontextModes
*glVisual
,
829 __DRIcontextPrivate
*driContextPriv
,
830 void *sharedContextPrivate
);
831 extern void radeonSwapBuffers( __DRIdrawablePrivate
*dPriv
);
832 extern GLboolean
radeonMakeCurrent( __DRIcontextPrivate
*driContextPriv
,
833 __DRIdrawablePrivate
*driDrawPriv
,
834 __DRIdrawablePrivate
*driReadPriv
);
835 extern GLboolean
radeonUnbindContext( __DRIcontextPrivate
*driContextPriv
);
837 /* ================================================================
843 extern int RADEON_DEBUG
;
845 #define RADEON_DEBUG 0
848 #define DEBUG_TEXTURE 0x001
849 #define DEBUG_STATE 0x002
850 #define DEBUG_IOCTL 0x004
851 #define DEBUG_PRIMS 0x008
852 #define DEBUG_VERTS 0x010
853 #define DEBUG_FALLBACKS 0x020
854 #define DEBUG_VFMT 0x040
855 #define DEBUG_CODEGEN 0x080
856 #define DEBUG_VERBOSE 0x100
857 #define DEBUG_DRI 0x200
858 #define DEBUG_DMA 0x400
859 #define DEBUG_SANITY 0x800
860 #define DEBUG_SYNC 0x1000
862 #endif /* __RADEON_CONTEXT_H__ */