src/mesa/drivers/dri/radeon/radeon_context.h

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Kevin E. Martin <martin@valinux.com>
  34  *   Gareth Hughes <gareth@valinux.com>
  35  *   Keith Whitwell <keith@tungstengraphics.com>
  36  */
  37
  38 #ifndef __RADEON_CONTEXT_H__
  39 #define __RADEON_CONTEXT_H__
  40
  41 #include "tnl/t_vertex.h"
  42 #include "dri_util.h"
  43 #include "drm.h"
  44 #include "radeon_drm.h"
  45 #include "texmem.h"
  46
  47 #include "macros.h"
  48 #include "mtypes.h"
  49 #include "colormac.h"
  50
  51 struct radeon_context;
  52 typedef struct radeon_context radeonContextRec;
  53 typedef struct radeon_context *radeonContextPtr;
  54
  55 #include "radeon_lock.h"
  56 #include "radeon_screen.h"
  57 #include "mm.h"
  58
  59 #include "math/m_vector.h"
  60
  61 /* Flags for software fallback cases */
  62 /* See correponding strings in radeon_swtcl.c */
  63 #define RADEON_FALLBACK_TEXTURE         0x0001
  64 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  65 #define RADEON_FALLBACK_STENCIL         0x0004
  66 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  67 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  68 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  69 #define RADEON_FALLBACK_DISABLE         0x0040
  70 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  71
  72 /* The blit width for texture uploads
  73  */
  74 #define BLIT_WIDTH_BYTES 1024
  75
  76 /* Use the templated vertex format:
  77  */
  78 #define COLOR_IS_RGBA
  79 #define TAG(x) radeon##x
  80 #include "tnl_dd/t_dd_vertex.h"
  81 #undef TAG
  82
  83 typedef void (*radeon_tri_func)( radeonContextPtr,
  84                                  radeonVertex *,
  85                                  radeonVertex *,
  86                                  radeonVertex * );
  87
  88 typedef void (*radeon_line_func)( radeonContextPtr,
  89                                   radeonVertex *,
  90                                   radeonVertex * );
  91
  92 typedef void (*radeon_point_func)( radeonContextPtr,
  93                                    radeonVertex * );
  94
  95
  96 struct radeon_colorbuffer_state {
  97    GLuint clear;
  98    int roundEnable;
  99 };
 100
 101
 102 struct radeon_depthbuffer_state {
 103    GLuint clear;
 104    GLfloat scale;
 105 };
 106
 107 struct radeon_scissor_state {
 108    drm_clip_rect_t rect;
 109    GLboolean enabled;
 110
 111    GLuint numClipRects;                 /* Cliprects active */
 112    GLuint numAllocedClipRects;          /* Cliprects available */
 113    drm_clip_rect_t *pClipRects;
 114 };
 115
 116 struct radeon_stencilbuffer_state {
 117    GLboolean hwBuffer;
 118    GLuint clear;                        /* rb3d_stencilrefmask value */
 119 };
 120
 121 struct radeon_stipple_state {
 122    GLuint mask[32];
 123 };
 124
 125 /* used for both tcl_vtx and vc_frmt tex bits (they are identical) */
 126 #define RADEON_ST_BIT(unit) \
 127 (unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit))
 128
 129 #define RADEON_Q_BIT(unit) \
 130 (unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit))
 131
 132 #define TEX_0   0x1
 133 #define TEX_1   0x2
 134 #define TEX_2   0x4
 135 #define TEX_ALL 0x7
 136
 137 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 138
 139 /* Texture object in locally shared texture space.
 140  */
 141 struct radeon_tex_obj {
 142    driTextureObject   base;
 143
 144    GLuint bufAddr;                      /* Offset to start of locally
 145                                            shared texture block */
 146
 147    GLuint dirty_state;                  /* Flags (1 per texunit) for
 148                                            whether or not this texobj
 149                                            has dirty hardware state
 150                                            (pp_*) that needs to be
 151                                            brought into the
 152                                            texunit. */
 153
 154    drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 155                                         /* Six, for the cube faces */
 156
 157    GLuint pp_txfilter;                  /* hardware register values */
 158    GLuint pp_txformat;
 159    GLuint pp_txoffset;                  /* Image location in texmem.
 160                                            All cube faces follow. */
 161    GLuint pp_txsize;                    /* npot only */
 162    GLuint pp_txpitch;                   /* npot only */
 163    GLuint pp_border_color;
 164    GLuint pp_cubic_faces;               /* cube face 1,2,3,4 log2 sizes */
 165
 166    GLboolean  border_fallback;
 167
 168    GLuint tile_bits;                    /* hw texture tile bits used on this texture */
 169 };
 170
 171
 172 struct radeon_texture_env_state {
 173    radeonTexObjPtr texobj;
 174    GLenum format;
 175    GLenum envMode;
 176 };
 177
 178 struct radeon_texture_state {
 179    struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS];
 180 };
 181
 182
 183 struct radeon_state_atom {
 184    struct radeon_state_atom *next, *prev;
 185    const char *name;                     /* for debug */
 186    int cmd_size;                         /* size in bytes */
 187    GLuint is_tcl;
 188    int *cmd;                             /* one or more cmd's */
 189    int *lastcmd;                         /* one or more cmd's */
 190    GLboolean dirty;                      /* dirty-mark in emit_state_list */
 191    GLboolean (*check)( GLcontext * );    /* is this state active? */
 192 };
 193
 194
 195
 196 /* Trying to keep these relatively short as the variables are becoming
 197  * extravagently long.  Drop the driver name prefix off the front of
 198  * everything - I think we know which driver we're in by now, and keep the
 199  * prefix to 3 letters unless absolutely impossible.
 200  */
 201
 202 #define CTX_CMD_0             0
 203 #define CTX_PP_MISC           1
 204 #define CTX_PP_FOG_COLOR      2
 205 #define CTX_RE_SOLID_COLOR    3
 206 #define CTX_RB3D_BLENDCNTL    4
 207 #define CTX_RB3D_DEPTHOFFSET  5
 208 #define CTX_RB3D_DEPTHPITCH   6
 209 #define CTX_RB3D_ZSTENCILCNTL 7
 210 #define CTX_CMD_1             8
 211 #define CTX_PP_CNTL           9
 212 #define CTX_RB3D_CNTL         10
 213 #define CTX_RB3D_COLOROFFSET  11
 214 #define CTX_CMD_2             12
 215 #define CTX_RB3D_COLORPITCH   13
 216 #define CTX_STATE_SIZE        14
 217
 218 #define SET_CMD_0               0
 219 #define SET_SE_CNTL             1
 220 #define SET_SE_COORDFMT         2
 221 #define SET_CMD_1               3
 222 #define SET_SE_CNTL_STATUS      4
 223 #define SET_STATE_SIZE          5
 224
 225 #define LIN_CMD_0               0
 226 #define LIN_RE_LINE_PATTERN     1
 227 #define LIN_RE_LINE_STATE       2
 228 #define LIN_CMD_1               3
 229 #define LIN_SE_LINE_WIDTH       4
 230 #define LIN_STATE_SIZE          5
 231
 232 #define MSK_CMD_0               0
 233 #define MSK_RB3D_STENCILREFMASK 1
 234 #define MSK_RB3D_ROPCNTL        2
 235 #define MSK_RB3D_PLANEMASK      3
 236 #define MSK_STATE_SIZE          4
 237
 238 #define VPT_CMD_0           0
 239 #define VPT_SE_VPORT_XSCALE          1
 240 #define VPT_SE_VPORT_XOFFSET         2
 241 #define VPT_SE_VPORT_YSCALE          3
 242 #define VPT_SE_VPORT_YOFFSET         4
 243 #define VPT_SE_VPORT_ZSCALE          5
 244 #define VPT_SE_VPORT_ZOFFSET         6
 245 #define VPT_STATE_SIZE      7
 246
 247 #define MSC_CMD_0               0
 248 #define MSC_RE_MISC             1
 249 #define MSC_STATE_SIZE          2
 250
 251 #define TEX_CMD_0                   0
 252 #define TEX_PP_TXFILTER             1
 253 #define TEX_PP_TXFORMAT             2
 254 #define TEX_PP_TXOFFSET             3
 255 #define TEX_PP_TXCBLEND             4
 256 #define TEX_PP_TXABLEND             5
 257 #define TEX_PP_TFACTOR              6
 258 #define TEX_CMD_1                   7
 259 #define TEX_PP_BORDER_COLOR         8
 260 #define TEX_STATE_SIZE              9
 261
 262 #define TXR_CMD_0                   0 /* rectangle textures */
 263 #define TXR_PP_TEX_SIZE             1 /* 0x1d04, 0x1d0c for NPOT! */
 264 #define TXR_PP_TEX_PITCH            2 /* 0x1d08, 0x1d10 for NPOT! */
 265 #define TXR_STATE_SIZE              3
 266
 267 #define CUBE_CMD_0                  0
 268 #define CUBE_PP_CUBIC_FACES         1
 269 #define CUBE_CMD_1                  2
 270 #define CUBE_PP_CUBIC_OFFSET_0      3
 271 #define CUBE_PP_CUBIC_OFFSET_1      4
 272 #define CUBE_PP_CUBIC_OFFSET_2      5
 273 #define CUBE_PP_CUBIC_OFFSET_3      6
 274 #define CUBE_PP_CUBIC_OFFSET_4      7
 275 #define CUBE_STATE_SIZE             8
 276
 277 #define ZBS_CMD_0              0
 278 #define ZBS_SE_ZBIAS_FACTOR             1
 279 #define ZBS_SE_ZBIAS_CONSTANT           2
 280 #define ZBS_STATE_SIZE         3
 281
 282 #define TCL_CMD_0                        0
 283 #define TCL_OUTPUT_VTXFMT         1
 284 #define TCL_OUTPUT_VTXSEL         2
 285 #define TCL_MATRIX_SELECT_0       3
 286 #define TCL_MATRIX_SELECT_1       4
 287 #define TCL_UCP_VERT_BLEND_CTL    5
 288 #define TCL_TEXTURE_PROC_CTL      6
 289 #define TCL_LIGHT_MODEL_CTL       7
 290 #define TCL_PER_LIGHT_CTL_0       8
 291 #define TCL_PER_LIGHT_CTL_1       9
 292 #define TCL_PER_LIGHT_CTL_2       10
 293 #define TCL_PER_LIGHT_CTL_3       11
 294 #define TCL_STATE_SIZE                   12
 295
 296 #define MTL_CMD_0            0
 297 #define MTL_EMMISSIVE_RED    1
 298 #define MTL_EMMISSIVE_GREEN  2
 299 #define MTL_EMMISSIVE_BLUE   3
 300 #define MTL_EMMISSIVE_ALPHA  4
 301 #define MTL_AMBIENT_RED      5
 302 #define MTL_AMBIENT_GREEN    6
 303 #define MTL_AMBIENT_BLUE     7
 304 #define MTL_AMBIENT_ALPHA    8
 305 #define MTL_DIFFUSE_RED      9
 306 #define MTL_DIFFUSE_GREEN    10
 307 #define MTL_DIFFUSE_BLUE     11
 308 #define MTL_DIFFUSE_ALPHA    12
 309 #define MTL_SPECULAR_RED     13
 310 #define MTL_SPECULAR_GREEN   14
 311 #define MTL_SPECULAR_BLUE    15
 312 #define MTL_SPECULAR_ALPHA   16
 313 #define MTL_SHININESS        17
 314 #define MTL_STATE_SIZE       18
 315
 316 #define VTX_CMD_0              0
 317 #define VTX_SE_COORD_FMT       1
 318 #define VTX_STATE_SIZE         2
 319
 320 #define MAT_CMD_0              0
 321 #define MAT_ELT_0              1
 322 #define MAT_STATE_SIZE         17
 323
 324 #define GRD_CMD_0                  0
 325 #define GRD_VERT_GUARD_CLIP_ADJ    1
 326 #define GRD_VERT_GUARD_DISCARD_ADJ 2
 327 #define GRD_HORZ_GUARD_CLIP_ADJ    3
 328 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
 329 #define GRD_STATE_SIZE             5
 330
 331 /* position changes frequently when lighting in modelpos - separate
 332  * out to new state item?
 333  */
 334 #define LIT_CMD_0                  0
 335 #define LIT_AMBIENT_RED            1
 336 #define LIT_AMBIENT_GREEN          2
 337 #define LIT_AMBIENT_BLUE           3
 338 #define LIT_AMBIENT_ALPHA          4
 339 #define LIT_DIFFUSE_RED            5
 340 #define LIT_DIFFUSE_GREEN          6
 341 #define LIT_DIFFUSE_BLUE           7
 342 #define LIT_DIFFUSE_ALPHA          8
 343 #define LIT_SPECULAR_RED           9
 344 #define LIT_SPECULAR_GREEN         10
 345 #define LIT_SPECULAR_BLUE          11
 346 #define LIT_SPECULAR_ALPHA         12
 347 #define LIT_POSITION_X             13
 348 #define LIT_POSITION_Y             14
 349 #define LIT_POSITION_Z             15
 350 #define LIT_POSITION_W             16
 351 #define LIT_DIRECTION_X            17
 352 #define LIT_DIRECTION_Y            18
 353 #define LIT_DIRECTION_Z            19
 354 #define LIT_DIRECTION_W            20
 355 #define LIT_ATTEN_QUADRATIC        21
 356 #define LIT_ATTEN_LINEAR           22
 357 #define LIT_ATTEN_CONST            23
 358 #define LIT_ATTEN_XXX              24
 359 #define LIT_CMD_1                  25
 360 #define LIT_SPOT_DCD               26
 361 #define LIT_SPOT_EXPONENT          27
 362 #define LIT_SPOT_CUTOFF            28
 363 #define LIT_SPECULAR_THRESH        29
 364 #define LIT_RANGE_CUTOFF           30 /* ? */
 365 #define LIT_ATTEN_CONST_INV        31
 366 #define LIT_STATE_SIZE             32
 367
 368 /* Fog
 369  */
 370 #define FOG_CMD_0      0
 371 #define FOG_R          1
 372 #define FOG_C          2
 373 #define FOG_D          3
 374 #define FOG_PAD        4
 375 #define FOG_STATE_SIZE 5
 376
 377 /* UCP
 378  */
 379 #define UCP_CMD_0      0
 380 #define UCP_X          1
 381 #define UCP_Y          2
 382 #define UCP_Z          3
 383 #define UCP_W          4
 384 #define UCP_STATE_SIZE 5
 385
 386 /* GLT - Global ambient
 387  */
 388 #define GLT_CMD_0      0
 389 #define GLT_RED        1
 390 #define GLT_GREEN      2
 391 #define GLT_BLUE       3
 392 #define GLT_ALPHA      4
 393 #define GLT_STATE_SIZE 5
 394
 395 /* EYE
 396  */
 397 #define EYE_CMD_0          0
 398 #define EYE_X              1
 399 #define EYE_Y              2
 400 #define EYE_Z              3
 401 #define EYE_RESCALE_FACTOR 4
 402 #define EYE_STATE_SIZE     5
 403
 404 #define SHN_CMD_0          0
 405 #define SHN_SHININESS      1
 406 #define SHN_STATE_SIZE     2
 407
 408
 409
 410
 411
 412 struct radeon_hw_state {
 413    /* Head of the linked list of state atoms. */
 414    struct radeon_state_atom atomlist;
 415
 416    /* Hardware state, stored as cmdbuf commands:
 417     *   -- Need to doublebuffer for
 418     *           - eliding noop statechange loops? (except line stipple count)
 419     */
 420    struct radeon_state_atom ctx;
 421    struct radeon_state_atom set;
 422    struct radeon_state_atom lin;
 423    struct radeon_state_atom msk;
 424    struct radeon_state_atom vpt;
 425    struct radeon_state_atom tcl;
 426    struct radeon_state_atom msc;
 427    struct radeon_state_atom tex[3];
 428    struct radeon_state_atom cube[3];
 429    struct radeon_state_atom zbs;
 430    struct radeon_state_atom mtl;
 431    struct radeon_state_atom mat[6];
 432    struct radeon_state_atom lit[8]; /* includes vec, scl commands */
 433    struct radeon_state_atom ucp[6];
 434    struct radeon_state_atom eye; /* eye pos */
 435    struct radeon_state_atom grd; /* guard band clipping */
 436    struct radeon_state_atom fog;
 437    struct radeon_state_atom glt;
 438    struct radeon_state_atom txr[3]; /* for NPOT */
 439
 440    int max_state_size;  /* Number of bytes necessary for a full state emit. */
 441    GLboolean is_dirty, all_dirty;
 442 };
 443
 444 struct radeon_state {
 445    /* Derived state for internal purposes:
 446     */
 447    struct radeon_colorbuffer_state color;
 448    struct radeon_depthbuffer_state depth;
 449    struct radeon_scissor_state scissor;
 450    struct radeon_stencilbuffer_state stencil;
 451    struct radeon_stipple_state stipple;
 452    struct radeon_texture_state texture;
 453 };
 454
 455
 456 /* Need refcounting on dma buffers:
 457  */
 458 struct radeon_dma_buffer {
 459    int refcount;                /* the number of retained regions in buf */
 460    drmBufPtr buf;
 461 };
 462
 463 #define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset +                       \
 464                         (rvb)->address - rmesa->dma.buf0_address +      \
 465                         (rvb)->start)
 466
 467 /* A retained region, eg vertices for indexed vertices.
 468  */
 469 struct radeon_dma_region {
 470    struct radeon_dma_buffer *buf;
 471    char *address;               /* == buf->address */
 472    int start, end, ptr;         /* offsets from start of buf */
 473    int aos_start;
 474    int aos_stride;
 475    int aos_size;
 476 };
 477
 478
 479 struct radeon_dma {
 480    /* Active dma region.  Allocations for vertices and retained
 481     * regions come from here.  Also used for emitting random vertices,
 482     * these may be flushed by calling flush_current();
 483     */
 484    struct radeon_dma_region current;
 485
 486    void (*flush)( radeonContextPtr );
 487
 488    char *buf0_address;          /* start of buf[0], for index calcs */
 489    GLuint nr_released_bufs;     /* flush after so many buffers released */
 490 };
 491
 492 struct radeon_dri_mirror {
 493    __DRIcontextPrivate  *context;       /* DRI context */
 494    __DRIscreenPrivate   *screen;        /* DRI screen */
 495    __DRIdrawablePrivate *drawable;      /* DRI drawable bound to this ctx */
 496
 497    drm_context_t hwContext;
 498    drm_hw_lock_t *hwLock;
 499    int fd;
 500    int drmMinor;
 501 };
 502
 503
 504 #define RADEON_CMD_BUF_SZ  (8*1024)
 505
 506 struct radeon_store {
 507    GLuint statenr;
 508    GLuint primnr;
 509    char cmd_buf[RADEON_CMD_BUF_SZ];
 510    int cmd_used;
 511    int elts_start;
 512 };
 513
 514
 515 /* radeon_tcl.c
 516  */
 517 struct radeon_tcl_info {
 518    GLuint vertex_format;
 519    GLint last_offset;
 520    GLuint hw_primitive;
 521
 522    /* Temporary for cases where incoming vertex data is incompatible
 523     * with maos code.
 524     */
 525    GLvector4f ObjClean;
 526
 527    struct radeon_dma_region *aos_components[8];
 528    GLuint nr_aos_components;
 529
 530    GLuint *Elts;
 531
 532    struct radeon_dma_region indexed_verts;
 533    struct radeon_dma_region obj;
 534    struct radeon_dma_region rgba;
 535    struct radeon_dma_region spec;
 536    struct radeon_dma_region fog;
 537    struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
 538    struct radeon_dma_region norm;
 539 };
 540
 541
 542 /* radeon_swtcl.c
 543  */
 544 struct radeon_swtcl_info {
 545    GLuint RenderIndex;
 546    GLuint vertex_size;
 547    GLuint vertex_format;
 548
 549    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 550    GLuint vertex_attr_count;
 551
 552    GLubyte *verts;
 553
 554    /* Fallback rasterization functions
 555     */
 556    radeon_point_func draw_point;
 557    radeon_line_func draw_line;
 558    radeon_tri_func draw_tri;
 559
 560    GLuint hw_primitive;
 561    GLenum render_primitive;
 562    GLuint numverts;
 563
 564    /**
 565     * Offset of the 4UB color data within a hardware (swtcl) vertex.
 566     */
 567    GLuint coloroffset;
 568
 569    /**
 570     * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
 571     */
 572    GLuint specoffset;
 573
 574    GLboolean needproj;
 575
 576    struct radeon_dma_region indexed_verts;
 577 };
 578
 579
 580 struct radeon_ioctl {
 581    GLuint vertex_offset;
 582    GLuint vertex_size;
 583 };
 584
 585
 586
 587 #define RADEON_MAX_PRIMS 64
 588
 589
 590 /* Want to keep a cache of these around.  Each is parameterized by
 591  * only a single value which has only a small range.  Only expect a
 592  * few, so just rescan the list each time?
 593  */
 594 struct dynfn {
 595    struct dynfn *next, *prev;
 596    int key;
 597    char *code;
 598 };
 599
 600 struct dfn_lists {
 601    struct dynfn Vertex2f;
 602    struct dynfn Vertex2fv;
 603    struct dynfn Vertex3f;
 604    struct dynfn Vertex3fv;
 605    struct dynfn Color4ub;
 606    struct dynfn Color4ubv;
 607    struct dynfn Color3ub;
 608    struct dynfn Color3ubv;
 609    struct dynfn Color4f;
 610    struct dynfn Color4fv;
 611    struct dynfn Color3f;
 612    struct dynfn Color3fv;
 613    struct dynfn SecondaryColor3ubEXT;
 614    struct dynfn SecondaryColor3ubvEXT;
 615    struct dynfn SecondaryColor3fEXT;
 616    struct dynfn SecondaryColor3fvEXT;
 617    struct dynfn Normal3f;
 618    struct dynfn Normal3fv;
 619    struct dynfn TexCoord2f;
 620    struct dynfn TexCoord2fv;
 621    struct dynfn TexCoord1f;
 622    struct dynfn TexCoord1fv;
 623    struct dynfn MultiTexCoord2fARB;
 624    struct dynfn MultiTexCoord2fvARB;
 625    struct dynfn MultiTexCoord1fARB;
 626    struct dynfn MultiTexCoord1fvARB;
 627 };
 628
 629 struct dfn_generators {
 630    struct dynfn *(*Vertex2f)( GLcontext *, int );
 631    struct dynfn *(*Vertex2fv)( GLcontext *, int );
 632    struct dynfn *(*Vertex3f)( GLcontext *, int );
 633    struct dynfn *(*Vertex3fv)( GLcontext *, int );
 634    struct dynfn *(*Color4ub)( GLcontext *, int );
 635    struct dynfn *(*Color4ubv)( GLcontext *, int );
 636    struct dynfn *(*Color3ub)( GLcontext *, int );
 637    struct dynfn *(*Color3ubv)( GLcontext *, int );
 638    struct dynfn *(*Color4f)( GLcontext *, int );
 639    struct dynfn *(*Color4fv)( GLcontext *, int );
 640    struct dynfn *(*Color3f)( GLcontext *, int );
 641    struct dynfn *(*Color3fv)( GLcontext *, int );
 642    struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int );
 643    struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int );
 644    struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int );
 645    struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int );
 646    struct dynfn *(*Normal3f)( GLcontext *, int );
 647    struct dynfn *(*Normal3fv)( GLcontext *, int );
 648    struct dynfn *(*TexCoord2f)( GLcontext *, int );
 649    struct dynfn *(*TexCoord2fv)( GLcontext *, int );
 650    struct dynfn *(*TexCoord1f)( GLcontext *, int );
 651    struct dynfn *(*TexCoord1fv)( GLcontext *, int );
 652    struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int );
 653    struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int );
 654    struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int );
 655    struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int );
 656 };
 657
 658
 659
 660 struct radeon_prim {
 661    GLuint start;
 662    GLuint end;
 663    GLuint prim;
 664 };
 665
 666 /* A maximum total of 20 elements per vertex:  3 floats for position, 3
 667  * floats for normal, 4 floats for color, 4 bytes for secondary color,
 668  * 3 floats for each texture unit (9 floats total).
 669  *
 670  * The position data is never actually stored here, so 3 elements could be
 671  * trimmed out of the buffer. This number is only valid for vtxfmt!
 672  */
 673 #define RADEON_MAX_VERTEX_SIZE 20
 674
 675 struct radeon_vbinfo {
 676    GLint counter, initial_counter;
 677    GLint *dmaptr;
 678    void (*notify)( void );
 679    GLint vertex_size;
 680
 681    union { float f; int i; radeon_color_t color; } vertex[RADEON_MAX_VERTEX_SIZE];
 682
 683    GLfloat *normalptr;
 684    GLfloat *floatcolorptr;
 685    radeon_color_t *colorptr;
 686    GLfloat *floatspecptr;
 687    radeon_color_t *specptr;
 688    GLfloat *texcoordptr[4];     /* 3 (TMU) + 1 for radeon_vtxfmt_c.c when GL_TEXTURE3 */
 689
 690    GLenum *prim;                /* &ctx->Driver.CurrentExecPrimitive */
 691    GLuint primflags;
 692    GLboolean enabled;           /* *_NO_VTXFMT / *_NO_TCL env vars */
 693    GLboolean installed;
 694    GLboolean fell_back;
 695    GLboolean recheck;
 696    GLint nrverts;
 697    GLuint vertex_format;
 698
 699    GLuint installed_vertex_format;
 700    GLuint installed_color_3f_sz;
 701
 702    struct radeon_prim primlist[RADEON_MAX_PRIMS];
 703    int nrprims;
 704
 705    struct dfn_lists dfn_cache;
 706    struct dfn_generators codegen;
 707    GLvertexformat vtxfmt;
 708 };
 709
 710
 711
 712
 713 struct radeon_context {
 714    GLcontext *glCtx;                    /* Mesa context */
 715
 716    /* Driver and hardware state management
 717     */
 718    struct radeon_hw_state hw;
 719    struct radeon_state state;
 720
 721    /* Texture object bookkeeping
 722     */
 723    unsigned              nr_heaps;
 724    driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
 725    driTextureObject      swapped;
 726    int                   texture_depth;
 727    float                 initialMaxAnisotropy;
 728
 729    /* Rasterization and vertex state:
 730     */
 731    GLuint TclFallback;
 732    GLuint Fallback;
 733    GLuint NewGLState;
 734    GLuint tnl_index;    /* index of bits for last tnl_install_attrs */
 735
 736    /* Vertex buffers
 737     */
 738    struct radeon_ioctl ioctl;
 739    struct radeon_dma dma;
 740    struct radeon_store store;
 741    /* A full state emit as of the first state emit in the main store, in case
 742     * the context is lost.
 743     */
 744    struct radeon_store backup_store;
 745
 746    /* Page flipping
 747     */
 748    GLuint doPageFlip;
 749
 750    /* Busy waiting
 751     */
 752    GLuint do_usleeps;
 753    GLuint do_irqs;
 754    GLuint irqsEmitted;
 755    drm_radeon_irq_wait_t iw;
 756
 757    /* Drawable, cliprect and scissor information
 758     */
 759    GLuint numClipRects;                 /* Cliprects for the draw buffer */
 760    drm_clip_rect_t *pClipRects;
 761    unsigned int lastStamp;
 762    GLboolean lost_context;
 763    GLboolean save_on_next_emit;
 764    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 765    drm_radeon_sarea_t *sarea;           /* Private SAREA data */
 766
 767    /* TCL stuff
 768     */
 769    GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS];
 770    GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS];
 771    GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS];
 772    GLuint TexGenEnabled;
 773    GLuint NeedTexMatrix;
 774    GLuint TexMatColSwap;
 775    GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS];
 776    GLuint last_ReallyEnabled;
 777
 778    /* VBI
 779     */
 780    GLuint vbl_seq;
 781    GLuint vblank_flags;
 782
 783    int64_t swap_ust;
 784    int64_t swap_missed_ust;
 785
 786    GLuint swap_count;
 787    GLuint swap_missed_count;
 788
 789
 790    /* radeon_tcl.c
 791     */
 792    struct radeon_tcl_info tcl;
 793
 794    /* radeon_swtcl.c
 795     */
 796    struct radeon_swtcl_info swtcl;
 797
 798    /* radeon_vtxfmt.c
 799     */
 800    struct radeon_vbinfo vb;
 801
 802    /* Mirrors of some DRI state
 803     */
 804    struct radeon_dri_mirror dri;
 805
 806    /* Configuration cache
 807     */
 808    driOptionCache optionCache;
 809
 810    GLboolean using_hyperz;
 811    GLboolean texmicrotile;
 812
 813    /* Performance counters
 814     */
 815    GLuint boxes;                        /* Draw performance boxes */
 816    GLuint hardwareWentIdle;
 817    GLuint c_clears;
 818    GLuint c_drawWaits;
 819    GLuint c_textureSwaps;
 820    GLuint c_textureBytes;
 821    GLuint c_vertexBuffers;
 822 };
 823
 824 #define RADEON_CONTEXT(ctx)             ((radeonContextPtr)(ctx->DriverCtx))
 825
 826
 827 static __inline GLuint radeonPackColor( GLuint cpp,
 828                                         GLubyte r, GLubyte g,
 829                                         GLubyte b, GLubyte a )
 830 {
 831    switch ( cpp ) {
 832    case 2:
 833       return PACK_COLOR_565( r, g, b );
 834    case 4:
 835       return PACK_COLOR_8888( a, r, g, b );
 836    default:
 837       return 0;
 838    }
 839 }
 840
 841 #define RADEON_OLD_PACKETS 1
 842
 843
 844 extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv );
 845 extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual,
 846                                      __DRIcontextPrivate *driContextPriv,
 847                                      void *sharedContextPrivate);
 848 extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv );
 849 extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
 850                                     __DRIdrawablePrivate *driDrawPriv,
 851                                     __DRIdrawablePrivate *driReadPriv );
 852 extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv );
 853
 854 /* ================================================================
 855  * Debugging:
 856  */
 857 #define DO_DEBUG                1
 858
 859 #if DO_DEBUG
 860 extern int RADEON_DEBUG;
 861 #else
 862 #define RADEON_DEBUG            0
 863 #endif
 864
 865 #define DEBUG_TEXTURE   0x001
 866 #define DEBUG_STATE     0x002
 867 #define DEBUG_IOCTL     0x004
 868 #define DEBUG_PRIMS     0x008
 869 #define DEBUG_VERTS     0x010
 870 #define DEBUG_FALLBACKS 0x020
 871 #define DEBUG_VFMT      0x040
 872 #define DEBUG_CODEGEN   0x080
 873 #define DEBUG_VERBOSE   0x100
 874 #define DEBUG_DRI       0x200
 875 #define DEBUG_DMA       0x400
 876 #define DEBUG_SANITY    0x800
 877 #define DEBUG_SYNC     0x1000
 878
 879 #endif /* __RADEON_CONTEXT_H__ */