src/mesa/drivers/dri/radeon/radeon_cs_legacy.c

   1 /*
   2  * Copyright © 2008 Nicolai Haehnle
   3  * Copyright © 2008 Jérôme Glisse
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26 /*
  27  * Authors:
  28  *      Aapo Tahkola <aet@rasterburn.org>
  29  *      Nicolai Haehnle <prefect_@gmx.net>
  30  *      Jérôme Glisse <glisse@freedesktop.org>
  31  */
  32 #include <errno.h>
  33
  34 #include "radeon_bocs_wrapper.h"
  35
  36 struct cs_manager_legacy {
  37     struct radeon_cs_manager    base;
  38     struct radeon_context       *ctx;
  39     /* hack for scratch stuff */
  40     uint32_t                    pending_age;
  41     uint32_t                    pending_count;
  42
  43
  44 };
  45
  46 struct cs_reloc_legacy {
  47     struct radeon_cs_reloc  base;
  48     uint32_t                cindices;
  49     uint32_t                *indices;
  50 };
  51
  52
  53 static struct radeon_cs *cs_create(struct radeon_cs_manager *csm,
  54                                    uint32_t ndw)
  55 {
  56     struct radeon_cs *cs;
  57
  58     cs = (struct radeon_cs*)calloc(1, sizeof(struct radeon_cs));
  59     if (cs == NULL) {
  60         return NULL;
  61     }
  62     cs->csm = csm;
  63     cs->ndw = (ndw + 0x3FF) & (~0x3FF);
  64     cs->packets = (uint32_t*)malloc(4*cs->ndw);
  65     if (cs->packets == NULL) {
  66         free(cs);
  67         return NULL;
  68     }
  69     cs->relocs_total_size = 0;
  70     return cs;
  71 }
  72
  73 static int cs_write_reloc(struct radeon_cs *cs,
  74                           struct radeon_bo *bo,
  75                           uint32_t read_domain,
  76                           uint32_t write_domain,
  77                           uint32_t flags)
  78 {
  79     struct cs_reloc_legacy *relocs;
  80     int i;
  81
  82     relocs = (struct cs_reloc_legacy *)cs->relocs;
  83     /* check domains */
  84     if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
  85         /* in one CS a bo can only be in read or write domain but not
  86          * in read & write domain at the same sime
  87          */
  88         return -EINVAL;
  89     }
  90     if (read_domain == RADEON_GEM_DOMAIN_CPU) {
  91         return -EINVAL;
  92     }
  93     if (write_domain == RADEON_GEM_DOMAIN_CPU) {
  94         return -EINVAL;
  95     }
  96     /* check if bo is already referenced */
  97     for(i = 0; i < cs->crelocs; i++) {
  98         uint32_t *indices;
  99
 100         if (relocs[i].base.bo->handle == bo->handle) {
 101             /* Check domains must be in read or write. As we check already
 102              * checked that in argument one of the read or write domain was
 103              * set we only need to check that if previous reloc as the read
 104              * domain set then the read_domain should also be set for this
 105              * new relocation.
 106              */
 107             if (relocs[i].base.read_domain && !read_domain) {
 108                 return -EINVAL;
 109             }
 110             if (relocs[i].base.write_domain && !write_domain) {
 111                 return -EINVAL;
 112             }
 113             relocs[i].base.read_domain |= read_domain;
 114             relocs[i].base.write_domain |= write_domain;
 115             /* save indice */
 116             relocs[i].cindices++;
 117             indices = (uint32_t*)realloc(relocs[i].indices,
 118                                          relocs[i].cindices * 4);
 119             if (indices == NULL) {
 120                 relocs[i].cindices -= 1;
 121                 return -ENOMEM;
 122             }
 123             relocs[i].indices = indices;
 124             relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1;
 125             return 0;
 126         }
 127     }
 128     /* add bo to reloc */
 129     relocs = (struct cs_reloc_legacy*)
 130              realloc(cs->relocs,
 131                      sizeof(struct cs_reloc_legacy) * (cs->crelocs + 1));
 132     if (relocs == NULL) {
 133         return -ENOMEM;
 134     }
 135     cs->relocs = relocs;
 136     relocs[cs->crelocs].base.bo = bo;
 137     relocs[cs->crelocs].base.read_domain = read_domain;
 138     relocs[cs->crelocs].base.write_domain = write_domain;
 139     relocs[cs->crelocs].base.flags = flags;
 140     relocs[cs->crelocs].indices = (uint32_t*)malloc(4);
 141     if (relocs[cs->crelocs].indices == NULL) {
 142         return -ENOMEM;
 143     }
 144     relocs[cs->crelocs].indices[0] = cs->cdw - 1;
 145     relocs[cs->crelocs].cindices = 1;
 146     cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo);
 147     cs->crelocs++;
 148     radeon_bo_ref(bo);
 149     return 0;
 150 }
 151
 152 static int cs_begin(struct radeon_cs *cs,
 153                     uint32_t ndw,
 154                     const char *file,
 155                     const char *func,
 156                     int line)
 157 {
 158     if (cs->section) {
 159         fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
 160                 cs->section_file, cs->section_func, cs->section_line);
 161         fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
 162                 file, func, line);
 163         return -EPIPE;
 164     }
 165     cs->section = 1;
 166     cs->section_ndw = ndw;
 167     cs->section_cdw = 0;
 168     cs->section_file = file;
 169     cs->section_func = func;
 170     cs->section_line = line;
 171
 172
 173     if (cs->cdw + ndw > cs->ndw) {
 174         uint32_t tmp, *ptr;
 175         int num = (ndw > 0x3FF) ? ndw : 0x3FF;
 176
 177         tmp = (cs->cdw + 1 + num) & (~num);
 178         ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
 179         if (ptr == NULL) {
 180             return -ENOMEM;
 181         }
 182         cs->packets = ptr;
 183         cs->ndw = tmp;
 184     }
 185
 186     return 0;
 187 }
 188
 189 static int cs_end(struct radeon_cs *cs,
 190                   const char *file,
 191                   const char *func,
 192                   int line)
 193
 194 {
 195     if (!cs->section) {
 196         fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
 197                 file, func, line);
 198         return -EPIPE;
 199     }
 200     cs->section = 0;
 201     if (cs->section_ndw != cs->section_cdw) {
 202         fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
 203                 cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
 204         fprintf(stderr, "CS section end at (%s,%s,%d)\n",
 205                 file, func, line);
 206         return -EPIPE;
 207     }
 208     return 0;
 209 }
 210
 211 static int cs_process_relocs(struct radeon_cs *cs)
 212 {
 213     struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
 214     struct cs_reloc_legacy *relocs;
 215     int i, j, r;
 216
 217     csm = (struct cs_manager_legacy*)cs->csm;
 218     relocs = (struct cs_reloc_legacy *)cs->relocs;
 219     for (i = 0; i < cs->crelocs; i++) {
 220         for (j = 0; j < relocs[i].cindices; j++) {
 221             uint32_t soffset, eoffset;
 222
 223             r = radeon_bo_legacy_validate(relocs[i].base.bo,
 224                                            &soffset, &eoffset);
 225             if (r) {
 226                 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
 227                         relocs[i].base.bo, soffset, eoffset);
 228                 return r;
 229             }
 230             cs->packets[relocs[i].indices[j]] += soffset;
 231             if (cs->packets[relocs[i].indices[j]] >= eoffset) {
 232               /*                radeon_bo_debug(relocs[i].base.bo, 12); */
 233                 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
 234                         relocs[i].base.bo, soffset, eoffset);
 235                 fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
 236                         relocs[i].base.bo,
 237                         cs->packets[relocs[i].indices[j]],
 238                         eoffset);
 239                 exit(0);
 240                 return -EINVAL;
 241             }
 242         }
 243     }
 244     return 0;
 245 }
 246
 247 static int cs_set_age(struct radeon_cs *cs)
 248 {
 249     struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
 250     struct cs_reloc_legacy *relocs;
 251     int i;
 252
 253     relocs = (struct cs_reloc_legacy *)cs->relocs;
 254     for (i = 0; i < cs->crelocs; i++) {
 255         radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age);
 256         radeon_bo_unref(relocs[i].base.bo);
 257     }
 258     return 0;
 259 }
 260
 261 static void dump_cmdbuf(struct radeon_cs *cs)
 262 {
 263   int i;
 264   for (i = 0; i < cs->cdw; i++){
 265     fprintf(stderr,"%x: %08x\n", i, cs->packets[i]);
 266   }
 267
 268 }
 269 static int cs_emit(struct radeon_cs *cs)
 270 {
 271     struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
 272     drm_radeon_cmd_buffer_t cmd;
 273     drm_r300_cmd_header_t age;
 274     uint64_t ull;
 275     int r;
 276
 277     csm->ctx->vtbl.emit_cs_header(cs, csm->ctx);
 278
 279
 280     /* append buffer age */
 281     if (IS_R300_CLASS(csm->ctx->radeonScreen)) {
 282       age.scratch.cmd_type = R300_CMD_SCRATCH;
 283       /* Scratch register 2 corresponds to what radeonGetAge polls */
 284       csm->pending_age = 0;
 285       csm->pending_count = 1;
 286       ull = (uint64_t) (intptr_t) &csm->pending_age;
 287       age.scratch.reg = 2;
 288       age.scratch.n_bufs = 1;
 289       age.scratch.flags = 0;
 290       radeon_cs_write_dword(cs, age.u);
 291       radeon_cs_write_dword(cs, ull & 0xffffffff);
 292       radeon_cs_write_dword(cs, ull >> 32);
 293       radeon_cs_write_dword(cs, 0);
 294     }
 295
 296     r = cs_process_relocs(cs);
 297     if (r) {
 298         return 0;
 299     }
 300
 301     cmd.buf = (char *)cs->packets;
 302     cmd.bufsz = cs->cdw * 4;
 303     if (csm->ctx->state.scissor.enabled) {
 304         cmd.nbox = csm->ctx->state.scissor.numClipRects;
 305         cmd.boxes = (drm_clip_rect_t *) csm->ctx->state.scissor.pClipRects;
 306     } else {
 307         cmd.nbox = csm->ctx->numClipRects;
 308         cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects;
 309     }
 310
 311     //dump_cmdbuf(cs);
 312
 313     r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
 314     if (r) {
 315         return r;
 316     }
 317     if (!IS_R300_CLASS(csm->ctx->radeonScreen)) {
 318         drm_radeon_irq_emit_t emit_cmd;
 319         emit_cmd.irq_seq = &csm->pending_age;
 320         r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));
 321         if (r) {
 322                 return r;
 323         }
 324     }
 325     cs_set_age(cs);
 326
 327     cs->csm->read_used = 0;
 328     cs->csm->vram_write_used = 0;
 329     cs->csm->gart_write_used = 0;
 330     return 0;
 331 }
 332
 333 static void inline cs_free_reloc(void *relocs_p, int crelocs)
 334 {
 335     struct cs_reloc_legacy *relocs = relocs_p;
 336     int i;
 337     if (!relocs_p)
 338       return;
 339     for (i = 0; i < crelocs; i++)
 340       free(relocs[i].indices);
 341 }
 342
 343 static int cs_destroy(struct radeon_cs *cs)
 344 {
 345     cs_free_reloc(cs->relocs, cs->crelocs);
 346     free(cs->relocs);
 347     free(cs->packets);
 348     free(cs);
 349     return 0;
 350 }
 351
 352 static int cs_erase(struct radeon_cs *cs)
 353 {
 354     cs_free_reloc(cs->relocs, cs->crelocs);
 355     free(cs->relocs);
 356     cs->relocs_total_size = 0;
 357     cs->relocs = NULL;
 358     cs->crelocs = 0;
 359     cs->cdw = 0;
 360     cs->section = 0;
 361     return 0;
 362 }
 363
 364 static int cs_need_flush(struct radeon_cs *cs)
 365 {
 366     /* FIXME: we should get the texture heap size */
 367     return (cs->relocs_total_size > (7*1024*1024));
 368 }
 369
 370 static void cs_print(struct radeon_cs *cs, FILE *file)
 371 {
 372 }
 373
 374 static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo)
 375 {
 376     struct radeon_cs_manager *csm = cs->csm;
 377     int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0;
 378     uint32_t read_domains, write_domain;
 379     int i;
 380     struct radeon_bo *bo;
 381
 382     /* check the totals for this operation */
 383
 384     if (num_bo == 0)
 385         return 0;
 386
 387     /* prepare */
 388     for (i = 0; i < num_bo; i++) {
 389       bo = bos[i].bo;
 390
 391       bos[i].new_accounted = 0;
 392       read_domains = bos[i].read_domains;
 393       write_domain = bos[i].write_domain;
 394
 395       /* pinned bos don't count */
 396       if (radeon_legacy_bo_is_static(bo))
 397           continue;
 398
 399       /* already accounted this bo */
 400       if (write_domain && (write_domain == bo->space_accounted))
 401           continue;
 402
 403       if (read_domains && ((read_domains << 16) == bo->space_accounted))
 404           continue;
 405
 406       if (bo->space_accounted == 0) {
 407           if (write_domain == RADEON_GEM_DOMAIN_VRAM)
 408               this_op_vram_write += bo->size;
 409           else if (write_domain == RADEON_GEM_DOMAIN_GTT)
 410               this_op_gart_write += bo->size;
 411           else
 412               this_op_read += bo->size;
 413           bos[i].new_accounted = (read_domains << 16) | write_domain;
 414       } else {
 415           uint16_t old_read, old_write;
 416
 417           old_read = bo->space_accounted >> 16;
 418           old_write = bo->space_accounted & 0xffff;
 419
 420           if (write_domain && (old_read & write_domain)) {
 421               bos[i].new_accounted = write_domain;
 422               /* moving from read to a write domain */
 423               if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
 424                   this_op_read -= bo->size;
 425                   this_op_vram_write += bo->size;
 426               } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
 427                   this_op_read -= bo->size;
 428                   this_op_gart_write += bo->size;
 429               }
 430           } else if (read_domains & old_write) {
 431               bos[i].new_accounted = bo->space_accounted & 0xffff;
 432           } else {
 433               /* rewrite the domains */
 434               if (write_domain != old_write)
 435                   fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
 436               if (read_domains != old_read)
 437                   fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
 438               return RADEON_CS_SPACE_FLUSH;
 439           }
 440       }
 441         }
 442
 443         if (this_op_read < 0)
 444                 this_op_read = 0;
 445
 446         /* check sizes - operation first */
 447         if ((this_op_read + this_op_gart_write > csm->gart_limit) ||
 448             (this_op_vram_write > csm->vram_limit)) {
 449             return RADEON_CS_SPACE_OP_TO_BIG;
 450         }
 451
 452         if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) ||
 453             ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) {
 454                 return RADEON_CS_SPACE_FLUSH;
 455         }
 456
 457         csm->gart_write_used += this_op_gart_write;
 458         csm->vram_write_used += this_op_vram_write;
 459         csm->read_used += this_op_read;
 460         /* commit */
 461         for (i = 0; i < num_bo; i++) {
 462                 bo = bos[i].bo;
 463                 bo->space_accounted = bos[i].new_accounted;
 464         }
 465
 466         return RADEON_CS_SPACE_OK;
 467 }
 468
 469 static struct radeon_cs_funcs  radeon_cs_legacy_funcs = {
 470     cs_create,
 471     cs_write_reloc,
 472     cs_begin,
 473     cs_end,
 474     cs_emit,
 475     cs_destroy,
 476     cs_erase,
 477     cs_need_flush,
 478     cs_print,
 479     cs_check_space
 480 };
 481
 482 struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx)
 483 {
 484     struct cs_manager_legacy *csm;
 485
 486     csm = (struct cs_manager_legacy*)
 487           calloc(1, sizeof(struct cs_manager_legacy));
 488     if (csm == NULL) {
 489         return NULL;
 490     }
 491     csm->base.funcs = &radeon_cs_legacy_funcs;
 492     csm->base.fd = ctx->dri.fd;
 493     csm->ctx = ctx;
 494     csm->pending_age = 1;
 495     return (struct radeon_cs_manager*)csm;
 496 }
 497
 498 void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm)
 499 {
 500     free(csm);
 501 }
 502