2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Jérôme Glisse
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 * Aapo Tahkola <aet@rasterburn.org>
29 * Nicolai Haehnle <prefect_@gmx.net>
30 * Jérôme Glisse <glisse@freedesktop.org>
35 #include "common_context.h"
36 #include "radeon_cs.h"
37 #include "radeon_cs_legacy.h"
38 #include "radeon_bo_legacy.h"
41 struct cs_manager_legacy
{
42 struct radeon_cs_manager base
;
43 struct radeon_context
*ctx
;
44 /* hack for scratch stuff */
46 uint32_t pending_count
;
49 struct cs_reloc_legacy
{
50 struct radeon_cs_reloc base
;
56 static struct radeon_cs
*cs_create(struct radeon_cs_manager
*csm
,
61 cs
= (struct radeon_cs
*)calloc(1, sizeof(struct radeon_cs
));
66 cs
->ndw
= (ndw
+ 0x3FF) & (~0x3FF);
67 cs
->packets
= (uint32_t*)malloc(4*cs
->ndw
);
68 if (cs
->packets
== NULL
) {
72 cs
->relocs_total_size
= 0;
76 int cs_write_dword(struct radeon_cs
*cs
, uint32_t dword
)
78 if (cs
->cdw
>= cs
->ndw
) {
80 tmp
= (cs
->cdw
+ 1 + 0x3FF) & (~0x3FF);
81 ptr
= (uint32_t*)realloc(cs
->packets
, 4 * tmp
);
88 cs
->packets
[cs
->cdw
++] = dword
;
95 static int cs_write_reloc(struct radeon_cs
*cs
,
98 uint32_t write_domain
,
101 struct cs_reloc_legacy
*relocs
;
104 relocs
= (struct cs_reloc_legacy
*)cs
->relocs
;
106 if ((read_domain
&& write_domain
) || (!read_domain
&& !write_domain
)) {
107 /* in one CS a bo can only be in read or write domain but not
108 * in read & write domain at the same sime
112 if (read_domain
== RADEON_GEM_DOMAIN_CPU
) {
115 if (write_domain
== RADEON_GEM_DOMAIN_CPU
) {
118 /* check if bo is already referenced */
119 for(i
= 0; i
< cs
->crelocs
; i
++) {
122 if (relocs
[i
].base
.bo
->handle
== bo
->handle
) {
123 /* Check domains must be in read or write. As we check already
124 * checked that in argument one of the read or write domain was
125 * set we only need to check that if previous reloc as the read
126 * domain set then the read_domain should also be set for this
129 if (relocs
[i
].base
.read_domain
&& !read_domain
) {
132 if (relocs
[i
].base
.write_domain
&& !write_domain
) {
135 relocs
[i
].base
.read_domain
|= read_domain
;
136 relocs
[i
].base
.write_domain
|= write_domain
;
138 relocs
[i
].cindices
++;
139 indices
= (uint32_t*)realloc(relocs
[i
].indices
,
140 relocs
[i
].cindices
* 4);
141 if (indices
== NULL
) {
142 relocs
[i
].cindices
-= 1;
145 relocs
[i
].indices
= indices
;
146 relocs
[i
].indices
[relocs
[i
].cindices
- 1] = cs
->cdw
- 1;
150 /* add bo to reloc */
151 relocs
= (struct cs_reloc_legacy
*)
153 sizeof(struct cs_reloc_legacy
) * (cs
->crelocs
+ 1));
154 if (relocs
== NULL
) {
158 relocs
[cs
->crelocs
].base
.bo
= bo
;
159 relocs
[cs
->crelocs
].base
.read_domain
= read_domain
;
160 relocs
[cs
->crelocs
].base
.write_domain
= write_domain
;
161 relocs
[cs
->crelocs
].base
.flags
= flags
;
162 relocs
[cs
->crelocs
].indices
= (uint32_t*)malloc(4);
163 if (relocs
[cs
->crelocs
].indices
== NULL
) {
166 relocs
[cs
->crelocs
].indices
[0] = cs
->cdw
- 1;
167 relocs
[cs
->crelocs
].cindices
= 1;
168 cs
->relocs_total_size
+= radeon_bo_legacy_relocs_size(bo
);
174 static int cs_begin(struct radeon_cs
*cs
,
181 fprintf(stderr
, "CS already in a section(%s,%s,%d)\n",
182 cs
->section_file
, cs
->section_func
, cs
->section_line
);
183 fprintf(stderr
, "CS can't start section(%s,%s,%d)\n",
188 cs
->section_ndw
= ndw
;
190 cs
->section_file
= file
;
191 cs
->section_func
= func
;
192 cs
->section_line
= line
;
196 static int cs_end(struct radeon_cs
*cs
,
203 fprintf(stderr
, "CS no section to end at (%s,%s,%d)\n",
208 if (cs
->section_ndw
!= cs
->section_cdw
) {
209 fprintf(stderr
, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
210 cs
->section_file
, cs
->section_func
, cs
->section_line
, cs
->section_ndw
, cs
->section_cdw
);
211 fprintf(stderr
, "CS section end at (%s,%s,%d)\n",
218 static int cs_process_relocs(struct radeon_cs
*cs
)
220 struct cs_manager_legacy
*csm
= (struct cs_manager_legacy
*)cs
->csm
;
221 struct cs_reloc_legacy
*relocs
;
224 csm
= (struct cs_manager_legacy
*)cs
->csm
;
225 relocs
= (struct cs_reloc_legacy
*)cs
->relocs
;
226 for (i
= 0; i
< cs
->crelocs
; i
++) {
227 for (j
= 0; j
< relocs
[i
].cindices
; j
++) {
228 uint32_t soffset
, eoffset
;
230 r
= radeon_bo_legacy_validate(relocs
[i
].base
.bo
,
233 fprintf(stderr
, "validated %p [0x%08X, 0x%08X]\n",
234 relocs
[i
].base
.bo
, soffset
, eoffset
);
237 cs
->packets
[relocs
[i
].indices
[j
]] += soffset
;
238 if (cs
->packets
[relocs
[i
].indices
[j
]] >= eoffset
) {
239 radeon_bo_debug(relocs
[i
].base
.bo
, 12);
240 fprintf(stderr
, "validated %p [0x%08X, 0x%08X]\n",
241 relocs
[i
].base
.bo
, soffset
, eoffset
);
242 fprintf(stderr
, "above end: %p 0x%08X 0x%08X\n",
244 cs
->packets
[relocs
[i
].indices
[j
]],
254 static int cs_set_age(struct radeon_cs
*cs
)
256 struct cs_manager_legacy
*csm
= (struct cs_manager_legacy
*)cs
->csm
;
257 struct cs_reloc_legacy
*relocs
;
260 relocs
= (struct cs_reloc_legacy
*)cs
->relocs
;
261 for (i
= 0; i
< cs
->crelocs
; i
++) {
262 radeon_bo_legacy_pending(relocs
[i
].base
.bo
, csm
->pending_age
);
263 radeon_bo_unref(relocs
[i
].base
.bo
);
268 static void dump_cmdbuf(struct radeon_cs
*cs
)
271 for (i
= 0; i
< cs
->cdw
; i
++){
272 fprintf(stderr
,"%x: %08x\n", i
, cs
->packets
[i
]);
276 static int cs_emit(struct radeon_cs
*cs
)
278 struct cs_manager_legacy
*csm
= (struct cs_manager_legacy
*)cs
->csm
;
279 drm_radeon_cmd_buffer_t cmd
;
280 drm_r300_cmd_header_t age
;
284 csm
->ctx
->vtbl
.emit_cs_header(cs
, csm
->ctx
);
287 /* append buffer age */
288 if (IS_R300_CLASS(csm
->ctx
->radeonScreen
)) {
289 age
.scratch
.cmd_type
= R300_CMD_SCRATCH
;
290 /* Scratch register 2 corresponds to what radeonGetAge polls */
291 csm
->pending_age
= 0;
292 csm
->pending_count
= 1;
293 ull
= (uint64_t) (intptr_t) &csm
->pending_age
;
295 age
.scratch
.n_bufs
= 1;
296 age
.scratch
.flags
= 0;
297 radeon_cs_write_dword(cs
, age
.u
);
298 radeon_cs_write_dword(cs
, ull
& 0xffffffff);
299 radeon_cs_write_dword(cs
, ull
>> 32);
300 radeon_cs_write_dword(cs
, 0);
303 r
= cs_process_relocs(cs
);
308 cmd
.buf
= (char *)cs
->packets
;
309 cmd
.bufsz
= cs
->cdw
* 4;
310 if (csm
->ctx
->state
.scissor
.enabled
) {
311 cmd
.nbox
= csm
->ctx
->state
.scissor
.numClipRects
;
312 cmd
.boxes
= (drm_clip_rect_t
*) csm
->ctx
->state
.scissor
.pClipRects
;
314 cmd
.nbox
= csm
->ctx
->numClipRects
;
315 cmd
.boxes
= (drm_clip_rect_t
*) csm
->ctx
->pClipRects
;
320 r
= drmCommandWrite(cs
->csm
->fd
, DRM_RADEON_CMDBUF
, &cmd
, sizeof(cmd
));
324 if (!IS_R300_CLASS(csm
->ctx
->radeonScreen
)) {
325 drm_radeon_irq_emit_t emit_cmd
;
326 emit_cmd
.irq_seq
= &csm
->pending_age
;
327 r
= drmCommandWrite(cs
->csm
->fd
, DRM_RADEON_IRQ_EMIT
, &emit_cmd
, sizeof(emit_cmd
));
336 static void inline cs_free_reloc(void *relocs_p
, int crelocs
)
338 struct cs_reloc_legacy
*relocs
= relocs_p
;
342 for (i
= 0; i
< crelocs
; i
++)
343 free(relocs
[i
].indices
);
346 static int cs_destroy(struct radeon_cs
*cs
)
348 cs_free_reloc(cs
->relocs
, cs
->crelocs
);
355 static int cs_erase(struct radeon_cs
*cs
)
357 cs_free_reloc(cs
->relocs
, cs
->crelocs
);
359 cs
->relocs_total_size
= 0;
367 static int cs_need_flush(struct radeon_cs
*cs
)
369 /* FIXME: we should get the texture heap size */
370 return (cs
->relocs_total_size
> (7*1024*1024));
373 static void cs_print(struct radeon_cs
*cs
, FILE *file
)
377 static struct radeon_cs_funcs radeon_cs_legacy_funcs
= {
390 struct radeon_cs_manager
*radeon_cs_manager_legacy_ctor(struct radeon_context
*ctx
)
392 struct cs_manager_legacy
*csm
;
394 csm
= (struct cs_manager_legacy
*)
395 calloc(1, sizeof(struct cs_manager_legacy
));
399 csm
->base
.funcs
= &radeon_cs_legacy_funcs
;
400 csm
->base
.fd
= ctx
->dri
.fd
;
402 csm
->pending_age
= 1;
403 return (struct radeon_cs_manager
*)csm
;
406 void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager
*csm
)