src/mesa/drivers/dri/radeon/radeon_cs_legacy.c

   1 /*
   2  * Copyright © 2008 Nicolai Haehnle
   3  * Copyright © 2008 Jérôme Glisse
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26 /*
  27  * Authors:
  28  *      Aapo Tahkola <aet@rasterburn.org>
  29  *      Nicolai Haehnle <prefect_@gmx.net>
  30  *      Jérôme Glisse <glisse@freedesktop.org>
  31  */
  32 #include <errno.h>
  33 #include "r300_reg.h"
  34 #include "r300_emit.h"
  35 #include "r300_cmdbuf.h"
  36 #include "radeon_cs.h"
  37 #include "radeon_cs_legacy.h"
  38 #include "radeon_bo_legacy.h"
  39 #include "radeon_context.h"
  40
  41 struct cs_manager_legacy {
  42     struct radeon_cs_manager    base;
  43     struct radeon_context       *ctx;
  44     /* hack for scratch stuff */
  45     uint32_t                    pending_age;
  46     uint32_t                    pending_count;
  47 };
  48
  49 struct cs_reloc_legacy {
  50     struct radeon_cs_reloc  base;
  51     uint32_t                cindices;
  52     uint32_t                *indices;
  53 };
  54
  55
  56 static struct radeon_cs *cs_create(struct radeon_cs_manager *csm,
  57                                    uint32_t ndw)
  58 {
  59     struct radeon_cs *cs;
  60
  61     cs = (struct radeon_cs*)calloc(1, sizeof(struct radeon_cs));
  62     if (cs == NULL) {
  63         return NULL;
  64     }
  65     cs->csm = csm;
  66     cs->ndw = (ndw + 0x3FF) & (~0x3FF);
  67     cs->packets = (uint32_t*)malloc(4*cs->ndw);
  68     if (cs->packets == NULL) {
  69         free(cs);
  70         return NULL;
  71     }
  72     cs->relocs_total_size = 0;
  73     return cs;
  74 }
  75
  76 static int cs_write_dword(struct radeon_cs *cs, uint32_t dword)
  77 {
  78     if (cs->cdw >= cs->ndw) {
  79         uint32_t tmp, *ptr;
  80         tmp = (cs->cdw + 1 + 0x3FF) & (~0x3FF);
  81         ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
  82         if (ptr == NULL) {
  83             return -ENOMEM;
  84         }
  85         cs->packets = ptr;
  86         cs->ndw = tmp;
  87     }
  88     cs->packets[cs->cdw++] = dword;
  89     if (cs->section) {
  90         cs->section_cdw++;
  91     }
  92     return 0;
  93 }
  94
  95 static int cs_write_reloc(struct radeon_cs *cs,
  96                           struct radeon_bo *bo,
  97                           uint32_t start_offset,
  98                           uint32_t end_offset,
  99                           uint32_t read_domain,
 100                           uint32_t write_domain,
 101                           uint32_t flags)
 102 {
 103     struct cs_reloc_legacy *relocs;
 104     int i;
 105
 106     relocs = (struct cs_reloc_legacy *)cs->relocs;
 107     /* check domains */
 108     if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
 109         /* in one CS a bo can only be in read or write domain but not
 110          * in read & write domain at the same sime
 111          */
 112         return -EINVAL;
 113     }
 114     if (read_domain == RADEON_GEM_DOMAIN_CPU) {
 115         return -EINVAL;
 116     }
 117     if (write_domain == RADEON_GEM_DOMAIN_CPU) {
 118         return -EINVAL;
 119     }
 120     /* check reloc window */
 121     if (end_offset > bo->size) {
 122         return -EINVAL;
 123     }
 124     if (start_offset > end_offset) {
 125         return -EINVAL;
 126     }
 127     /* check if bo is already referenced */
 128     for(i = 0; i < cs->crelocs; i++) {
 129         uint32_t *indices;
 130
 131         if (relocs[i].base.bo->handle == bo->handle) {
 132             /* update start and end offset */
 133             if (start_offset < relocs[i].base.start_offset) {
 134                 relocs[i].base.start_offset = start_offset;
 135             }
 136             if (end_offset > relocs[i].base.end_offset) {
 137                 relocs[i].base.end_offset = end_offset;
 138             }
 139             /* Check domains must be in read or write. As we check already
 140              * checked that in argument one of the read or write domain was
 141              * set we only need to check that if previous reloc as the read
 142              * domain set then the read_domain should also be set for this
 143              * new relocation.
 144              */
 145             if (relocs[i].base.read_domain && !read_domain) {
 146                 return -EINVAL;
 147             }
 148             if (relocs[i].base.write_domain && !write_domain) {
 149                 return -EINVAL;
 150             }
 151             relocs[i].base.read_domain |= read_domain;
 152             relocs[i].base.write_domain |= write_domain;
 153             /* save indice */
 154             relocs[i].cindices += 1;
 155             indices = (uint32_t*)realloc(relocs[i].indices,
 156                                          relocs[i].cindices * 4);
 157             if (indices == NULL) {
 158                 relocs[i].cindices -= 1;
 159                 return -ENOMEM;
 160             }
 161             relocs[i].indices = indices;
 162             relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1;
 163             return 0;
 164         }
 165     }
 166     /* add bo to reloc */
 167     relocs = (struct cs_reloc_legacy*)
 168              realloc(cs->relocs,
 169                      sizeof(struct cs_reloc_legacy) * (cs->crelocs + 1));
 170     if (relocs == NULL) {
 171         return -ENOMEM;
 172     }
 173     cs->relocs = relocs;
 174     relocs[cs->crelocs].base.bo = bo;
 175     relocs[cs->crelocs].base.start_offset = start_offset;
 176     relocs[cs->crelocs].base.end_offset = end_offset;
 177     relocs[cs->crelocs].base.read_domain = read_domain;
 178     relocs[cs->crelocs].base.write_domain = write_domain;
 179     relocs[cs->crelocs].base.flags = flags;
 180     relocs[cs->crelocs].indices = (uint32_t*)malloc(4);
 181     if (relocs[cs->crelocs].indices == NULL) {
 182         return -ENOMEM;
 183     }
 184     relocs[cs->crelocs].indices[0] = cs->cdw - 1;
 185     relocs[cs->crelocs].cindices = 1;
 186     cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo);
 187     cs->crelocs++;
 188     radeon_bo_ref(bo);
 189     return 0;
 190 }
 191
 192 static int cs_begin(struct radeon_cs *cs,
 193                     uint32_t ndw,
 194                     const char *file,
 195                     const char *func,
 196                     int line)
 197 {
 198     if (cs->section) {
 199         fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
 200                 cs->section_file, cs->section_func, cs->section_line);
 201         fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
 202                 file, func, line);
 203         return -EPIPE;
 204     }
 205     cs->section = 1;
 206     cs->section_ndw = ndw;
 207     cs->section_cdw = 0;
 208     cs->section_file = file;
 209     cs->section_func = func;
 210     cs->section_line = line;
 211     return 0;
 212 }
 213
 214 static int cs_end(struct radeon_cs *cs,
 215                   const char *file,
 216                   const char *func,
 217                   int line)
 218
 219 {
 220     if (!cs->section) {
 221         fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
 222                 file, func, line);
 223         return -EPIPE;
 224     }
 225     cs->section = 0;
 226     if (cs->section_ndw != cs->section_cdw) {
 227         fprintf(stderr, "CS section size missmatch start at (%s,%s,%d)\n",
 228                 cs->section_file, cs->section_func, cs->section_line);
 229         fprintf(stderr, "CS section end at (%s,%s,%d)\n",
 230                 file, func, line);
 231         return -EPIPE;
 232     }
 233     return 0;
 234 }
 235
 236 static int cs_process_relocs(struct radeon_cs *cs)
 237 {
 238     struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
 239     struct cs_reloc_legacy *relocs;
 240     int i, j, r;
 241
 242     if (!IS_R300_CLASS(csm->ctx->radeonScreen)) {
 243         /* FIXME: r300 only right now */
 244         return -EINVAL;
 245     }
 246     csm = (struct cs_manager_legacy*)cs->csm;
 247     relocs = (struct cs_reloc_legacy *)cs->relocs;
 248     for (i = 0; i < cs->crelocs; i++) {
 249         for (j = 0; j < relocs[i].cindices; j++) {
 250             uint32_t soffset, eoffset;
 251
 252             soffset = relocs[i].base.start_offset;
 253             eoffset = relocs[i].base.end_offset;
 254             r = radeon_bo_legacy_validate(relocs[i].base.bo,
 255                                            &soffset, &eoffset);
 256             if (r) {
 257                 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
 258                         relocs[i].base.bo, soffset, eoffset);
 259                 return r;
 260             }
 261             cs->packets[relocs[i].indices[j]] += soffset;
 262             if (cs->packets[relocs[i].indices[j]] >= eoffset) {
 263                 radeon_bo_debug(relocs[i].base.bo, 12);
 264                 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
 265                         relocs[i].base.bo, soffset, eoffset);
 266                 fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
 267                         relocs[i].base.bo,
 268                         cs->packets[relocs[i].indices[j]],
 269                         eoffset);
 270                 exit(0);
 271                 return -EINVAL;
 272             }
 273         }
 274     }
 275     return 0;
 276 }
 277
 278 static int cs_set_age(struct radeon_cs *cs)
 279 {
 280     struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
 281     struct cs_reloc_legacy *relocs;
 282     int i;
 283
 284     relocs = (struct cs_reloc_legacy *)cs->relocs;
 285     for (i = 0; i < cs->crelocs; i++) {
 286         radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age);
 287         radeon_bo_unref(relocs[i].base.bo);
 288     }
 289     return 0;
 290 }
 291
 292 static int cs_emit(struct radeon_cs *cs)
 293 {
 294     struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
 295     drm_radeon_cmd_buffer_t cmd;
 296     drm_r300_cmd_header_t age;
 297     uint64_t ull;
 298     int r;
 299
 300     /* please flush pipe do all pending work */
 301     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 302                                   R300_SC_SCREENDOOR, 1));
 303     cs_write_dword(cs, 0x0);
 304     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 305                                   R300_SC_SCREENDOOR, 1));
 306     cs_write_dword(cs, 0x00FFFFFF);
 307     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 308                                   R300_SC_HYPERZ, 1));
 309     cs_write_dword(cs, 0x0);
 310     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 311                                   R300_US_CONFIG, 1));
 312     cs_write_dword(cs, 0x0);
 313     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 314                                   R300_ZB_CNTL, 1));
 315     cs_write_dword(cs, 0x0);
 316     cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, R300_WAIT_3D));
 317     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 318                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 319     cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 320     cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
 321                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 322     cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 323     cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen,
 324                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 325
 326     /* append buffer age */
 327     age.scratch.cmd_type = R300_CMD_SCRATCH;
 328     /* Scratch register 2 corresponds to what radeonGetAge polls */
 329     csm->pending_age = 0;
 330     csm->pending_count = 1;
 331     ull = (uint64_t) (intptr_t) &csm->pending_age;
 332     age.scratch.reg = 2;
 333     age.scratch.n_bufs = 1;
 334     age.scratch.flags = 0;
 335     radeon_cs_write_dword(cs, age.u);
 336     radeon_cs_write_dword(cs, ull & 0xffffffff);
 337     radeon_cs_write_dword(cs, ull >> 32);
 338     radeon_cs_write_dword(cs, 0);
 339
 340     r = cs_process_relocs(cs);
 341     if (r) {
 342         return 0;
 343     }
 344
 345     cmd.buf = (char *)cs->packets;
 346     cmd.bufsz = cs->cdw * 4;
 347     if (csm->ctx->state.scissor.enabled) {
 348         cmd.nbox = csm->ctx->state.scissor.numClipRects;
 349         cmd.boxes = (drm_clip_rect_t *) csm->ctx->state.scissor.pClipRects;
 350     } else {
 351         cmd.nbox = csm->ctx->numClipRects;
 352         cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects;
 353     }
 354
 355     r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
 356     if (r) {
 357         return r;
 358     }
 359     cs_set_age(cs);
 360     return 0;
 361 }
 362
 363 static int cs_destroy(struct radeon_cs *cs)
 364 {
 365     free(cs->relocs);
 366     free(cs->packets);
 367     free(cs);
 368     return 0;
 369 }
 370
 371 static int cs_erase(struct radeon_cs *cs)
 372 {
 373     free(cs->relocs);
 374     cs->relocs_total_size = 0;
 375     cs->relocs = NULL;
 376     cs->crelocs = 0;
 377     cs->cdw = 0;
 378     cs->section = 0;
 379     return 0;
 380 }
 381
 382 static int cs_need_flush(struct radeon_cs *cs)
 383 {
 384     /* FIXME: we should get the texture heap size */
 385     return (cs->relocs_total_size > (7*1024*1024));
 386 }
 387
 388 static struct radeon_cs_funcs  radeon_cs_legacy_funcs = {
 389     cs_create,
 390     cs_write_dword,
 391     cs_write_reloc,
 392     cs_begin,
 393     cs_end,
 394     cs_emit,
 395     cs_destroy,
 396     cs_erase,
 397     cs_need_flush
 398 };
 399
 400 struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx)
 401 {
 402     struct cs_manager_legacy *csm;
 403
 404     csm = (struct cs_manager_legacy*)
 405           calloc(1, sizeof(struct cs_manager_legacy));
 406     if (csm == NULL) {
 407         return NULL;
 408     }
 409     csm->base.funcs = &radeon_cs_legacy_funcs;
 410     csm->base.fd = ctx->dri.fd;
 411     csm->ctx = ctx;
 412     csm->pending_age = 1;
 413     return (struct radeon_cs_manager*)csm;
 414 }
 415
 416 void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm)
 417 {
 418     free(csm);
 419 }