1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
40 #include "main/attrib.h"
41 #include "main/bufferobj.h"
42 #include "swrast/swrast.h"
44 #include "main/glheader.h"
45 #include "main/imports.h"
46 #include "main/simple_list.h"
47 #include "swrast/swrast.h"
49 #include "radeon_context.h"
50 #include "radeon_common.h"
51 #include "radeon_ioctl.h"
53 #define STANDALONE_MMIO
57 #define RADEON_TIMEOUT 512
58 #define RADEON_IDLE_RETRY 16
61 /* =============================================================
62 * Kernel command buffer handling
65 /* The state atoms will be emitted in the order they appear in the atom list,
66 * so this step is important.
68 void radeonSetUpAtomList( r100ContextPtr rmesa
)
70 int i
, mtu
= rmesa
->radeon
.glCtx
->Const
.MaxTextureUnits
;
72 make_empty_list(&rmesa
->radeon
.hw
.atomlist
);
73 rmesa
->radeon
.hw
.atomlist
.name
= "atom-list";
75 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ctx
);
76 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.set
);
77 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lin
);
78 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msk
);
79 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpt
);
80 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tcl
);
81 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msc
);
82 for (i
= 0; i
< mtu
; ++i
) {
83 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tex
[i
]);
84 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.txr
[i
]);
85 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.cube
[i
]);
87 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.zbs
);
88 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mtl
);
89 for (i
= 0; i
< 3 + mtu
; ++i
)
90 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mat
[i
]);
91 for (i
= 0; i
< 8; ++i
)
92 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lit
[i
]);
93 for (i
= 0; i
< 6; ++i
)
94 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ucp
[i
]);
95 if (rmesa
->radeon
.radeonScreen
->kernel_mm
)
96 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.stp
);
97 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.eye
);
98 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.grd
);
99 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.fog
);
100 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.glt
);
103 static void radeonEmitScissor(r100ContextPtr rmesa
)
105 BATCH_LOCALS(&rmesa
->radeon
);
106 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
109 if (rmesa
->radeon
.state
.scissor
.enabled
) {
111 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL
, 0));
112 OUT_BATCH(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] | RADEON_SCISSOR_ENABLE
);
113 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT
, 0));
114 OUT_BATCH((rmesa
->radeon
.state
.scissor
.rect
.y1
<< 16) |
115 rmesa
->radeon
.state
.scissor
.rect
.x1
);
116 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT
, 0));
117 OUT_BATCH(((rmesa
->radeon
.state
.scissor
.rect
.y2
) << 16) |
118 (rmesa
->radeon
.state
.scissor
.rect
.x2
));
122 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL
, 0));
123 OUT_BATCH(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & ~RADEON_SCISSOR_ENABLE
);
128 /* Fire a section of the retained (indexed_verts) buffer as a regular
131 extern void radeonEmitVbufPrim( r100ContextPtr rmesa
,
132 GLuint vertex_format
,
136 BATCH_LOCALS(&rmesa
->radeon
);
138 assert(!(primitive
& RADEON_CP_VC_CNTL_PRIM_WALK_IND
));
140 radeonEmitState(&rmesa
->radeon
);
141 radeonEmitScissor(rmesa
);
143 #if RADEON_OLD_PACKETS
145 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM
, 3);
146 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
147 OUT_BATCH_RELOC(rmesa
->ioctl
.vertex_offset
, rmesa
->ioctl
.bo
, rmesa
->ioctl
.vertex_offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
149 OUT_BATCH(rmesa
->ioctl
.vertex_offset
);
152 OUT_BATCH(vertex_nr
);
153 OUT_BATCH(vertex_format
);
154 OUT_BATCH(primitive
| RADEON_CP_VC_CNTL_PRIM_WALK_LIST
|
155 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
156 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
157 (vertex_nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
));
159 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
160 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
162 RADEON_GEM_DOMAIN_GTT
,
170 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF
, 1);
171 OUT_BATCH(vertex_format
);
172 OUT_BATCH(primitive
|
173 RADEON_CP_VC_CNTL_PRIM_WALK_LIST
|
174 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
175 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
176 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
177 (vertex_nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
));
182 void radeonFlushElts( GLcontext
*ctx
)
184 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
185 BATCH_LOCALS(&rmesa
->radeon
);
187 uint32_t *cmd
= (uint32_t *)(rmesa
->radeon
.cmdbuf
.cs
->packets
+ rmesa
->tcl
.elt_cmd_start
);
188 int dwords
= (rmesa
->radeon
.cmdbuf
.cs
->section_ndw
- rmesa
->radeon
.cmdbuf
.cs
->section_cdw
);
190 if (RADEON_DEBUG
& RADEON_IOCTL
)
191 fprintf(stderr
, "%s\n", __FUNCTION__
);
193 assert( rmesa
->radeon
.dma
.flush
== radeonFlushElts
);
194 rmesa
->radeon
.dma
.flush
= NULL
;
196 nr
= rmesa
->tcl
.elt_used
;
198 #if RADEON_OLD_PACKETS
199 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
204 #if RADEON_OLD_PACKETS
205 cmd
[1] |= (dwords
+ 3) << 16;
206 cmd
[5] |= nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
;
208 cmd
[1] |= (dwords
+ 2) << 16;
209 cmd
[3] |= nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
;
212 rmesa
->radeon
.cmdbuf
.cs
->cdw
+= dwords
;
213 rmesa
->radeon
.cmdbuf
.cs
->section_cdw
+= dwords
;
215 #if RADEON_OLD_PACKETS
216 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
217 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
219 RADEON_GEM_DOMAIN_GTT
,
226 if (RADEON_DEBUG
& RADEON_SYNC
) {
227 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
228 radeonFinish( rmesa
->radeon
.glCtx
);
233 GLushort
*radeonAllocEltsOpenEnded( r100ContextPtr rmesa
,
234 GLuint vertex_format
,
240 BATCH_LOCALS(&rmesa
->radeon
);
242 if (RADEON_DEBUG
& RADEON_IOCTL
)
243 fprintf(stderr
, "%s %d prim %x\n", __FUNCTION__
, min_nr
, primitive
);
245 assert((primitive
& RADEON_CP_VC_CNTL_PRIM_WALK_IND
));
247 radeonEmitState(&rmesa
->radeon
);
248 radeonEmitScissor(rmesa
);
250 rmesa
->tcl
.elt_cmd_start
= rmesa
->radeon
.cmdbuf
.cs
->cdw
;
252 /* round up min_nr to align the state */
253 align_min_nr
= (min_nr
+ 1) & ~1;
255 #if RADEON_OLD_PACKETS
256 BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr
)/4);
257 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM
, 0);
258 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
259 OUT_BATCH_RELOC(rmesa
->ioctl
.vertex_offset
, rmesa
->ioctl
.bo
, rmesa
->ioctl
.vertex_offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
261 OUT_BATCH(rmesa
->ioctl
.vertex_offset
);
263 OUT_BATCH(rmesa
->ioctl
.vertex_max
);
264 OUT_BATCH(vertex_format
);
265 OUT_BATCH(primitive
|
266 RADEON_CP_VC_CNTL_PRIM_WALK_IND
|
267 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
268 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
);
270 BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr
)/4);
271 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX
, 0);
272 OUT_BATCH(vertex_format
);
273 OUT_BATCH(primitive
|
274 RADEON_CP_VC_CNTL_PRIM_WALK_IND
|
275 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
276 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
277 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
);
281 rmesa
->tcl
.elt_cmd_offset
= rmesa
->radeon
.cmdbuf
.cs
->cdw
;
282 rmesa
->tcl
.elt_used
= min_nr
;
284 retval
= (GLushort
*)(rmesa
->radeon
.cmdbuf
.cs
->packets
+ rmesa
->tcl
.elt_cmd_offset
);
286 if (RADEON_DEBUG
& RADEON_RENDER
)
287 fprintf(stderr
, "%s: header prim %x \n",
288 __FUNCTION__
, primitive
);
290 assert(!rmesa
->radeon
.dma
.flush
);
291 rmesa
->radeon
.glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
292 rmesa
->radeon
.dma
.flush
= radeonFlushElts
;
297 void radeonEmitVertexAOS( r100ContextPtr rmesa
,
299 struct radeon_bo
*bo
,
302 #if RADEON_OLD_PACKETS
303 rmesa
->ioctl
.vertex_offset
= offset
;
304 rmesa
->ioctl
.bo
= bo
;
306 BATCH_LOCALS(&rmesa
->radeon
);
308 if (RADEON_DEBUG
& (RADEON_PRIMS
|DEBUG_IOCTL
))
309 fprintf(stderr
, "%s: vertex_size 0x%x offset 0x%x \n",
310 __FUNCTION__
, vertex_size
, offset
);
313 OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR
, 2);
315 OUT_BATCH(vertex_size
| (vertex_size
<< 8));
316 OUT_BATCH_RELOC(offset
, bo
, offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
323 void radeonEmitAOS( r100ContextPtr rmesa
,
327 #if RADEON_OLD_PACKETS
329 rmesa
->ioctl
.bo
= rmesa
->radeon
.tcl
.aos
[0].bo
;
330 rmesa
->ioctl
.vertex_offset
=
331 (rmesa
->radeon
.tcl
.aos
[0].offset
+ offset
* rmesa
->radeon
.tcl
.aos
[0].stride
* 4);
332 rmesa
->ioctl
.vertex_max
= rmesa
->radeon
.tcl
.aos
[0].count
;
334 BATCH_LOCALS(&rmesa
->radeon
);
336 // int sz = AOS_BUFSZ(nr);
337 int sz
= 1 + (nr
>> 1) * 3 + (nr
& 1) * 2;
340 if (RADEON_DEBUG
& RADEON_IOCTL
)
341 fprintf(stderr
, "%s\n", __FUNCTION__
);
343 BEGIN_BATCH(sz
+2+(nr
* 2));
344 OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR
, sz
- 1);
347 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
348 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
349 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
350 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
351 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
352 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
354 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
355 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
356 OUT_BATCH_RELOC(voffset
,
357 rmesa
->radeon
.tcl
.aos
[i
].bo
,
359 RADEON_GEM_DOMAIN_GTT
,
361 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
362 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
363 OUT_BATCH_RELOC(voffset
,
364 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
366 RADEON_GEM_DOMAIN_GTT
,
371 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
372 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
373 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
374 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
375 OUT_BATCH_RELOC(voffset
,
376 rmesa
->radeon
.tcl
.aos
[nr
- 1].bo
,
378 RADEON_GEM_DOMAIN_GTT
,
382 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
383 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
384 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
385 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
386 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
388 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
389 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
391 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
392 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
397 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
398 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
399 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
400 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
403 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
404 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
405 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
406 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
407 rmesa
->radeon
.tcl
.aos
[i
+0].bo
,
408 RADEON_GEM_DOMAIN_GTT
,
410 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
411 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
412 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
413 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
414 RADEON_GEM_DOMAIN_GTT
,
418 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
419 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
420 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
421 rmesa
->radeon
.tcl
.aos
[nr
-1].bo
,
422 RADEON_GEM_DOMAIN_GTT
,
431 /* ================================================================
434 #define RADEON_MAX_CLEARS 256
436 static void radeonKernelClear(GLcontext
*ctx
, GLuint flags
)
438 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
439 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
440 drm_radeon_sarea_t
*sarea
= rmesa
->radeon
.sarea
;
443 GLint cx
, cy
, cw
, ch
;
445 radeonEmitState(&rmesa
->radeon
);
447 LOCK_HARDWARE( &rmesa
->radeon
);
449 /* compute region after locking: */
450 cx
= ctx
->DrawBuffer
->_Xmin
;
451 cy
= ctx
->DrawBuffer
->_Ymin
;
452 cw
= ctx
->DrawBuffer
->_Xmax
- cx
;
453 ch
= ctx
->DrawBuffer
->_Ymax
- cy
;
455 /* Flip top to bottom */
457 cy
= dPriv
->y
+ dPriv
->h
- cy
- ch
;
459 /* Throttle the number of clear ioctls we do.
463 drm_radeon_getparam_t gp
;
465 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
466 gp
.value
= (int *)&clear
;
467 ret
= drmCommandWriteRead( rmesa
->radeon
.dri
.fd
,
468 DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
) );
471 fprintf( stderr
, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__
, ret
);
475 if ( sarea
->last_clear
- clear
<= RADEON_MAX_CLEARS
) {
479 if ( rmesa
->radeon
.do_usleeps
) {
480 UNLOCK_HARDWARE( &rmesa
->radeon
);
482 LOCK_HARDWARE( &rmesa
->radeon
);
486 /* Send current state to the hardware */
487 rcommonFlushCmdBufLocked( &rmesa
->radeon
, __FUNCTION__
);
489 for ( i
= 0 ; i
< dPriv
->numClipRects
; ) {
490 GLint nr
= MIN2( i
+ RADEON_NR_SAREA_CLIPRECTS
, dPriv
->numClipRects
);
491 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
492 drm_clip_rect_t
*b
= rmesa
->radeon
.sarea
->boxes
;
493 drm_radeon_clear_t clear
;
494 drm_radeon_clear_rect_t depth_boxes
[RADEON_NR_SAREA_CLIPRECTS
];
497 if (cw
!= dPriv
->w
|| ch
!= dPriv
->h
) {
498 /* clear subregion */
499 for ( ; i
< nr
; i
++ ) {
502 GLint w
= box
[i
].x2
- x
;
503 GLint h
= box
[i
].y2
- y
;
505 if ( x
< cx
) w
-= cx
- x
, x
= cx
;
506 if ( y
< cy
) h
-= cy
- y
, y
= cy
;
507 if ( x
+ w
> cx
+ cw
) w
= cx
+ cw
- x
;
508 if ( y
+ h
> cy
+ ch
) h
= cy
+ ch
- y
;
509 if ( w
<= 0 ) continue;
510 if ( h
<= 0 ) continue;
520 /* clear whole buffer */
521 for ( ; i
< nr
; i
++ ) {
527 rmesa
->radeon
.sarea
->nbox
= n
;
530 clear
.clear_color
= rmesa
->radeon
.state
.color
.clear
;
531 clear
.clear_depth
= rmesa
->radeon
.state
.depth
.clear
;
532 clear
.color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
533 clear
.depth_mask
= rmesa
->radeon
.state
.stencil
.clear
;
534 clear
.depth_boxes
= depth_boxes
;
537 b
= rmesa
->radeon
.sarea
->boxes
;
538 for ( ; n
>= 0 ; n
-- ) {
539 depth_boxes
[n
].f
[CLEAR_X1
] = (float)b
[n
].x1
;
540 depth_boxes
[n
].f
[CLEAR_Y1
] = (float)b
[n
].y1
;
541 depth_boxes
[n
].f
[CLEAR_X2
] = (float)b
[n
].x2
;
542 depth_boxes
[n
].f
[CLEAR_Y2
] = (float)b
[n
].y2
;
543 depth_boxes
[n
].f
[CLEAR_DEPTH
] =
544 (float)rmesa
->radeon
.state
.depth
.clear
;
547 ret
= drmCommandWrite( rmesa
->radeon
.dri
.fd
, DRM_RADEON_CLEAR
,
548 &clear
, sizeof(drm_radeon_clear_t
));
551 UNLOCK_HARDWARE( &rmesa
->radeon
);
552 fprintf( stderr
, "DRM_RADEON_CLEAR: return = %d\n", ret
);
556 UNLOCK_HARDWARE( &rmesa
->radeon
);
559 static void radeonClear( GLcontext
*ctx
, GLbitfield mask
)
561 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
562 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
564 GLuint color_mask
= 0;
565 GLuint orig_mask
= mask
;
567 if (mask
& (BUFFER_BIT_FRONT_LEFT
| BUFFER_BIT_FRONT_RIGHT
)) {
568 rmesa
->radeon
.front_buffer_dirty
= GL_TRUE
;
571 if ( RADEON_DEBUG
& RADEON_IOCTL
) {
572 fprintf( stderr
, "radeonClear\n");
576 LOCK_HARDWARE( &rmesa
->radeon
);
577 UNLOCK_HARDWARE( &rmesa
->radeon
);
578 if ( dPriv
->numClipRects
== 0 )
582 radeon_firevertices(&rmesa
->radeon
);
584 if ( mask
& BUFFER_BIT_FRONT_LEFT
) {
585 flags
|= RADEON_FRONT
;
586 color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
587 mask
&= ~BUFFER_BIT_FRONT_LEFT
;
590 if ( mask
& BUFFER_BIT_BACK_LEFT
) {
591 flags
|= RADEON_BACK
;
592 color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
593 mask
&= ~BUFFER_BIT_BACK_LEFT
;
596 if ( mask
& BUFFER_BIT_DEPTH
) {
597 flags
|= RADEON_DEPTH
;
598 mask
&= ~BUFFER_BIT_DEPTH
;
601 if ( (mask
& BUFFER_BIT_STENCIL
) ) {
602 flags
|= RADEON_STENCIL
;
603 mask
&= ~BUFFER_BIT_STENCIL
;
607 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
608 fprintf(stderr
, "%s: swrast clear, mask: %x\n", __FUNCTION__
, mask
);
609 _swrast_Clear( ctx
, mask
);
615 if (rmesa
->using_hyperz
) {
616 flags
|= RADEON_USE_COMP_ZBUF
;
617 /* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
618 flags |= RADEON_USE_HIERZ; */
619 if (((flags
& RADEON_DEPTH
) && (flags
& RADEON_STENCIL
) &&
620 ((rmesa
->radeon
.state
.stencil
.clear
& RADEON_STENCIL_WRITE_MASK
) == RADEON_STENCIL_WRITE_MASK
))) {
621 flags
|= RADEON_CLEAR_FASTZ
;
625 if (rmesa
->radeon
.radeonScreen
->kernel_mm
)
626 radeonUserClear(ctx
, orig_mask
);
628 radeonKernelClear(ctx
, flags
);
629 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
633 void radeonInitIoctlFuncs( GLcontext
*ctx
)
635 ctx
->Driver
.Clear
= radeonClear
;
636 ctx
->Driver
.Finish
= radeonFinish
;
637 ctx
->Driver
.Flush
= radeonFlush
;