src/mesa/drivers/dri/radeon/radeon_ioctl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include <sched.h>
  38 #include <errno.h>
  39
  40 #include "main/glheader.h"
  41 #include "main/imports.h"
  42 #include "main/simple_list.h"
  43 #include "swrast/swrast.h"
  44
  45 #include "radeon_context.h"
  46 #include "radeon_common.h"
  47 #include "radeon_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "radeon_tcl.h"
  50 #include "radeon_sanity.h"
  51
  52 #define STANDALONE_MMIO
  53 #include "radeon_macros.h"  /* for INREG() */
  54
  55 #include "drirenderbuffer.h"
  56 #include "vblank.h"
  57
  58 #define RADEON_TIMEOUT             512
  59 #define RADEON_IDLE_RETRY           16
  60
  61
  62 /* =============================================================
  63  * Kernel command buffer handling
  64  */
  65
  66 /* The state atoms will be emitted in the order they appear in the atom list,
  67  * so this step is important.
  68  */
  69 void radeonSetUpAtomList( r100ContextPtr rmesa )
  70 {
  71    int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits;
  72
  73    make_empty_list(&rmesa->radeon.hw.atomlist);
  74    rmesa->radeon.hw.atomlist.name = "atom-list";
  75
  76    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx);
  77    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set);
  78    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin);
  79    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk);
  80    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt);
  81    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
  82    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc);
  83    for (i = 0; i < mtu; ++i) {
  84        insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]);
  85        insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]);
  86        insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i]);
  87    }
  88    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs);
  89    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mtl);
  90    for (i = 0; i < 3 + mtu; ++i)
  91       insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i]);
  92    for (i = 0; i < 8; ++i)
  93       insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
  94    for (i = 0; i < 6; ++i)
  95       insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
  96    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
  97    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
  98    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
  99    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);
 100 }
 101
 102 /* Fire a section of the retained (indexed_verts) buffer as a regular
 103  * primtive.
 104  */
 105 extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
 106                                 GLuint vertex_format,
 107                                 GLuint primitive,
 108                                 GLuint vertex_nr )
 109 {
 110    BATCH_LOCALS(&rmesa->radeon);
 111
 112    assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 113
 114    radeonEmitState(&rmesa->radeon);
 115
 116 #if RADEON_OLD_PACKETS
 117    BEGIN_BATCH(8);
 118    OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3);
 119    OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 120    OUT_BATCH(vertex_nr);
 121    OUT_BATCH(vertex_format);
 122    OUT_BATCH(primitive |  RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
 123              RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
 124              RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
 125              (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT));
 126    END_BATCH();
 127
 128 #else
 129    BEGIN_BATCH(4);
 130    OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 1);
 131    OUT_BATCH(vertex_format);
 132    OUT_BATCH(primitive |
 133              RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
 134              RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
 135              RADEON_CP_VC_CNTL_MAOS_ENABLE |
 136              RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
 137              (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT));
 138    END_BATCH();
 139 #endif
 140 }
 141
 142 void radeonFlushElts( GLcontext *ctx )
 143 {
 144    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 145    BATCH_LOCALS(&rmesa->radeon);
 146    int nr;
 147    uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
 148    int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
 149
 150    if (RADEON_DEBUG & DEBUG_IOCTL)
 151       fprintf(stderr, "%s\n", __FUNCTION__);
 152
 153    assert( rmesa->radeon.dma.flush == radeonFlushElts );
 154    rmesa->radeon.dma.flush = NULL;
 155
 156    nr = rmesa->tcl.elt_used;
 157
 158    rmesa->radeon.cmdbuf.cs->cdw += dwords;
 159
 160 #if RADEON_OLD_PACKETS
 161    cmd[1] |= (dwords + 3) << 16;
 162    cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
 163 #else
 164    cmd[1] |= (dwords + 2) << 16;
 165    cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
 166 #endif
 167
 168    rmesa->radeon.cmdbuf.cs->section_cdw += dwords;
 169    END_BATCH();
 170
 171    if (RADEON_DEBUG & DEBUG_SYNC) {
 172       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
 173       radeonFinish( rmesa->radeon.glCtx );
 174    }
 175
 176 }
 177
 178 GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
 179                                     GLuint vertex_format,
 180                                     GLuint primitive,
 181                                     GLuint min_nr )
 182 {
 183    GLushort *retval;
 184    int align_min_nr;
 185    BATCH_LOCALS(&rmesa->radeon);
 186
 187    if (RADEON_DEBUG & DEBUG_IOCTL)
 188       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 189
 190    assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 191
 192    radeonEmitState(&rmesa->radeon);
 193
 194    rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
 195
 196    /* round up min_nr to align the state */
 197    align_min_nr = (min_nr + 1) & ~1;
 198
 199 #if RADEON_OLD_PACKETS
 200    BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4);
 201    OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0);
 202    OUT_BATCH_RELOC(rmesa->ioctl.vertex_offset, rmesa->ioctl.bo, rmesa->ioctl.vertex_offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 203    OUT_BATCH(0xffff);
 204    OUT_BATCH(vertex_format);
 205    OUT_BATCH(primitive |
 206              RADEON_CP_VC_CNTL_PRIM_WALK_IND |
 207              RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
 208              RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
 209
 210 #else
 211    BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4);
 212    OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0);
 213    OUT_BATCH(vertex_format);
 214    OUT_BATCH(primitive |
 215              RADEON_CP_VC_CNTL_PRIM_WALK_IND |
 216              RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
 217              RADEON_CP_VC_CNTL_MAOS_ENABLE |
 218              RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
 219 #endif
 220
 221
 222    rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw;
 223    rmesa->tcl.elt_used = min_nr;
 224
 225    retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
 226
 227    if (RADEON_DEBUG & DEBUG_PRIMS)
 228       fprintf(stderr, "%s: header prim %x \n",
 229               __FUNCTION__, primitive);
 230
 231    assert(!rmesa->radeon.dma.flush);
 232    rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 233    rmesa->radeon.dma.flush = radeonFlushElts;
 234
 235    return retval;
 236 }
 237
 238 void radeonEmitVertexAOS( r100ContextPtr rmesa,
 239                           GLuint vertex_size,
 240                           struct radeon_bo *bo,
 241                           GLuint offset )
 242 {
 243 #if RADEON_OLD_PACKETS
 244    rmesa->ioctl.vertex_offset = offset;
 245    rmesa->ioctl.bo = bo;
 246 #else
 247    BATCH_LOCALS(&rmesa->radeon);
 248
 249    if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
 250       fprintf(stderr, "%s:  vertex_size 0x%x offset 0x%x \n",
 251               __FUNCTION__, vertex_size, offset);
 252
 253    BEGIN_BATCH(7);
 254    OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2);
 255    OUT_BATCH(1);
 256    OUT_BATCH(vertex_size | (vertex_size << 8));
 257    OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
 258    END_BATCH();
 259
 260 #endif
 261 }
 262
 263
 264 void radeonEmitAOS( r100ContextPtr rmesa,
 265                     GLuint nr,
 266                     GLuint offset )
 267 {
 268 #if RADEON_OLD_PACKETS
 269    assert( nr == 1 );
 270    rmesa->ioctl.bo = rmesa->tcl.aos[0].bo;
 271    rmesa->ioctl.vertex_offset =
 272      (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4);
 273 #else
 274    BATCH_LOCALS(&rmesa->radeon);
 275    uint32_t voffset;
 276    //   int sz = AOS_BUFSZ(nr);
 277    int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
 278    int i;
 279
 280    if (RADEON_DEBUG & DEBUG_IOCTL)
 281       fprintf(stderr, "%s\n", __FUNCTION__);
 282
 283    BEGIN_BATCH(sz+2+(nr * 2));
 284    OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1);
 285    OUT_BATCH(nr);
 286
 287    if (!rmesa->radeon.radeonScreen->kernel_mm) {
 288       for (i = 0; i + 1 < nr; i += 2) {
 289          OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
 290                    (rmesa->tcl.aos[i].stride << 8) |
 291                    (rmesa->tcl.aos[i + 1].components << 16) |
 292                    (rmesa->tcl.aos[i + 1].stride << 24));
 293
 294          voffset =  rmesa->tcl.aos[i + 0].offset +
 295             offset * 4 * rmesa->tcl.aos[i + 0].stride;
 296          OUT_BATCH_RELOC(voffset,
 297                          rmesa->tcl.aos[i].bo,
 298                          voffset,
 299                          RADEON_GEM_DOMAIN_GTT,
 300                          0, 0);
 301          voffset =  rmesa->tcl.aos[i + 1].offset +
 302             offset * 4 * rmesa->tcl.aos[i + 1].stride;
 303          OUT_BATCH_RELOC(voffset,
 304                          rmesa->tcl.aos[i+1].bo,
 305                          voffset,
 306                          RADEON_GEM_DOMAIN_GTT,
 307                          0, 0);
 308       }
 309
 310       if (nr & 1) {
 311          OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
 312                    (rmesa->tcl.aos[nr - 1].stride << 8));
 313          voffset =  rmesa->tcl.aos[nr - 1].offset +
 314             offset * 4 * rmesa->tcl.aos[nr - 1].stride;
 315          OUT_BATCH_RELOC(voffset,
 316                          rmesa->tcl.aos[nr - 1].bo,
 317                          voffset,
 318                          RADEON_GEM_DOMAIN_GTT,
 319                          0, 0);
 320       }
 321    } else {
 322       for (i = 0; i + 1 < nr; i += 2) {
 323          OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
 324                    (rmesa->tcl.aos[i].stride << 8) |
 325                    (rmesa->tcl.aos[i + 1].components << 16) |
 326                    (rmesa->tcl.aos[i + 1].stride << 24));
 327
 328          voffset =  rmesa->tcl.aos[i + 0].offset +
 329             offset * 4 * rmesa->tcl.aos[i + 0].stride;
 330          OUT_BATCH(voffset);
 331          voffset =  rmesa->tcl.aos[i + 1].offset +
 332             offset * 4 * rmesa->tcl.aos[i + 1].stride;
 333          OUT_BATCH(voffset);
 334       }
 335
 336       if (nr & 1) {
 337          OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
 338                    (rmesa->tcl.aos[nr - 1].stride << 8));
 339          voffset =  rmesa->tcl.aos[nr - 1].offset +
 340             offset * 4 * rmesa->tcl.aos[nr - 1].stride;
 341          OUT_BATCH(voffset);
 342       }
 343       for (i = 0; i + 1 < nr; i += 2) {
 344          voffset =  rmesa->tcl.aos[i + 0].offset +
 345             offset * 4 * rmesa->tcl.aos[i + 0].stride;
 346          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 347                                rmesa->tcl.aos[i+0].bo,
 348                                RADEON_GEM_DOMAIN_GTT,
 349                                0, 0);
 350          voffset =  rmesa->tcl.aos[i + 1].offset +
 351             offset * 4 * rmesa->tcl.aos[i + 1].stride;
 352          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 353                                rmesa->tcl.aos[i+1].bo,
 354                                RADEON_GEM_DOMAIN_GTT,
 355                                0, 0);
 356       }
 357       if (nr & 1) {
 358          voffset =  rmesa->tcl.aos[nr - 1].offset +
 359             offset * 4 * rmesa->tcl.aos[nr - 1].stride;
 360          radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
 361                                rmesa->tcl.aos[nr-1].bo,
 362                                RADEON_GEM_DOMAIN_GTT,
 363                                0, 0);
 364       }
 365    }
 366    END_BATCH();
 367
 368 #endif
 369 }
 370
 371 /* ================================================================
 372  * Buffer clear
 373  */
 374 #define RADEON_MAX_CLEARS       256
 375
 376 static void radeonClear( GLcontext *ctx, GLbitfield mask )
 377 {
 378    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 379    __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
 380    drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
 381    uint32_t clear;
 382    GLuint flags = 0;
 383    GLuint color_mask = 0;
 384    GLint ret, i;
 385    GLint cx, cy, cw, ch;
 386
 387    if ( RADEON_DEBUG & DEBUG_IOCTL ) {
 388       fprintf( stderr, "radeonClear\n");
 389    }
 390
 391    {
 392       LOCK_HARDWARE( &rmesa->radeon );
 393       UNLOCK_HARDWARE( &rmesa->radeon );
 394       if ( dPriv->numClipRects == 0 )
 395          return;
 396    }
 397
 398    radeonFlush( ctx );
 399
 400    if ( mask & BUFFER_BIT_FRONT_LEFT ) {
 401       flags |= RADEON_FRONT;
 402       color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
 403       mask &= ~BUFFER_BIT_FRONT_LEFT;
 404    }
 405
 406    if ( mask & BUFFER_BIT_BACK_LEFT ) {
 407       flags |= RADEON_BACK;
 408       color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
 409       mask &= ~BUFFER_BIT_BACK_LEFT;
 410    }
 411
 412    if ( mask & BUFFER_BIT_DEPTH ) {
 413       flags |= RADEON_DEPTH;
 414       mask &= ~BUFFER_BIT_DEPTH;
 415    }
 416
 417    if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) {
 418       flags |= RADEON_STENCIL;
 419       mask &= ~BUFFER_BIT_STENCIL;
 420    }
 421
 422    if ( mask ) {
 423       if (RADEON_DEBUG & DEBUG_FALLBACKS)
 424          fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
 425       _swrast_Clear( ctx, mask );
 426    }
 427
 428    if ( !flags )
 429       return;
 430
 431    if (rmesa->using_hyperz) {
 432       flags |= RADEON_USE_COMP_ZBUF;
 433 /*      if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
 434          flags |= RADEON_USE_HIERZ; */
 435       if (!(rmesa->radeon.state.stencil.hwBuffer) ||
 436          ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
 437             ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
 438           flags |= RADEON_CLEAR_FASTZ;
 439       }
 440    }
 441
 442    LOCK_HARDWARE( &rmesa->radeon );
 443
 444    /* compute region after locking: */
 445    cx = ctx->DrawBuffer->_Xmin;
 446    cy = ctx->DrawBuffer->_Ymin;
 447    cw = ctx->DrawBuffer->_Xmax - cx;
 448    ch = ctx->DrawBuffer->_Ymax - cy;
 449
 450    /* Flip top to bottom */
 451    cx += dPriv->x;
 452    cy  = dPriv->y + dPriv->h - cy - ch;
 453
 454    /* Throttle the number of clear ioctls we do.
 455     */
 456    while ( 1 ) {
 457       int ret;
 458       drm_radeon_getparam_t gp;
 459
 460       gp.param = RADEON_PARAM_LAST_CLEAR;
 461       gp.value = (int *)&clear;
 462       ret = drmCommandWriteRead( rmesa->radeon.dri.fd,
 463                                  DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
 464
 465       if ( ret ) {
 466          fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
 467          exit(1);
 468       }
 469
 470       if ( sarea->last_clear - clear <= RADEON_MAX_CLEARS ) {
 471          break;
 472       }
 473
 474       if ( rmesa->radeon.do_usleeps ) {
 475          UNLOCK_HARDWARE( &rmesa->radeon );
 476          DO_USLEEP( 1 );
 477          LOCK_HARDWARE( &rmesa->radeon );
 478       }
 479    }
 480
 481    /* Send current state to the hardware */
 482    rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
 483
 484    for ( i = 0 ; i < dPriv->numClipRects ; ) {
 485       GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
 486       drm_clip_rect_t *box = dPriv->pClipRects;
 487       drm_clip_rect_t *b = rmesa->radeon.sarea->boxes;
 488       drm_radeon_clear_t clear;
 489       drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
 490       GLint n = 0;
 491
 492       if (cw != dPriv->w || ch != dPriv->h) {
 493          /* clear subregion */
 494          for ( ; i < nr ; i++ ) {
 495             GLint x = box[i].x1;
 496             GLint y = box[i].y1;
 497             GLint w = box[i].x2 - x;
 498             GLint h = box[i].y2 - y;
 499
 500             if ( x < cx ) w -= cx - x, x = cx;
 501             if ( y < cy ) h -= cy - y, y = cy;
 502             if ( x + w > cx + cw ) w = cx + cw - x;
 503             if ( y + h > cy + ch ) h = cy + ch - y;
 504             if ( w <= 0 ) continue;
 505             if ( h <= 0 ) continue;
 506
 507             b->x1 = x;
 508             b->y1 = y;
 509             b->x2 = x + w;
 510             b->y2 = y + h;
 511             b++;
 512             n++;
 513          }
 514       } else {
 515          /* clear whole buffer */
 516          for ( ; i < nr ; i++ ) {
 517             *b++ = box[i];
 518             n++;
 519          }
 520       }
 521
 522       rmesa->radeon.sarea->nbox = n;
 523
 524       clear.flags       = flags;
 525       clear.clear_color = rmesa->radeon.state.color.clear;
 526       clear.clear_depth = rmesa->radeon.state.depth.clear;
 527       clear.color_mask  = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
 528       clear.depth_mask  = rmesa->radeon.state.stencil.clear;
 529       clear.depth_boxes = depth_boxes;
 530
 531       n--;
 532       b = rmesa->radeon.sarea->boxes;
 533       for ( ; n >= 0 ; n-- ) {
 534          depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
 535          depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
 536          depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
 537          depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
 538          depth_boxes[n].f[CLEAR_DEPTH] =
 539             (float)rmesa->radeon.state.depth.clear;
 540       }
 541
 542       ret = drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_CLEAR,
 543                              &clear, sizeof(drm_radeon_clear_t));
 544
 545       if ( ret ) {
 546          UNLOCK_HARDWARE( &rmesa->radeon );
 547          fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret );
 548          exit( 1 );
 549       }
 550    }
 551
 552    UNLOCK_HARDWARE( &rmesa->radeon );
 553    rmesa->radeon.hw.all_dirty = GL_TRUE;
 554 }
 555
 556 void radeonInitIoctlFuncs( GLcontext *ctx )
 557 {
 558     ctx->Driver.Clear = radeonClear;
 559     ctx->Driver.Finish = radeonFinish;
 560     ctx->Driver.Flush = radeonFlush;
 561 }
 562