1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
40 #include "main/attrib.h"
41 #include "main/enable.h"
42 #include "main/blend.h"
43 #include "main/bufferobj.h"
44 #include "main/buffers.h"
45 #include "main/depth.h"
46 #include "main/shaders.h"
47 #include "main/texstate.h"
48 #include "main/varray.h"
49 #include "swrast/swrast.h"
50 #include "main/stencil.h"
51 #include "main/matrix.h"
53 #include "main/glheader.h"
54 #include "main/imports.h"
55 #include "main/simple_list.h"
56 #include "swrast/swrast.h"
58 #include "radeon_context.h"
59 #include "radeon_common.h"
60 #include "radeon_state.h"
61 #include "radeon_ioctl.h"
62 #include "radeon_tcl.h"
63 #include "radeon_sanity.h"
65 #define STANDALONE_MMIO
66 #include "radeon_macros.h" /* for INREG() */
68 #include "drirenderbuffer.h"
71 #define RADEON_TIMEOUT 512
72 #define RADEON_IDLE_RETRY 16
75 /* =============================================================
76 * Kernel command buffer handling
79 /* The state atoms will be emitted in the order they appear in the atom list,
80 * so this step is important.
82 void radeonSetUpAtomList( r100ContextPtr rmesa
)
84 int i
, mtu
= rmesa
->radeon
.glCtx
->Const
.MaxTextureUnits
;
86 make_empty_list(&rmesa
->radeon
.hw
.atomlist
);
87 rmesa
->radeon
.hw
.atomlist
.name
= "atom-list";
89 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ctx
);
90 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.set
);
91 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lin
);
92 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msk
);
93 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.vpt
);
94 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tcl
);
95 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.msc
);
96 for (i
= 0; i
< mtu
; ++i
) {
97 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.tex
[i
]);
98 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.txr
[i
]);
99 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.cube
[i
]);
101 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.zbs
);
102 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mtl
);
103 for (i
= 0; i
< 3 + mtu
; ++i
)
104 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.mat
[i
]);
105 for (i
= 0; i
< 8; ++i
)
106 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.lit
[i
]);
107 for (i
= 0; i
< 6; ++i
)
108 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.ucp
[i
]);
109 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.eye
);
110 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.grd
);
111 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.fog
);
112 insert_at_tail(&rmesa
->radeon
.hw
.atomlist
, &rmesa
->hw
.glt
);
115 static void radeonEmitScissor(r100ContextPtr rmesa
)
117 BATCH_LOCALS(&rmesa
->radeon
);
118 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
121 if (rmesa
->radeon
.state
.scissor
.enabled
) {
123 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL
, 0));
124 OUT_BATCH(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] | RADEON_SCISSOR_ENABLE
);
125 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT
, 0));
126 OUT_BATCH((rmesa
->radeon
.state
.scissor
.rect
.y1
<< 16) |
127 rmesa
->radeon
.state
.scissor
.rect
.x1
);
128 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT
, 0));
129 OUT_BATCH(((rmesa
->radeon
.state
.scissor
.rect
.y2
) << 16) |
130 (rmesa
->radeon
.state
.scissor
.rect
.x2
));
134 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL
, 0));
135 OUT_BATCH(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & ~RADEON_SCISSOR_ENABLE
);
140 /* Fire a section of the retained (indexed_verts) buffer as a regular
143 extern void radeonEmitVbufPrim( r100ContextPtr rmesa
,
144 GLuint vertex_format
,
148 BATCH_LOCALS(&rmesa
->radeon
);
150 assert(!(primitive
& RADEON_CP_VC_CNTL_PRIM_WALK_IND
));
152 radeonEmitState(&rmesa
->radeon
);
153 radeonEmitScissor(rmesa
);
155 #if RADEON_OLD_PACKETS
157 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM
, 3);
158 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
159 OUT_BATCH_RELOC(rmesa
->ioctl
.vertex_offset
, rmesa
->ioctl
.bo
, rmesa
->ioctl
.vertex_offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
161 OUT_BATCH(rmesa
->ioctl
.vertex_offset
);
164 OUT_BATCH(vertex_nr
);
165 OUT_BATCH(vertex_format
);
166 OUT_BATCH(primitive
| RADEON_CP_VC_CNTL_PRIM_WALK_LIST
|
167 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
168 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
169 (vertex_nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
));
171 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
172 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
174 RADEON_GEM_DOMAIN_GTT
,
182 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF
, 1);
183 OUT_BATCH(vertex_format
);
184 OUT_BATCH(primitive
|
185 RADEON_CP_VC_CNTL_PRIM_WALK_LIST
|
186 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
187 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
188 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
189 (vertex_nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
));
194 void radeonFlushElts( GLcontext
*ctx
)
196 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
197 BATCH_LOCALS(&rmesa
->radeon
);
199 uint32_t *cmd
= (uint32_t *)(rmesa
->radeon
.cmdbuf
.cs
->packets
+ rmesa
->tcl
.elt_cmd_start
);
200 int dwords
= (rmesa
->radeon
.cmdbuf
.cs
->section_ndw
- rmesa
->radeon
.cmdbuf
.cs
->section_cdw
);
202 if (RADEON_DEBUG
& RADEON_IOCTL
)
203 fprintf(stderr
, "%s\n", __FUNCTION__
);
205 assert( rmesa
->radeon
.dma
.flush
== radeonFlushElts
);
206 rmesa
->radeon
.dma
.flush
= NULL
;
208 nr
= rmesa
->tcl
.elt_used
;
210 #if RADEON_OLD_PACKETS
211 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
216 #if RADEON_OLD_PACKETS
217 cmd
[1] |= (dwords
+ 3) << 16;
218 cmd
[5] |= nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
;
220 cmd
[1] |= (dwords
+ 2) << 16;
221 cmd
[3] |= nr
<< RADEON_CP_VC_CNTL_NUM_SHIFT
;
224 rmesa
->radeon
.cmdbuf
.cs
->cdw
+= dwords
;
225 rmesa
->radeon
.cmdbuf
.cs
->section_cdw
+= dwords
;
227 #if RADEON_OLD_PACKETS
228 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
229 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
231 RADEON_GEM_DOMAIN_GTT
,
238 if (RADEON_DEBUG
& RADEON_SYNC
) {
239 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
240 radeonFinish( rmesa
->radeon
.glCtx
);
245 GLushort
*radeonAllocEltsOpenEnded( r100ContextPtr rmesa
,
246 GLuint vertex_format
,
252 BATCH_LOCALS(&rmesa
->radeon
);
254 if (RADEON_DEBUG
& RADEON_IOCTL
)
255 fprintf(stderr
, "%s %d prim %x\n", __FUNCTION__
, min_nr
, primitive
);
257 assert((primitive
& RADEON_CP_VC_CNTL_PRIM_WALK_IND
));
259 radeonEmitState(&rmesa
->radeon
);
260 radeonEmitScissor(rmesa
);
262 rmesa
->tcl
.elt_cmd_start
= rmesa
->radeon
.cmdbuf
.cs
->cdw
;
264 /* round up min_nr to align the state */
265 align_min_nr
= (min_nr
+ 1) & ~1;
267 #if RADEON_OLD_PACKETS
268 BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr
)/4);
269 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM
, 0);
270 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
271 OUT_BATCH_RELOC(rmesa
->ioctl
.vertex_offset
, rmesa
->ioctl
.bo
, rmesa
->ioctl
.vertex_offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
273 OUT_BATCH(rmesa
->ioctl
.vertex_offset
);
275 OUT_BATCH(rmesa
->ioctl
.vertex_max
);
276 OUT_BATCH(vertex_format
);
277 OUT_BATCH(primitive
|
278 RADEON_CP_VC_CNTL_PRIM_WALK_IND
|
279 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
280 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
);
282 BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr
)/4);
283 OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX
, 0);
284 OUT_BATCH(vertex_format
);
285 OUT_BATCH(primitive
|
286 RADEON_CP_VC_CNTL_PRIM_WALK_IND
|
287 RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
|
288 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
289 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
);
293 rmesa
->tcl
.elt_cmd_offset
= rmesa
->radeon
.cmdbuf
.cs
->cdw
;
294 rmesa
->tcl
.elt_used
= min_nr
;
296 retval
= (GLushort
*)(rmesa
->radeon
.cmdbuf
.cs
->packets
+ rmesa
->tcl
.elt_cmd_offset
);
298 if (RADEON_DEBUG
& RADEON_RENDER
)
299 fprintf(stderr
, "%s: header prim %x \n",
300 __FUNCTION__
, primitive
);
302 assert(!rmesa
->radeon
.dma
.flush
);
303 rmesa
->radeon
.glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
304 rmesa
->radeon
.dma
.flush
= radeonFlushElts
;
309 void radeonEmitVertexAOS( r100ContextPtr rmesa
,
311 struct radeon_bo
*bo
,
314 #if RADEON_OLD_PACKETS
315 rmesa
->ioctl
.vertex_offset
= offset
;
316 rmesa
->ioctl
.bo
= bo
;
318 BATCH_LOCALS(&rmesa
->radeon
);
320 if (RADEON_DEBUG
& (RADEON_PRIMS
|DEBUG_IOCTL
))
321 fprintf(stderr
, "%s: vertex_size 0x%x offset 0x%x \n",
322 __FUNCTION__
, vertex_size
, offset
);
325 OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR
, 2);
327 OUT_BATCH(vertex_size
| (vertex_size
<< 8));
328 OUT_BATCH_RELOC(offset
, bo
, offset
, RADEON_GEM_DOMAIN_GTT
, 0, 0);
335 void radeonEmitAOS( r100ContextPtr rmesa
,
339 #if RADEON_OLD_PACKETS
341 rmesa
->ioctl
.bo
= rmesa
->radeon
.tcl
.aos
[0].bo
;
342 rmesa
->ioctl
.vertex_offset
=
343 (rmesa
->radeon
.tcl
.aos
[0].offset
+ offset
* rmesa
->radeon
.tcl
.aos
[0].stride
* 4);
344 rmesa
->ioctl
.vertex_max
= rmesa
->radeon
.tcl
.aos
[0].count
;
346 BATCH_LOCALS(&rmesa
->radeon
);
348 // int sz = AOS_BUFSZ(nr);
349 int sz
= 1 + (nr
>> 1) * 3 + (nr
& 1) * 2;
352 if (RADEON_DEBUG
& RADEON_IOCTL
)
353 fprintf(stderr
, "%s\n", __FUNCTION__
);
355 BEGIN_BATCH(sz
+2+(nr
* 2));
356 OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR
, sz
- 1);
359 if (!rmesa
->radeon
.radeonScreen
->kernel_mm
) {
360 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
361 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
362 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
363 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
364 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
366 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
367 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
368 OUT_BATCH_RELOC(voffset
,
369 rmesa
->radeon
.tcl
.aos
[i
].bo
,
371 RADEON_GEM_DOMAIN_GTT
,
373 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
374 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
375 OUT_BATCH_RELOC(voffset
,
376 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
378 RADEON_GEM_DOMAIN_GTT
,
383 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
384 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
385 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
386 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
387 OUT_BATCH_RELOC(voffset
,
388 rmesa
->radeon
.tcl
.aos
[nr
- 1].bo
,
390 RADEON_GEM_DOMAIN_GTT
,
394 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
395 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[i
].components
<< 0) |
396 (rmesa
->radeon
.tcl
.aos
[i
].stride
<< 8) |
397 (rmesa
->radeon
.tcl
.aos
[i
+ 1].components
<< 16) |
398 (rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
<< 24));
400 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
401 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
403 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
404 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
409 OUT_BATCH((rmesa
->radeon
.tcl
.aos
[nr
- 1].components
<< 0) |
410 (rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
<< 8));
411 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
412 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
415 for (i
= 0; i
+ 1 < nr
; i
+= 2) {
416 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 0].offset
+
417 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 0].stride
;
418 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
419 rmesa
->radeon
.tcl
.aos
[i
+0].bo
,
420 RADEON_GEM_DOMAIN_GTT
,
422 voffset
= rmesa
->radeon
.tcl
.aos
[i
+ 1].offset
+
423 offset
* 4 * rmesa
->radeon
.tcl
.aos
[i
+ 1].stride
;
424 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
425 rmesa
->radeon
.tcl
.aos
[i
+1].bo
,
426 RADEON_GEM_DOMAIN_GTT
,
430 voffset
= rmesa
->radeon
.tcl
.aos
[nr
- 1].offset
+
431 offset
* 4 * rmesa
->radeon
.tcl
.aos
[nr
- 1].stride
;
432 radeon_cs_write_reloc(rmesa
->radeon
.cmdbuf
.cs
,
433 rmesa
->radeon
.tcl
.aos
[nr
-1].bo
,
434 RADEON_GEM_DOMAIN_GTT
,
443 /* ================================================================
446 #define RADEON_MAX_CLEARS 256
448 static void radeonKernelClear(GLcontext
*ctx
, GLuint flags
)
450 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
451 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
452 drm_radeon_sarea_t
*sarea
= rmesa
->radeon
.sarea
;
455 GLint cx
, cy
, cw
, ch
;
457 LOCK_HARDWARE( &rmesa
->radeon
);
459 /* compute region after locking: */
460 cx
= ctx
->DrawBuffer
->_Xmin
;
461 cy
= ctx
->DrawBuffer
->_Ymin
;
462 cw
= ctx
->DrawBuffer
->_Xmax
- cx
;
463 ch
= ctx
->DrawBuffer
->_Ymax
- cy
;
465 /* Flip top to bottom */
467 cy
= dPriv
->y
+ dPriv
->h
- cy
- ch
;
469 /* Throttle the number of clear ioctls we do.
473 drm_radeon_getparam_t gp
;
475 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
476 gp
.value
= (int *)&clear
;
477 ret
= drmCommandWriteRead( rmesa
->radeon
.dri
.fd
,
478 DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
) );
481 fprintf( stderr
, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__
, ret
);
485 if ( sarea
->last_clear
- clear
<= RADEON_MAX_CLEARS
) {
489 if ( rmesa
->radeon
.do_usleeps
) {
490 UNLOCK_HARDWARE( &rmesa
->radeon
);
492 LOCK_HARDWARE( &rmesa
->radeon
);
496 /* Send current state to the hardware */
497 rcommonFlushCmdBufLocked( &rmesa
->radeon
, __FUNCTION__
);
499 for ( i
= 0 ; i
< dPriv
->numClipRects
; ) {
500 GLint nr
= MIN2( i
+ RADEON_NR_SAREA_CLIPRECTS
, dPriv
->numClipRects
);
501 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
502 drm_clip_rect_t
*b
= rmesa
->radeon
.sarea
->boxes
;
503 drm_radeon_clear_t clear
;
504 drm_radeon_clear_rect_t depth_boxes
[RADEON_NR_SAREA_CLIPRECTS
];
507 if (cw
!= dPriv
->w
|| ch
!= dPriv
->h
) {
508 /* clear subregion */
509 for ( ; i
< nr
; i
++ ) {
512 GLint w
= box
[i
].x2
- x
;
513 GLint h
= box
[i
].y2
- y
;
515 if ( x
< cx
) w
-= cx
- x
, x
= cx
;
516 if ( y
< cy
) h
-= cy
- y
, y
= cy
;
517 if ( x
+ w
> cx
+ cw
) w
= cx
+ cw
- x
;
518 if ( y
+ h
> cy
+ ch
) h
= cy
+ ch
- y
;
519 if ( w
<= 0 ) continue;
520 if ( h
<= 0 ) continue;
530 /* clear whole buffer */
531 for ( ; i
< nr
; i
++ ) {
537 rmesa
->radeon
.sarea
->nbox
= n
;
540 clear
.clear_color
= rmesa
->radeon
.state
.color
.clear
;
541 clear
.clear_depth
= rmesa
->radeon
.state
.depth
.clear
;
542 clear
.color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
543 clear
.depth_mask
= rmesa
->radeon
.state
.stencil
.clear
;
544 clear
.depth_boxes
= depth_boxes
;
547 b
= rmesa
->radeon
.sarea
->boxes
;
548 for ( ; n
>= 0 ; n
-- ) {
549 depth_boxes
[n
].f
[CLEAR_X1
] = (float)b
[n
].x1
;
550 depth_boxes
[n
].f
[CLEAR_Y1
] = (float)b
[n
].y1
;
551 depth_boxes
[n
].f
[CLEAR_X2
] = (float)b
[n
].x2
;
552 depth_boxes
[n
].f
[CLEAR_Y2
] = (float)b
[n
].y2
;
553 depth_boxes
[n
].f
[CLEAR_DEPTH
] =
554 (float)rmesa
->radeon
.state
.depth
.clear
;
557 ret
= drmCommandWrite( rmesa
->radeon
.dri
.fd
, DRM_RADEON_CLEAR
,
558 &clear
, sizeof(drm_radeon_clear_t
));
561 UNLOCK_HARDWARE( &rmesa
->radeon
);
562 fprintf( stderr
, "DRM_RADEON_CLEAR: return = %d\n", ret
);
566 UNLOCK_HARDWARE( &rmesa
->radeon
);
569 static void radeonClear( GLcontext
*ctx
, GLbitfield mask
)
571 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
572 __DRIdrawable
*dPriv
= radeon_get_drawable(&rmesa
->radeon
);
574 GLuint color_mask
= 0;
575 GLuint orig_mask
= mask
;
577 if (mask
& (BUFFER_BIT_FRONT_LEFT
| BUFFER_BIT_FRONT_RIGHT
)) {
578 rmesa
->radeon
.front_buffer_dirty
= GL_TRUE
;
581 if ( RADEON_DEBUG
& RADEON_IOCTL
) {
582 fprintf( stderr
, "radeonClear\n");
586 LOCK_HARDWARE( &rmesa
->radeon
);
587 UNLOCK_HARDWARE( &rmesa
->radeon
);
588 if ( dPriv
->numClipRects
== 0 )
592 radeon_firevertices(&rmesa
->radeon
);
594 if ( mask
& BUFFER_BIT_FRONT_LEFT
) {
595 flags
|= RADEON_FRONT
;
596 color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
597 mask
&= ~BUFFER_BIT_FRONT_LEFT
;
600 if ( mask
& BUFFER_BIT_BACK_LEFT
) {
601 flags
|= RADEON_BACK
;
602 color_mask
= rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
];
603 mask
&= ~BUFFER_BIT_BACK_LEFT
;
606 if ( mask
& BUFFER_BIT_DEPTH
) {
607 flags
|= RADEON_DEPTH
;
608 mask
&= ~BUFFER_BIT_DEPTH
;
611 if ( (mask
& BUFFER_BIT_STENCIL
) ) {
612 flags
|= RADEON_STENCIL
;
613 mask
&= ~BUFFER_BIT_STENCIL
;
617 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
618 fprintf(stderr
, "%s: swrast clear, mask: %x\n", __FUNCTION__
, mask
);
619 _swrast_Clear( ctx
, mask
);
625 if (rmesa
->using_hyperz
) {
626 flags
|= RADEON_USE_COMP_ZBUF
;
627 /* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
628 flags |= RADEON_USE_HIERZ; */
629 if (((flags
& RADEON_DEPTH
) && (flags
& RADEON_STENCIL
) &&
630 ((rmesa
->radeon
.state
.stencil
.clear
& RADEON_STENCIL_WRITE_MASK
) == RADEON_STENCIL_WRITE_MASK
))) {
631 flags
|= RADEON_CLEAR_FASTZ
;
635 if (rmesa
->radeon
.radeonScreen
->kernel_mm
)
636 radeonUserClear(ctx
, orig_mask
);
638 radeonKernelClear(ctx
, flags
);
639 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
643 void radeonInitIoctlFuncs( GLcontext
*ctx
)
645 ctx
->Driver
.Clear
= radeonClear
;
646 ctx
->Driver
.Finish
= radeonFinish
;
647 ctx
->Driver
.Flush
= radeonFlush
;