src/mesa/drivers/dri/radeon/radeon_ioctl.h

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Kevin E. Martin <martin@valinux.com>
  34  *   Gareth Hughes <gareth@valinux.com>
  35  */
  36
  37 #ifndef __RADEON_IOCTL_H__
  38 #define __RADEON_IOCTL_H__
  39
  40 #include "simple_list.h"
  41 #include "radeon_lock.h"
  42
  43
  44 extern void radeonEmitState( radeonContextPtr rmesa );
  45 extern void radeonEmitVertexAOS( radeonContextPtr rmesa,
  46                                  GLuint vertex_size,
  47                                  GLuint offset );
  48
  49 extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
  50                                 GLuint vertex_format,
  51                                 GLuint primitive,
  52                                 GLuint vertex_nr );
  53
  54 extern void radeonFlushElts( radeonContextPtr rmesa );
  55
  56 extern GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
  57                                            GLuint vertex_format,
  58                                            GLuint primitive,
  59                                            GLuint min_nr );
  60
  61 extern void radeonEmitAOS( radeonContextPtr rmesa,
  62                            struct radeon_dma_region **regions,
  63                            GLuint n,
  64                            GLuint offset );
  65
  66 extern void radeonEmitBlit( radeonContextPtr rmesa,
  67                             GLuint color_fmt,
  68                             GLuint src_pitch,
  69                             GLuint src_offset,
  70                             GLuint dst_pitch,
  71                             GLuint dst_offset,
  72                             GLint srcx, GLint srcy,
  73                             GLint dstx, GLint dsty,
  74                             GLuint w, GLuint h );
  75
  76 extern void radeonEmitWait( radeonContextPtr rmesa, GLuint flags );
  77
  78 extern void radeonFlushCmdBuf( radeonContextPtr rmesa, const char * );
  79 extern void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa );
  80
  81 extern void radeonAllocDmaRegion( radeonContextPtr rmesa,
  82                                   struct radeon_dma_region *region,
  83                                   int bytes,
  84                                   int alignment );
  85
  86 extern void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
  87                                        struct radeon_dma_region *region,
  88                                        int numverts,
  89                                        int vertsize,
  90                                        int alignment );
  91
  92 extern void radeonReleaseDmaRegion( radeonContextPtr rmesa,
  93                                     struct radeon_dma_region *region,
  94                                     const char *caller );
  95
  96 extern void radeonCopyBuffer( const __DRIdrawablePrivate *drawable );
  97 extern void radeonPageFlip( const __DRIdrawablePrivate *drawable );
  98 extern void radeonFlush( GLcontext *ctx );
  99 extern void radeonFinish( GLcontext *ctx );
 100 extern void radeonWaitForIdleLocked( radeonContextPtr rmesa );
 101 extern void radeonWaitForVBlank( radeonContextPtr rmesa );
 102 extern void radeonInitIoctlFuncs( GLcontext *ctx );
 103 extern void radeonGetAllParams( radeonContextPtr rmesa );
 104 extern void radeonSetUpAtomList( radeonContextPtr rmesa );
 105
 106 /* radeon_compat.c:
 107  */
 108 extern void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
 109                                        GLuint vertex_format,
 110                                        GLuint hw_primitive,
 111                                        GLuint nrverts );
 112
 113 /* ================================================================
 114  * Helper macros:
 115  */
 116
 117 /* Close off the last primitive, if it exists.
 118  */
 119 #define RADEON_NEWPRIM( rmesa )                 \
 120 do {                                            \
 121    if ( rmesa->dma.flush )                      \
 122       rmesa->dma.flush( rmesa );        \
 123 } while (0)
 124
 125 /* Can accomodate several state changes and primitive changes without
 126  * actually firing the buffer.
 127  */
 128 #define RADEON_STATECHANGE( rmesa, ATOM )                       \
 129 do {                                                            \
 130    RADEON_NEWPRIM( rmesa );                                     \
 131    rmesa->hw.ATOM.dirty = GL_TRUE;                              \
 132    rmesa->hw.is_dirty = GL_TRUE;                                \
 133 } while (0)
 134
 135 #define RADEON_DB_STATE( ATOM )                         \
 136    memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd,  \
 137            rmesa->hw.ATOM.cmd_size * 4)
 138
 139 static __inline int RADEON_DB_STATECHANGE(
 140    radeonContextPtr rmesa,
 141    struct radeon_state_atom *atom )
 142 {
 143    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
 144       int *tmp;
 145       RADEON_NEWPRIM( rmesa );
 146       atom->dirty = GL_TRUE;
 147       rmesa->hw.is_dirty = GL_TRUE;
 148       tmp = atom->cmd;
 149       atom->cmd = atom->lastcmd;
 150       atom->lastcmd = tmp;
 151       return 1;
 152    }
 153    else
 154       return 0;
 155 }
 156
 157
 158 /* Fire the buffered vertices no matter what.
 159  */
 160 #define RADEON_FIREVERTICES( rmesa )                    \
 161 do {                                                    \
 162    if ( rmesa->store.cmd_used || rmesa->dma.flush ) {   \
 163       radeonFlush( rmesa->glCtx );                      \
 164    }                                                    \
 165 } while (0)
 166
 167 /* Command lengths.  Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
 168  * are available, you will also be adding an rmesa->state.max_state_size because
 169  * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
 170  */
 171 #if RADEON_OLD_PACKETS
 172 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int))
 173 #define VERT_AOS_BUFSZ  (0)
 174 #define ELTS_BUFSZ(nr)  (24 + nr * 2)
 175 #define VBUF_BUFSZ      (6 * sizeof(int))
 176 #else
 177 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int))
 178 #define VERT_AOS_BUFSZ  (5 * sizeof(int))
 179 #define ELTS_BUFSZ(nr)  (16 + nr * 2)
 180 #define VBUF_BUFSZ      (4 * sizeof(int))
 181 #endif
 182
 183 /* Ensure that a minimum amount of space is available in the command buffer.
 184  * This is used to ensure atomicity of state updates with the rendering requests
 185  * that rely on them.
 186  *
 187  * An alternative would be to implement a "soft lock" such that when the buffer
 188  * wraps at an inopportune time, we grab the lock, flush the current buffer,
 189  * and hang on to the lock until the critical section is finished and we flush
 190  * the buffer again and unlock.
 191  */
 192 static __inline void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
 193                                               int bytes )
 194 {
 195    if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
 196       radeonFlushCmdBuf( rmesa, __FUNCTION__ );
 197    assert( bytes <= RADEON_CMD_BUF_SZ );
 198 }
 199
 200 /* Alloc space in the command buffer
 201  */
 202 static __inline char *radeonAllocCmdBuf( radeonContextPtr rmesa,
 203                                          int bytes, const char *where )
 204 {
 205    if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
 206       radeonFlushCmdBuf( rmesa, __FUNCTION__ );
 207
 208    assert(rmesa->dri.drmMinor >= 3);
 209
 210    {
 211       char *head = rmesa->store.cmd_buf + rmesa->store.cmd_used;
 212       rmesa->store.cmd_used += bytes;
 213       return head;
 214    }
 215 }
 216
 217 #endif /* __RADEON_IOCTL_H__ */