src/mesa/drivers/dri/radeon/radeon_maos_verts.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc., Austin, Texas.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38 #include "mtypes.h"
  39
  40 #include "array_cache/acache.h"
  41 #include "math/m_translate.h"
  42 #include "tnl/tnl.h"
  43 #include "tnl/t_pipeline.h"
  44 #include "math/m_translate.h"
  45 #include "radeon_context.h"
  46 #include "radeon_state.h"
  47 #include "radeon_ioctl.h"
  48 #include "radeon_tex.h"
  49 #include "radeon_tcl.h"
  50 #include "radeon_swtcl.h"
  51 #include "radeon_maos.h"
  52
  53
  54 #define RADEON_TCL_MAX_SETUP 19
  55
  56 union emit_union { float f; GLuint ui; radeon_color_t rgba; };
  57
  58 static struct {
  59    void   (*emit)( GLcontext *, GLuint, GLuint, void * );
  60    GLuint vertex_size;
  61    GLuint vertex_format;
  62 } setup_tab[RADEON_TCL_MAX_SETUP];
  63
  64 #define DO_W    (IND & RADEON_CP_VC_FRMT_W0)
  65 #define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
  66 #define DO_SPEC (IND & RADEON_CP_VC_FRMT_PKSPEC)
  67 #define DO_FOG  (IND & RADEON_CP_VC_FRMT_PKSPEC)
  68 #define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
  69 #define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
  70 #define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2)
  71 #define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
  72 #define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
  73
  74 #define DO_TEX3 0
  75
  76 #define GET_TEXSOURCE(n)  n
  77
  78 /***********************************************************************
  79  *             Generate vertex emit functions               *
  80  ***********************************************************************/
  81
  82
  83 /* Defined in order of increasing vertex size:
  84  */
  85 #define IDX 0
  86 #define IND (RADEON_CP_VC_FRMT_XY|              \
  87              RADEON_CP_VC_FRMT_Z|               \
  88              RADEON_CP_VC_FRMT_PKCOLOR)
  89 #define TAG(x) x##_rgba
  90 #include "radeon_maos_vbtmp.h"
  91
  92 #define IDX 1
  93 #define IND (RADEON_CP_VC_FRMT_XY|              \
  94              RADEON_CP_VC_FRMT_Z|               \
  95              RADEON_CP_VC_FRMT_N0)
  96 #define TAG(x) x##_n
  97 #include "radeon_maos_vbtmp.h"
  98
  99 #define IDX 2
 100 #define IND (RADEON_CP_VC_FRMT_XY|              \
 101              RADEON_CP_VC_FRMT_Z|               \
 102              RADEON_CP_VC_FRMT_PKCOLOR|         \
 103              RADEON_CP_VC_FRMT_ST0)
 104 #define TAG(x) x##_rgba_st
 105 #include "radeon_maos_vbtmp.h"
 106
 107 #define IDX 3
 108 #define IND (RADEON_CP_VC_FRMT_XY|              \
 109              RADEON_CP_VC_FRMT_Z|               \
 110              RADEON_CP_VC_FRMT_PKCOLOR|         \
 111              RADEON_CP_VC_FRMT_N0)
 112 #define TAG(x) x##_rgba_n
 113 #include "radeon_maos_vbtmp.h"
 114
 115 #define IDX 4
 116 #define IND (RADEON_CP_VC_FRMT_XY|              \
 117              RADEON_CP_VC_FRMT_Z|               \
 118              RADEON_CP_VC_FRMT_ST0|             \
 119              RADEON_CP_VC_FRMT_N0)
 120 #define TAG(x) x##_st_n
 121 #include "radeon_maos_vbtmp.h"
 122
 123 #define IDX 5
 124 #define IND (RADEON_CP_VC_FRMT_XY|              \
 125              RADEON_CP_VC_FRMT_Z|               \
 126              RADEON_CP_VC_FRMT_PKCOLOR|         \
 127              RADEON_CP_VC_FRMT_ST0|             \
 128              RADEON_CP_VC_FRMT_ST1)
 129 #define TAG(x) x##_rgba_st_st
 130 #include "radeon_maos_vbtmp.h"
 131
 132 #define IDX 6
 133 #define IND (RADEON_CP_VC_FRMT_XY|              \
 134              RADEON_CP_VC_FRMT_Z|               \
 135              RADEON_CP_VC_FRMT_PKCOLOR|         \
 136              RADEON_CP_VC_FRMT_ST0|             \
 137              RADEON_CP_VC_FRMT_N0)
 138 #define TAG(x) x##_rgba_st_n
 139 #include "radeon_maos_vbtmp.h"
 140
 141 #define IDX 7
 142 #define IND (RADEON_CP_VC_FRMT_XY|              \
 143              RADEON_CP_VC_FRMT_Z|               \
 144              RADEON_CP_VC_FRMT_PKCOLOR|         \
 145              RADEON_CP_VC_FRMT_PKSPEC|          \
 146              RADEON_CP_VC_FRMT_ST0|             \
 147              RADEON_CP_VC_FRMT_ST1)
 148 #define TAG(x) x##_rgba_spec_st_st
 149 #include "radeon_maos_vbtmp.h"
 150
 151 #define IDX 8
 152 #define IND (RADEON_CP_VC_FRMT_XY|              \
 153              RADEON_CP_VC_FRMT_Z|               \
 154              RADEON_CP_VC_FRMT_ST0|             \
 155              RADEON_CP_VC_FRMT_ST1|             \
 156              RADEON_CP_VC_FRMT_N0)
 157 #define TAG(x) x##_st_st_n
 158 #include "radeon_maos_vbtmp.h"
 159
 160 #define IDX 9
 161 #define IND (RADEON_CP_VC_FRMT_XY|              \
 162              RADEON_CP_VC_FRMT_Z|               \
 163              RADEON_CP_VC_FRMT_PKCOLOR|         \
 164              RADEON_CP_VC_FRMT_PKSPEC|          \
 165              RADEON_CP_VC_FRMT_ST0|             \
 166              RADEON_CP_VC_FRMT_ST1|             \
 167              RADEON_CP_VC_FRMT_N0)
 168 #define TAG(x) x##_rgba_spec_st_st_n
 169 #include "radeon_maos_vbtmp.h"
 170
 171 #define IDX 10
 172 #define IND (RADEON_CP_VC_FRMT_XY|              \
 173              RADEON_CP_VC_FRMT_Z|               \
 174              RADEON_CP_VC_FRMT_PKCOLOR|         \
 175              RADEON_CP_VC_FRMT_ST0|             \
 176              RADEON_CP_VC_FRMT_Q0)
 177 #define TAG(x) x##_rgba_stq
 178 #include "radeon_maos_vbtmp.h"
 179
 180 #define IDX 11
 181 #define IND (RADEON_CP_VC_FRMT_XY|              \
 182              RADEON_CP_VC_FRMT_Z|               \
 183              RADEON_CP_VC_FRMT_PKCOLOR|         \
 184              RADEON_CP_VC_FRMT_ST1|             \
 185              RADEON_CP_VC_FRMT_Q1|              \
 186              RADEON_CP_VC_FRMT_ST0|             \
 187              RADEON_CP_VC_FRMT_Q0)
 188 #define TAG(x) x##_rgba_stq_stq
 189 #include "radeon_maos_vbtmp.h"
 190
 191 #define IDX 12
 192 #define IND (RADEON_CP_VC_FRMT_XY|              \
 193              RADEON_CP_VC_FRMT_Z|               \
 194              RADEON_CP_VC_FRMT_W0|              \
 195              RADEON_CP_VC_FRMT_PKCOLOR|         \
 196              RADEON_CP_VC_FRMT_PKSPEC|          \
 197              RADEON_CP_VC_FRMT_ST0|             \
 198              RADEON_CP_VC_FRMT_Q0|              \
 199              RADEON_CP_VC_FRMT_ST1|             \
 200              RADEON_CP_VC_FRMT_Q1|              \
 201              RADEON_CP_VC_FRMT_N0)
 202 #define TAG(x) x##_w_rgba_spec_stq_stq_n
 203 #include "radeon_maos_vbtmp.h"
 204
 205 #define IDX 13
 206 #define IND (RADEON_CP_VC_FRMT_XY|              \
 207              RADEON_CP_VC_FRMT_Z|               \
 208              RADEON_CP_VC_FRMT_PKCOLOR|         \
 209              RADEON_CP_VC_FRMT_ST0|             \
 210              RADEON_CP_VC_FRMT_ST1|             \
 211              RADEON_CP_VC_FRMT_ST2)
 212 #define TAG(x) x##_rgba_st_st_st
 213 #include "radeon_maos_vbtmp.h"
 214
 215 #define IDX 14
 216 #define IND (RADEON_CP_VC_FRMT_XY|              \
 217              RADEON_CP_VC_FRMT_Z|               \
 218              RADEON_CP_VC_FRMT_PKCOLOR|         \
 219              RADEON_CP_VC_FRMT_PKSPEC|          \
 220              RADEON_CP_VC_FRMT_ST0|             \
 221              RADEON_CP_VC_FRMT_ST1|             \
 222              RADEON_CP_VC_FRMT_ST2)
 223 #define TAG(x) x##_rgba_spec_st_st_st
 224 #include "radeon_maos_vbtmp.h"
 225
 226 #define IDX 15
 227 #define IND (RADEON_CP_VC_FRMT_XY|              \
 228              RADEON_CP_VC_FRMT_Z|               \
 229              RADEON_CP_VC_FRMT_ST0|             \
 230              RADEON_CP_VC_FRMT_ST1|             \
 231              RADEON_CP_VC_FRMT_ST2|             \
 232              RADEON_CP_VC_FRMT_N0)
 233 #define TAG(x) x##_st_st_st_n
 234 #include "radeon_maos_vbtmp.h"
 235
 236 #define IDX 16
 237 #define IND (RADEON_CP_VC_FRMT_XY|              \
 238              RADEON_CP_VC_FRMT_Z|               \
 239              RADEON_CP_VC_FRMT_PKCOLOR|         \
 240              RADEON_CP_VC_FRMT_PKSPEC|          \
 241              RADEON_CP_VC_FRMT_ST0|             \
 242              RADEON_CP_VC_FRMT_ST1|             \
 243              RADEON_CP_VC_FRMT_ST2|             \
 244              RADEON_CP_VC_FRMT_N0)
 245 #define TAG(x) x##_rgba_spec_st_st_st_n
 246 #include "radeon_maos_vbtmp.h"
 247
 248 #define IDX 17
 249 #define IND (RADEON_CP_VC_FRMT_XY|              \
 250              RADEON_CP_VC_FRMT_Z|               \
 251              RADEON_CP_VC_FRMT_PKCOLOR|         \
 252              RADEON_CP_VC_FRMT_ST0|             \
 253              RADEON_CP_VC_FRMT_Q0|              \
 254              RADEON_CP_VC_FRMT_ST1|             \
 255              RADEON_CP_VC_FRMT_Q1|              \
 256              RADEON_CP_VC_FRMT_ST2|             \
 257              RADEON_CP_VC_FRMT_Q2)
 258 #define TAG(x) x##_rgba_stq_stq_stq
 259 #include "radeon_maos_vbtmp.h"
 260
 261 #define IDX 18
 262 #define IND (RADEON_CP_VC_FRMT_XY|              \
 263              RADEON_CP_VC_FRMT_Z|               \
 264              RADEON_CP_VC_FRMT_W0|              \
 265              RADEON_CP_VC_FRMT_PKCOLOR|         \
 266              RADEON_CP_VC_FRMT_PKSPEC|          \
 267              RADEON_CP_VC_FRMT_ST0|             \
 268              RADEON_CP_VC_FRMT_Q0|              \
 269              RADEON_CP_VC_FRMT_ST1|             \
 270              RADEON_CP_VC_FRMT_Q1|              \
 271              RADEON_CP_VC_FRMT_ST2|             \
 272              RADEON_CP_VC_FRMT_Q2|              \
 273              RADEON_CP_VC_FRMT_N0)
 274 #define TAG(x) x##_w_rgba_spec_stq_stq_stq_n
 275 #include "radeon_maos_vbtmp.h"
 276
 277
 278
 279
 280 /***********************************************************************
 281  *                         Initialization
 282  ***********************************************************************/
 283
 284
 285 static void init_tcl_verts( void )
 286 {
 287    init_rgba();
 288    init_n();
 289    init_rgba_n();
 290    init_rgba_st();
 291    init_st_n();
 292    init_rgba_st_st();
 293    init_rgba_st_n();
 294    init_rgba_spec_st_st();
 295    init_st_st_n();
 296    init_rgba_spec_st_st_n();
 297    init_rgba_stq();
 298    init_rgba_stq_stq();
 299    init_w_rgba_spec_stq_stq_n();
 300    init_rgba_st_st_st();
 301    init_rgba_spec_st_st_st();
 302    init_st_st_st_n();
 303    init_rgba_spec_st_st_st_n();
 304    init_rgba_stq_stq_stq();
 305    init_w_rgba_spec_stq_stq_stq_n();
 306 }
 307
 308
 309 void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 310 {
 311    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 312    struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
 313    GLuint req = 0;
 314    GLuint unit;
 315    GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
 316                  ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2));
 317    int i;
 318    static int firsttime = 1;
 319
 320    if (firsttime) {
 321       init_tcl_verts();
 322       firsttime = 0;
 323    }
 324
 325    if (1) {
 326       req |= RADEON_CP_VC_FRMT_Z;
 327       if (VB->ObjPtr->size == 4) {
 328          req |= RADEON_CP_VC_FRMT_W0;
 329       }
 330    }
 331
 332    if (inputs & VERT_BIT_NORMAL) {
 333       req |= RADEON_CP_VC_FRMT_N0;
 334    }
 335
 336    if (inputs & VERT_BIT_COLOR0) {
 337       req |= RADEON_CP_VC_FRMT_PKCOLOR;
 338    }
 339
 340    if (inputs & VERT_BIT_COLOR1) {
 341       req |= RADEON_CP_VC_FRMT_PKSPEC;
 342    }
 343
 344    for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) {
 345       if (inputs & VERT_BIT_TEX(unit)) {
 346          req |= RADEON_ST_BIT(unit);
 347          /* assume we need the 3rd coord if texgen is active for r/q OR at least
 348             3 coords are submitted. This may not be 100% correct */
 349          if (VB->TexCoordPtr[unit]->size >= 3) {
 350             req |= RADEON_Q_BIT(unit);
 351             vtx |= RADEON_Q_BIT(unit);
 352          }
 353          if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) )
 354             vtx |= RADEON_Q_BIT(unit);
 355          else if ((VB->TexCoordPtr[unit]->size >= 3) &&
 356                   ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) {
 357             GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3);
 358             if (((rmesa->NeedTexMatrix >> unit) & 1) &&
 359                  (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1)))
 360                radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ;
 361          }
 362       }
 363    }
 364
 365    if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
 366       RADEON_STATECHANGE( rmesa, tcl );
 367       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
 368    }
 369
 370    for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++)
 371       if ((setup_tab[i].vertex_format & req) == req)
 372          break;
 373
 374    if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
 375        rmesa->tcl.indexed_verts.buf)
 376       return;
 377
 378    if (rmesa->tcl.indexed_verts.buf)
 379       radeonReleaseArrays( ctx, ~0 );
 380
 381    radeonAllocDmaRegion( rmesa,
 382                          &rmesa->tcl.indexed_verts,
 383                          VB->Count * setup_tab[i].vertex_size * 4,
 384                          4);
 385
 386    /* The vertex code expects Obj to be clean to element 3.  To fix
 387     * this, add more vertex code (for obj-2, obj-3) or preferably move
 388     * to maos.
 389     */
 390    if (VB->ObjPtr->size < 3 ||
 391        (VB->ObjPtr->size == 3 &&
 392         (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) {
 393
 394       _math_trans_4f( rmesa->tcl.ObjClean.data,
 395                       VB->ObjPtr->data,
 396                       VB->ObjPtr->stride,
 397                       GL_FLOAT,
 398                       VB->ObjPtr->size,
 399                       0,
 400                       VB->Count );
 401
 402       switch (VB->ObjPtr->size) {
 403       case 1:
 404             _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
 405       case 2:
 406             _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2);
 407       case 3:
 408          if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) {
 409             _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3);
 410          }
 411       case 4:
 412       default:
 413          break;
 414       }
 415
 416       VB->ObjPtr = &rmesa->tcl.ObjClean;
 417    }
 418
 419
 420
 421    setup_tab[i].emit( ctx, 0, VB->Count,
 422                       rmesa->tcl.indexed_verts.address +
 423                       rmesa->tcl.indexed_verts.start );
 424
 425    rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
 426    rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts );
 427    rmesa->tcl.indexed_verts.aos_size = setup_tab[i].vertex_size;
 428    rmesa->tcl.indexed_verts.aos_stride = setup_tab[i].vertex_size;
 429
 430    rmesa->tcl.aos_components[0] = &rmesa->tcl.indexed_verts;
 431    rmesa->tcl.nr_aos_components = 1;
 432 }
 433
 434
 435
 436 void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
 437 {
 438    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 439
 440 #if 0
 441    if (RADEON_DEBUG & DEBUG_VERTS)
 442       _tnl_print_vert_flags( __FUNCTION__, newinputs );
 443 #endif
 444
 445    if (newinputs)
 446      radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ );
 447 }