1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 Tungsten Graphics Inc., Austin, Texas.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Keith Whitwell <keith@tungstengraphics.com>
40 #include "array_cache/acache.h"
41 #include "math/m_translate.h"
43 #include "tnl/t_pipeline.h"
44 #include "math/m_translate.h"
45 #include "radeon_context.h"
46 #include "radeon_state.h"
47 #include "radeon_ioctl.h"
48 #include "radeon_tex.h"
49 #include "radeon_tcl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_maos.h"
54 #define RADEON_TCL_MAX_SETUP 13
56 union emit_union
{ float f
; GLuint ui
; radeon_color_t rgba
; };
59 void (*emit
)( GLcontext
*, GLuint
, GLuint
, void * );
62 } setup_tab
[RADEON_TCL_MAX_SETUP
];
64 #define DO_W (IND & RADEON_CP_VC_FRMT_W0)
65 #define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
66 #define DO_SPEC (IND & RADEON_CP_VC_FRMT_PKSPEC)
67 #define DO_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
68 #define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
69 #define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
70 #define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
71 #define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
76 #define GET_TEXSOURCE(n) n
78 /***********************************************************************
79 * Generate vertex emit functions *
80 ***********************************************************************/
83 /* Defined in order of increasing vertex size:
86 #define IND (RADEON_CP_VC_FRMT_XY| \
87 RADEON_CP_VC_FRMT_Z| \
88 RADEON_CP_VC_FRMT_PKCOLOR)
89 #define TAG(x) x##_rgba
90 #include "radeon_maos_vbtmp.h"
93 #define IND (RADEON_CP_VC_FRMT_XY| \
94 RADEON_CP_VC_FRMT_Z| \
97 #include "radeon_maos_vbtmp.h"
100 #define IND (RADEON_CP_VC_FRMT_XY| \
101 RADEON_CP_VC_FRMT_Z| \
102 RADEON_CP_VC_FRMT_PKCOLOR| \
103 RADEON_CP_VC_FRMT_ST0)
104 #define TAG(x) x##_rgba_st
105 #include "radeon_maos_vbtmp.h"
108 #define IND (RADEON_CP_VC_FRMT_XY| \
109 RADEON_CP_VC_FRMT_Z| \
110 RADEON_CP_VC_FRMT_PKCOLOR| \
111 RADEON_CP_VC_FRMT_N0)
112 #define TAG(x) x##_rgba_n
113 #include "radeon_maos_vbtmp.h"
116 #define IND (RADEON_CP_VC_FRMT_XY| \
117 RADEON_CP_VC_FRMT_Z| \
118 RADEON_CP_VC_FRMT_ST0| \
119 RADEON_CP_VC_FRMT_N0)
120 #define TAG(x) x##_st_n
121 #include "radeon_maos_vbtmp.h"
124 #define IND (RADEON_CP_VC_FRMT_XY| \
125 RADEON_CP_VC_FRMT_Z| \
126 RADEON_CP_VC_FRMT_PKCOLOR| \
127 RADEON_CP_VC_FRMT_ST0| \
128 RADEON_CP_VC_FRMT_ST1)
129 #define TAG(x) x##_rgba_st_st
130 #include "radeon_maos_vbtmp.h"
133 #define IND (RADEON_CP_VC_FRMT_XY| \
134 RADEON_CP_VC_FRMT_Z| \
135 RADEON_CP_VC_FRMT_PKCOLOR| \
136 RADEON_CP_VC_FRMT_ST0| \
137 RADEON_CP_VC_FRMT_N0)
138 #define TAG(x) x##_rgba_st_n
139 #include "radeon_maos_vbtmp.h"
142 #define IND (RADEON_CP_VC_FRMT_XY| \
143 RADEON_CP_VC_FRMT_Z| \
144 RADEON_CP_VC_FRMT_PKCOLOR| \
145 RADEON_CP_VC_FRMT_PKSPEC| \
146 RADEON_CP_VC_FRMT_ST0| \
147 RADEON_CP_VC_FRMT_ST1)
148 #define TAG(x) x##_rgba_spec_st_st
149 #include "radeon_maos_vbtmp.h"
152 #define IND (RADEON_CP_VC_FRMT_XY| \
153 RADEON_CP_VC_FRMT_Z| \
154 RADEON_CP_VC_FRMT_ST0| \
155 RADEON_CP_VC_FRMT_ST1| \
156 RADEON_CP_VC_FRMT_N0)
157 #define TAG(x) x##_st_st_n
158 #include "radeon_maos_vbtmp.h"
161 #define IND (RADEON_CP_VC_FRMT_XY| \
162 RADEON_CP_VC_FRMT_Z| \
163 RADEON_CP_VC_FRMT_PKCOLOR| \
164 RADEON_CP_VC_FRMT_PKSPEC| \
165 RADEON_CP_VC_FRMT_ST0| \
166 RADEON_CP_VC_FRMT_ST1| \
167 RADEON_CP_VC_FRMT_N0)
168 #define TAG(x) x##_rgba_spec_st_st_n
169 #include "radeon_maos_vbtmp.h"
172 #define IND (RADEON_CP_VC_FRMT_XY| \
173 RADEON_CP_VC_FRMT_Z| \
174 RADEON_CP_VC_FRMT_PKCOLOR| \
175 RADEON_CP_VC_FRMT_ST0| \
176 RADEON_CP_VC_FRMT_Q0)
177 #define TAG(x) x##_rgba_stq
178 #include "radeon_maos_vbtmp.h"
181 #define IND (RADEON_CP_VC_FRMT_XY| \
182 RADEON_CP_VC_FRMT_Z| \
183 RADEON_CP_VC_FRMT_PKCOLOR| \
184 RADEON_CP_VC_FRMT_ST1| \
185 RADEON_CP_VC_FRMT_Q1| \
186 RADEON_CP_VC_FRMT_ST0| \
187 RADEON_CP_VC_FRMT_Q0)
188 #define TAG(x) x##_rgba_stq_stq
189 #include "radeon_maos_vbtmp.h"
192 #define IND (RADEON_CP_VC_FRMT_XY| \
193 RADEON_CP_VC_FRMT_Z| \
194 RADEON_CP_VC_FRMT_W0| \
195 RADEON_CP_VC_FRMT_PKCOLOR| \
196 RADEON_CP_VC_FRMT_PKSPEC| \
197 RADEON_CP_VC_FRMT_ST0| \
198 RADEON_CP_VC_FRMT_Q0| \
199 RADEON_CP_VC_FRMT_ST1| \
200 RADEON_CP_VC_FRMT_Q1| \
201 RADEON_CP_VC_FRMT_N0)
202 #define TAG(x) x##_w_rgba_spec_stq_stq_n
203 #include "radeon_maos_vbtmp.h"
209 /***********************************************************************
211 ***********************************************************************/
214 static void init_tcl_verts( void )
223 init_rgba_spec_st_st();
225 init_rgba_spec_st_st_n();
228 init_w_rgba_spec_stq_stq_n();
232 void radeonEmitArrays( GLcontext
*ctx
, GLuint inputs
)
234 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
235 struct vertex_buffer
*VB
= &TNL_CONTEXT(ctx
)->vb
;
237 GLuint vtx
= (rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &
238 ~(RADEON_TCL_VTX_Q0
|RADEON_TCL_VTX_Q1
));
240 static int firsttime
= 1;
248 req
|= RADEON_CP_VC_FRMT_Z
;
249 if (VB
->ObjPtr
->size
== 4) {
250 req
|= RADEON_CP_VC_FRMT_W0
;
254 if (inputs
& VERT_BIT_NORMAL
) {
255 req
|= RADEON_CP_VC_FRMT_N0
;
258 if (inputs
& VERT_BIT_COLOR0
) {
259 req
|= RADEON_CP_VC_FRMT_PKCOLOR
;
262 if (inputs
& VERT_BIT_COLOR1
) {
263 req
|= RADEON_CP_VC_FRMT_PKSPEC
;
266 if (inputs
& VERT_BIT_TEX0
) {
267 req
|= RADEON_CP_VC_FRMT_ST0
;
269 if (VB
->TexCoordPtr
[0]->size
== 4) {
270 req
|= RADEON_CP_VC_FRMT_Q0
;
271 vtx
|= RADEON_TCL_VTX_Q0
;
275 if (inputs
& VERT_BIT_TEX1
) {
276 req
|= RADEON_CP_VC_FRMT_ST1
;
278 if (VB
->TexCoordPtr
[1]->size
== 4) {
279 req
|= RADEON_CP_VC_FRMT_Q1
;
280 vtx
|= RADEON_TCL_VTX_Q1
;
284 if (vtx
!= rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
]) {
285 RADEON_STATECHANGE( rmesa
, tcl
);
286 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] = vtx
;
289 for (i
= 0 ; i
< RADEON_TCL_MAX_SETUP
; i
++)
290 if ((setup_tab
[i
].vertex_format
& req
) == req
)
293 if (rmesa
->tcl
.vertex_format
== setup_tab
[i
].vertex_format
&&
294 rmesa
->tcl
.indexed_verts
.buf
)
297 if (rmesa
->tcl
.indexed_verts
.buf
)
298 radeonReleaseArrays( ctx
, ~0 );
300 radeonAllocDmaRegionVerts( rmesa
,
301 &rmesa
->tcl
.indexed_verts
,
303 setup_tab
[i
].vertex_size
* 4,
306 /* The vertex code expects Obj to be clean to element 3. To fix
307 * this, add more vertex code (for obj-2, obj-3) or preferably move
310 if (VB
->ObjPtr
->size
< 3 ||
311 (VB
->ObjPtr
->size
== 3 &&
312 (setup_tab
[i
].vertex_format
& RADEON_CP_VC_FRMT_W0
))) {
314 _math_trans_4f( rmesa
->tcl
.ObjClean
.data
,
322 switch (VB
->ObjPtr
->size
) {
324 _mesa_vector4f_clean_elem(&rmesa
->tcl
.ObjClean
, VB
->Count
, 1);
326 _mesa_vector4f_clean_elem(&rmesa
->tcl
.ObjClean
, VB
->Count
, 2);
328 if (setup_tab
[i
].vertex_format
& RADEON_CP_VC_FRMT_W0
) {
329 _mesa_vector4f_clean_elem(&rmesa
->tcl
.ObjClean
, VB
->Count
, 3);
336 VB
->ObjPtr
= &rmesa
->tcl
.ObjClean
;
341 setup_tab
[i
].emit( ctx
, 0, VB
->Count
,
342 rmesa
->tcl
.indexed_verts
.address
+
343 rmesa
->tcl
.indexed_verts
.start
);
345 rmesa
->tcl
.vertex_format
= setup_tab
[i
].vertex_format
;
346 rmesa
->tcl
.indexed_verts
.aos_start
= GET_START( &rmesa
->tcl
.indexed_verts
);
347 rmesa
->tcl
.indexed_verts
.aos_size
= setup_tab
[i
].vertex_size
;
348 rmesa
->tcl
.indexed_verts
.aos_stride
= setup_tab
[i
].vertex_size
;
350 rmesa
->tcl
.aos_components
[0] = &rmesa
->tcl
.indexed_verts
;
351 rmesa
->tcl
.nr_aos_components
= 1;
356 void radeonReleaseArrays( GLcontext
*ctx
, GLuint newinputs
)
358 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
361 if (RADEON_DEBUG
& DEBUG_VERTS
)
362 _tnl_print_vert_flags( __FUNCTION__
, newinputs
);
366 radeonReleaseDmaRegion( rmesa
, &rmesa
->tcl
.indexed_verts
, __FUNCTION__
);