src/mesa/drivers/dri/radeon/radeon_maos_verts.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc., Austin, Texas.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38 #include "mtypes.h"
  39
  40 #include "array_cache/acache.h"
  41 #include "math/m_translate.h"
  42 #include "tnl/tnl.h"
  43 #include "tnl/t_pipeline.h"
  44
  45 #include "radeon_context.h"
  46 #include "radeon_state.h"
  47 #include "radeon_ioctl.h"
  48 #include "radeon_tex.h"
  49 #include "radeon_tcl.h"
  50 #include "radeon_swtcl.h"
  51 #include "radeon_maos.h"
  52
  53
  54 #define RADEON_TCL_MAX_SETUP 13
  55
  56 union emit_union { float f; GLuint ui; radeon_color_t rgba; };
  57
  58 static struct {
  59    void   (*emit)( GLcontext *, GLuint, GLuint, void * );
  60    GLuint vertex_size;
  61    GLuint vertex_format;
  62 } setup_tab[RADEON_TCL_MAX_SETUP];
  63
  64 #define DO_W    (IND & RADEON_CP_VC_FRMT_W0)
  65 #define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
  66 #define DO_SPEC (IND & RADEON_CP_VC_FRMT_PKSPEC)
  67 #define DO_FOG  (IND & RADEON_CP_VC_FRMT_PKSPEC)
  68 #define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
  69 #define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
  70 #define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
  71 #define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
  72
  73 #define DO_TEX2 0
  74 #define DO_TEX3 0
  75
  76 #define GET_TEXSOURCE(n)  n
  77
  78 /***********************************************************************
  79  *             Generate vertex emit functions               *
  80  ***********************************************************************/
  81
  82
  83 /* Defined in order of increasing vertex size:
  84  */
  85 #define IDX 0
  86 #define IND (RADEON_CP_VC_FRMT_XY|              \
  87              RADEON_CP_VC_FRMT_Z|               \
  88              RADEON_CP_VC_FRMT_PKCOLOR)
  89 #define TAG(x) x##_rgba
  90 #include "radeon_maos_vbtmp.h"
  91
  92 #define IDX 1
  93 #define IND (RADEON_CP_VC_FRMT_XY|              \
  94              RADEON_CP_VC_FRMT_Z|               \
  95              RADEON_CP_VC_FRMT_N0)
  96 #define TAG(x) x##_n
  97 #include "radeon_maos_vbtmp.h"
  98
  99 #define IDX 2
 100 #define IND (RADEON_CP_VC_FRMT_XY|              \
 101              RADEON_CP_VC_FRMT_Z|               \
 102              RADEON_CP_VC_FRMT_PKCOLOR|         \
 103              RADEON_CP_VC_FRMT_ST0)
 104 #define TAG(x) x##_rgba_st
 105 #include "radeon_maos_vbtmp.h"
 106
 107 #define IDX 3
 108 #define IND (RADEON_CP_VC_FRMT_XY|              \
 109              RADEON_CP_VC_FRMT_Z|               \
 110              RADEON_CP_VC_FRMT_PKCOLOR|         \
 111              RADEON_CP_VC_FRMT_N0)
 112 #define TAG(x) x##_rgba_n
 113 #include "radeon_maos_vbtmp.h"
 114
 115 #define IDX 4
 116 #define IND (RADEON_CP_VC_FRMT_XY|              \
 117              RADEON_CP_VC_FRMT_Z|               \
 118              RADEON_CP_VC_FRMT_ST0|             \
 119              RADEON_CP_VC_FRMT_N0)
 120 #define TAG(x) x##_st_n
 121 #include "radeon_maos_vbtmp.h"
 122
 123 #define IDX 5
 124 #define IND (RADEON_CP_VC_FRMT_XY|              \
 125              RADEON_CP_VC_FRMT_Z|               \
 126              RADEON_CP_VC_FRMT_PKCOLOR|         \
 127              RADEON_CP_VC_FRMT_ST0|             \
 128              RADEON_CP_VC_FRMT_ST1)
 129 #define TAG(x) x##_rgba_st_st
 130 #include "radeon_maos_vbtmp.h"
 131
 132 #define IDX 6
 133 #define IND (RADEON_CP_VC_FRMT_XY|              \
 134              RADEON_CP_VC_FRMT_Z|               \
 135              RADEON_CP_VC_FRMT_PKCOLOR|         \
 136              RADEON_CP_VC_FRMT_ST0|             \
 137              RADEON_CP_VC_FRMT_N0)
 138 #define TAG(x) x##_rgba_st_n
 139 #include "radeon_maos_vbtmp.h"
 140
 141 #define IDX 7
 142 #define IND (RADEON_CP_VC_FRMT_XY|              \
 143              RADEON_CP_VC_FRMT_Z|               \
 144              RADEON_CP_VC_FRMT_PKCOLOR|         \
 145              RADEON_CP_VC_FRMT_PKSPEC|          \
 146              RADEON_CP_VC_FRMT_ST0|             \
 147              RADEON_CP_VC_FRMT_ST1)
 148 #define TAG(x) x##_rgba_spec_st_st
 149 #include "radeon_maos_vbtmp.h"
 150
 151 #define IDX 8
 152 #define IND (RADEON_CP_VC_FRMT_XY|              \
 153              RADEON_CP_VC_FRMT_Z|               \
 154              RADEON_CP_VC_FRMT_ST0|             \
 155              RADEON_CP_VC_FRMT_ST1|             \
 156              RADEON_CP_VC_FRMT_N0)
 157 #define TAG(x) x##_st_st_n
 158 #include "radeon_maos_vbtmp.h"
 159
 160 #define IDX 9
 161 #define IND (RADEON_CP_VC_FRMT_XY|              \
 162              RADEON_CP_VC_FRMT_Z|               \
 163              RADEON_CP_VC_FRMT_PKCOLOR|         \
 164              RADEON_CP_VC_FRMT_PKSPEC|          \
 165              RADEON_CP_VC_FRMT_ST0|             \
 166              RADEON_CP_VC_FRMT_ST1|             \
 167              RADEON_CP_VC_FRMT_N0)
 168 #define TAG(x) x##_rgba_spec_st_st_n
 169 #include "radeon_maos_vbtmp.h"
 170
 171 #define IDX 10
 172 #define IND (RADEON_CP_VC_FRMT_XY|              \
 173              RADEON_CP_VC_FRMT_Z|               \
 174              RADEON_CP_VC_FRMT_PKCOLOR|         \
 175              RADEON_CP_VC_FRMT_ST0|             \
 176              RADEON_CP_VC_FRMT_Q0)
 177 #define TAG(x) x##_rgba_stq
 178 #include "radeon_maos_vbtmp.h"
 179
 180 #define IDX 11
 181 #define IND (RADEON_CP_VC_FRMT_XY|              \
 182              RADEON_CP_VC_FRMT_Z|               \
 183              RADEON_CP_VC_FRMT_PKCOLOR|         \
 184              RADEON_CP_VC_FRMT_ST1|             \
 185              RADEON_CP_VC_FRMT_Q1|              \
 186              RADEON_CP_VC_FRMT_ST0|             \
 187              RADEON_CP_VC_FRMT_Q0)
 188 #define TAG(x) x##_rgba_stq_stq
 189 #include "radeon_maos_vbtmp.h"
 190
 191 #define IDX 12
 192 #define IND (RADEON_CP_VC_FRMT_XY|              \
 193              RADEON_CP_VC_FRMT_Z|               \
 194              RADEON_CP_VC_FRMT_W0|              \
 195              RADEON_CP_VC_FRMT_PKCOLOR|         \
 196              RADEON_CP_VC_FRMT_PKSPEC|          \
 197              RADEON_CP_VC_FRMT_ST0|             \
 198              RADEON_CP_VC_FRMT_Q0|              \
 199              RADEON_CP_VC_FRMT_ST1|             \
 200              RADEON_CP_VC_FRMT_Q1|              \
 201              RADEON_CP_VC_FRMT_N0)
 202 #define TAG(x) x##_w_rgba_spec_stq_stq_n
 203 #include "radeon_maos_vbtmp.h"
 204
 205
 206
 207
 208
 209 /***********************************************************************
 210  *                         Initialization
 211  ***********************************************************************/
 212
 213
 214 static void init_tcl_verts( void )
 215 {
 216    init_rgba();
 217    init_n();
 218    init_rgba_n();
 219    init_rgba_st();
 220    init_st_n();
 221    init_rgba_st_st();
 222    init_rgba_st_n();
 223    init_rgba_spec_st_st();
 224    init_st_st_n();
 225    init_rgba_spec_st_st_n();
 226    init_rgba_stq();
 227    init_rgba_stq_stq();
 228    init_w_rgba_spec_stq_stq_n();
 229 }
 230
 231
 232 void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 233 {
 234    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 235    struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
 236    GLuint req = 0;
 237    GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
 238                  ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1));
 239    int i;
 240    static int firsttime = 1;
 241
 242    if (firsttime) {
 243       init_tcl_verts();
 244       firsttime = 0;
 245    }
 246
 247    if (1) {
 248       req |= RADEON_CP_VC_FRMT_Z;
 249       if (VB->ObjPtr->size == 4) {
 250          req |= RADEON_CP_VC_FRMT_W0;
 251       }
 252    }
 253
 254    if (inputs & VERT_BIT_NORMAL) {
 255       req |= RADEON_CP_VC_FRMT_N0;
 256    }
 257
 258    if (inputs & VERT_BIT_COLOR0) {
 259       req |= RADEON_CP_VC_FRMT_PKCOLOR;
 260    }
 261
 262    if (inputs & VERT_BIT_COLOR1) {
 263       req |= RADEON_CP_VC_FRMT_PKSPEC;
 264    }
 265
 266    if (inputs & VERT_BIT_TEX0) {
 267       req |= RADEON_CP_VC_FRMT_ST0;
 268
 269       if (VB->TexCoordPtr[0]->size == 4) {
 270          req |= RADEON_CP_VC_FRMT_Q0;
 271          vtx |= RADEON_TCL_VTX_Q0;
 272       }
 273    }
 274
 275    if (inputs & VERT_BIT_TEX1) {
 276       req |= RADEON_CP_VC_FRMT_ST1;
 277
 278       if (VB->TexCoordPtr[1]->size == 4) {
 279          req |= RADEON_CP_VC_FRMT_Q1;
 280          vtx |= RADEON_TCL_VTX_Q1;
 281       }
 282    }
 283
 284    if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
 285       RADEON_STATECHANGE( rmesa, tcl );
 286       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
 287    }
 288
 289    for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++)
 290       if ((setup_tab[i].vertex_format & req) == req)
 291          break;
 292
 293    if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
 294        rmesa->tcl.indexed_verts.buf)
 295       return;
 296
 297    if (rmesa->tcl.indexed_verts.buf)
 298       radeonReleaseArrays( ctx, ~0 );
 299
 300    radeonAllocDmaRegionVerts( rmesa,
 301                               &rmesa->tcl.indexed_verts,
 302                               VB->Count,
 303                               setup_tab[i].vertex_size * 4,
 304                               4);
 305
 306    /* The vertex code expects Obj to be clean to element 3.  To fix
 307     * this, add more vertex code (for obj-2, obj-3) or preferably move
 308     * to maos.
 309     */
 310    if (VB->ObjPtr->size < 3 ||
 311        (VB->ObjPtr->size == 3 &&
 312         (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) {
 313
 314       _math_trans_4f( rmesa->tcl.ObjClean.data,
 315                       VB->ObjPtr->data,
 316                       VB->ObjPtr->stride,
 317                       GL_FLOAT,
 318                       VB->ObjPtr->size,
 319                       0,
 320                       VB->Count );
 321
 322       switch (VB->ObjPtr->size) {
 323       case 1:
 324             _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
 325       case 2:
 326             _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2);
 327       case 3:
 328          if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) {
 329             _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3);
 330          }
 331       case 4:
 332       default:
 333          break;
 334       }
 335
 336       VB->ObjPtr = &rmesa->tcl.ObjClean;
 337    }
 338
 339
 340
 341    setup_tab[i].emit( ctx, 0, VB->Count,
 342                       rmesa->tcl.indexed_verts.address +
 343                       rmesa->tcl.indexed_verts.start );
 344
 345    rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
 346    rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts );
 347    rmesa->tcl.indexed_verts.aos_size = setup_tab[i].vertex_size;
 348    rmesa->tcl.indexed_verts.aos_stride = setup_tab[i].vertex_size;
 349
 350    rmesa->tcl.aos_components[0] = &rmesa->tcl.indexed_verts;
 351    rmesa->tcl.nr_aos_components = 1;
 352 }
 353
 354
 355
 356 void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
 357 {
 358    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 359
 360 #if 0
 361    if (RADEON_DEBUG & DEBUG_VERTS)
 362       _tnl_print_vert_flags( __FUNCTION__, newinputs );
 363 #endif
 364
 365    if (newinputs)
 366      radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ );
 367 }