src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora.
   3  * Copyright (C) 2008 Nicolai Haehnle.
   4  *
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sublicense, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial
  17  * portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  22  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  23  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  24  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  25  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "radeon_mipmap_tree.h"
  30
  31 #include <errno.h>
  32 #include <unistd.h>
  33
  34 #include "main/simple_list.h"
  35 #include "main/teximage.h"
  36 #include "main/texobj.h"
  37 #include "main/enums.h"
  38 #include "radeon_texture.h"
  39 #include "radeon_tile.h"
  40
  41 static unsigned get_aligned_compressed_row_stride(
  42                 gl_format format,
  43                 unsigned width,
  44                 unsigned minStride)
  45 {
  46         const unsigned blockBytes = _mesa_get_format_bytes(format);
  47         unsigned blockWidth, blockHeight;
  48         unsigned stride;
  49
  50         _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
  51
  52         /* Count number of blocks required to store the given width.
  53          * And then multiple it with bytes required to store a block.
  54          */
  55         stride = (width + blockWidth - 1) / blockWidth * blockBytes;
  56
  57         /* Round the given minimum stride to the next full blocksize.
  58          * (minStride + blockBytes - 1) / blockBytes * blockBytes
  59          */
  60         if ( stride < minStride )
  61                 stride = (minStride + blockBytes - 1) / blockBytes * blockBytes;
  62
  63         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
  64                         "%s width %u, minStride %u, block(bytes %u, width %u):"
  65                         "stride %u\n",
  66                         __func__, width, minStride,
  67                         blockBytes, blockWidth,
  68                         stride);
  69
  70         return stride;
  71 }
  72
  73 unsigned get_texture_image_size(
  74                 gl_format format,
  75                 unsigned rowStride,
  76                 unsigned height,
  77                 unsigned depth,
  78                 unsigned tiling)
  79 {
  80         if (_mesa_is_format_compressed(format)) {
  81                 unsigned blockWidth, blockHeight;
  82
  83                 _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
  84
  85                 return rowStride * ((height + blockHeight - 1) / blockHeight) * depth;
  86         } else if (tiling) {
  87                 /* Need to align height to tile height */
  88                 unsigned tileWidth, tileHeight;
  89
  90                 get_tile_size(format, &tileWidth, &tileHeight);
  91                 tileHeight--;
  92
  93                 height = (height + tileHeight) & ~tileHeight;
  94         }
  95
  96         return rowStride * height * depth;
  97 }
  98
  99 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
 100 {
 101         if (_mesa_is_format_compressed(format)) {
 102                 return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
 103         } else {
 104                 unsigned row_align;
 105
 106                 if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
 107                         row_align = rmesa->texture_rect_row_align - 1;
 108                 } else if (tiling) {
 109                         unsigned tileWidth, tileHeight;
 110                         get_tile_size(format, &tileWidth, &tileHeight);
 111                         row_align = tileWidth * _mesa_get_format_bytes(format) - 1;
 112                 } else {
 113                         row_align = rmesa->texture_row_align - 1;
 114                 }
 115
 116                 return (_mesa_format_row_stride(format, width) + row_align) & ~row_align;
 117         }
 118 }
 119
 120 /**
 121  * Compute sizes and fill in offset and blit information for the given
 122  * image (determined by \p face and \p level).
 123  *
 124  * \param curOffset points to the offset at which the image is to be stored
 125  * and is updated by this function according to the size of the image.
 126  */
 127 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 128         GLuint face, GLuint level, GLuint* curOffset)
 129 {
 130         radeon_mipmap_level *lvl = &mt->levels[level];
 131         GLuint height;
 132
 133         height = _mesa_next_pow_two_32(lvl->height);
 134
 135         lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
 136         lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
 137
 138         assert(lvl->size > 0);
 139
 140         lvl->faces[face].offset = *curOffset;
 141         *curOffset += lvl->size;
 142
 143         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 144                         "%s(%p) level %d, face %d: rs:%d %dx%d at %d\n",
 145                         __func__, rmesa,
 146                         level, face,
 147                         lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
 148 }
 149
 150 static GLuint minify(GLuint size, GLuint levels)
 151 {
 152         size = size >> levels;
 153         if (size < 1)
 154                 size = 1;
 155         return size;
 156 }
 157
 158
 159 static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 160 {
 161         GLuint curOffset, i, face, level;
 162
 163         assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
 164
 165         curOffset = 0;
 166         for(face = 0; face < mt->faces; face++) {
 167
 168                 for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
 169                         mt->levels[level].valid = 1;
 170                         mt->levels[level].width = minify(mt->width0, i);
 171                         mt->levels[level].height = minify(mt->height0, i);
 172                         mt->levels[level].depth = minify(mt->depth0, i);
 173                         compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
 174                 }
 175         }
 176
 177         /* Note the required size in memory */
 178         mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
 179
 180         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 181                         "%s(%p, %p) total size %d\n",
 182                         __func__, rmesa, mt, mt->totalsize);
 183 }
 184
 185 /**
 186  * Create a new mipmap tree, calculate its layout and allocate memory.
 187  */
 188 static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
 189                 GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
 190                 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
 191 {
 192         radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
 193
 194         radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 195                 "%s(%p) new tree is %p.\n",
 196                 __func__, rmesa, mt);
 197
 198         mt->mesaFormat = mesaFormat;
 199         mt->refcount = 1;
 200         mt->target = target;
 201         mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
 202         mt->baseLevel = baseLevel;
 203         mt->numLevels = numLevels;
 204         mt->width0 = width0;
 205         mt->height0 = height0;
 206         mt->depth0 = depth0;
 207         mt->tilebits = tilebits;
 208
 209         calculate_miptree_layout(rmesa, mt);
 210
 211         mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
 212                             0, mt->totalsize, 1024,
 213                             RADEON_GEM_DOMAIN_VRAM,
 214                             0);
 215
 216         return mt;
 217 }
 218
 219 void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr)
 220 {
 221         assert(!*ptr);
 222
 223         mt->refcount++;
 224         assert(mt->refcount > 0);
 225
 226         *ptr = mt;
 227 }
 228
 229 void radeon_miptree_unreference(radeon_mipmap_tree **ptr)
 230 {
 231         radeon_mipmap_tree *mt = *ptr;
 232         if (!mt)
 233                 return;
 234
 235         assert(mt->refcount > 0);
 236
 237         mt->refcount--;
 238         if (!mt->refcount) {
 239                 radeon_bo_unref(mt->bo);
 240                 free(mt);
 241         }
 242
 243         *ptr = 0;
 244 }
 245
 246 /**
 247  * Calculate min and max LOD for the given texture object.
 248  * @param[in] tObj texture object whose LOD values to calculate
 249  * @param[out] pminLod minimal LOD
 250  * @param[out] pmaxLod maximal LOD
 251  */
 252 static void calculate_min_max_lod(struct gl_texture_object *tObj,
 253                                        unsigned *pminLod, unsigned *pmaxLod)
 254 {
 255         int minLod, maxLod;
 256         /* Yes, this looks overly complicated, but it's all needed.
 257         */
 258         switch (tObj->Target) {
 259         case GL_TEXTURE_1D:
 260         case GL_TEXTURE_2D:
 261         case GL_TEXTURE_3D:
 262         case GL_TEXTURE_CUBE_MAP:
 263                 if (tObj->Sampler.MinFilter == GL_NEAREST || tObj->Sampler.MinFilter == GL_LINEAR) {
 264                         /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
 265                         */
 266                         minLod = maxLod = tObj->BaseLevel;
 267                 } else {
 268                         minLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MinLod);
 269                         minLod = MAX2(minLod, tObj->BaseLevel);
 270                         minLod = MIN2(minLod, tObj->MaxLevel);
 271                         maxLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MaxLod + 0.5);
 272                         maxLod = MIN2(maxLod, tObj->MaxLevel);
 273                         maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod);
 274                         maxLod = MAX2(maxLod, minLod); /* need at least one level */
 275                 }
 276                 break;
 277         case GL_TEXTURE_RECTANGLE_NV:
 278         case GL_TEXTURE_4D_SGIS:
 279                 minLod = maxLod = 0;
 280                 break;
 281         default:
 282                 return;
 283         }
 284
 285         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 286                         "%s(%p) target %s, min %d, max %d.\n",
 287                         __func__, tObj,
 288                         _mesa_lookup_enum_by_nr(tObj->Target),
 289                         minLod, maxLod);
 290
 291         /* save these values */
 292         *pminLod = minLod;
 293         *pmaxLod = maxLod;
 294 }
 295
 296 /**
 297  * Checks whether the given miptree can hold the given texture image at the
 298  * given face and level.
 299  */
 300 GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 301                 struct gl_texture_image *texImage, GLuint face, GLuint level)
 302 {
 303         radeon_mipmap_level *lvl;
 304
 305         if (face >= mt->faces)
 306                 return GL_FALSE;
 307
 308         if (texImage->TexFormat != mt->mesaFormat)
 309                 return GL_FALSE;
 310
 311         lvl = &mt->levels[level];
 312         if (!lvl->valid ||
 313             lvl->width != texImage->Width ||
 314             lvl->height != texImage->Height ||
 315             lvl->depth != texImage->Depth)
 316                 return GL_FALSE;
 317
 318         return GL_TRUE;
 319 }
 320
 321 /**
 322  * Checks whether the given miptree has the right format to store the given texture object.
 323  */
 324 static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj)
 325 {
 326         struct gl_texture_image *firstImage;
 327         unsigned numLevels;
 328         radeon_mipmap_level *mtBaseLevel;
 329
 330         if (texObj->BaseLevel < mt->baseLevel)
 331                 return GL_FALSE;
 332
 333         mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel];
 334         firstImage = texObj->Image[0][texObj->BaseLevel];
 335         numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1);
 336
 337         if (radeon_is_debug_enabled(RADEON_TEXTURE,RADEON_TRACE)) {
 338                 fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj);
 339                 fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target);
 340                 fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat);
 341                 fprintf(stderr, "numLevels %d vs %d\n", mt->numLevels, numLevels);
 342                 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
 343                 fprintf(stderr, "height0 %d vs %d\n", mtBaseLevel->height, firstImage->Height);
 344                 fprintf(stderr, "depth0 %d vs %d\n", mtBaseLevel->depth, firstImage->Depth);
 345                 if (mt->target == texObj->Target &&
 346                 mt->mesaFormat == firstImage->TexFormat &&
 347                 mt->numLevels >= numLevels &&
 348                 mtBaseLevel->width == firstImage->Width &&
 349                 mtBaseLevel->height == firstImage->Height &&
 350                 mtBaseLevel->depth == firstImage->Depth) {
 351                         fprintf(stderr, "MATCHED\n");
 352                 } else {
 353                         fprintf(stderr, "NOT MATCHED\n");
 354                 }
 355         }
 356
 357         return (mt->target == texObj->Target &&
 358                 mt->mesaFormat == firstImage->TexFormat &&
 359                 mt->numLevels >= numLevels &&
 360                 mtBaseLevel->width == firstImage->Width &&
 361                 mtBaseLevel->height == firstImage->Height &&
 362                 mtBaseLevel->depth == firstImage->Depth);
 363 }
 364
 365 /**
 366  * Try to allocate a mipmap tree for the given texture object.
 367  * @param[in] rmesa radeon context
 368  * @param[in] t radeon texture object
 369  */
 370 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t)
 371 {
 372         struct gl_texture_object *texObj = &t->base;
 373         struct gl_texture_image *texImg = texObj->Image[0][texObj->BaseLevel];
 374         GLuint numLevels;
 375
 376         assert(!t->mt);
 377
 378         if (!texImg) {
 379                 radeon_warning("%s(%p) No image in given texture object(%p).\n",
 380                                 __func__, rmesa, t);
 381                 return;
 382         }
 383
 384
 385         numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1);
 386
 387         t->mt = radeon_miptree_create(rmesa, t->base.Target,
 388                 texImg->TexFormat, texObj->BaseLevel,
 389                 numLevels, texImg->Width, texImg->Height,
 390                 texImg->Depth, t->tile_bits);
 391 }
 392
 393 GLuint
 394 radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 395                             GLuint face, GLuint level)
 396 {
 397         if (mt->target == GL_TEXTURE_CUBE_MAP_ARB)
 398                 return (mt->levels[level].faces[face].offset);
 399         else
 400                 return mt->levels[level].faces[0].offset;
 401 }
 402
 403 /**
 404  * Ensure that the given image is stored in the given miptree from now on.
 405  */
 406 static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
 407                                                                          radeon_texture_image *image,
 408                                                                          int face, int level)
 409 {
 410         radeon_mipmap_level *dstlvl = &mt->levels[level];
 411         unsigned char *dest;
 412
 413         assert(image->mt != mt);
 414         assert(dstlvl->valid);
 415         assert(dstlvl->width == image->base.Base.Width);
 416         assert(dstlvl->height == image->base.Base.Height);
 417         assert(dstlvl->depth == image->base.Base.Depth);
 418
 419         radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
 420                         "%s miptree %p, image %p, face %d, level %d.\n",
 421                         __func__, mt, image, face, level);
 422
 423         radeon_bo_map(mt->bo, GL_TRUE);
 424         dest = mt->bo->ptr + dstlvl->faces[face].offset;
 425
 426         if (image->mt) {
 427                 /* Format etc. should match, so we really just need a memcpy().
 428                  * In fact, that memcpy() could be done by the hardware in many
 429                  * cases, provided that we have a proper memory manager.
 430                  */
 431                 assert(mt->mesaFormat == image->base.Base.TexFormat);
 432
 433                 radeon_mipmap_level *srclvl = &image->mt->levels[image->base.Base.Level];
 434
 435                 assert(image->base.Base.Level == level);
 436                 assert(srclvl->size == dstlvl->size);
 437                 assert(srclvl->rowstride == dstlvl->rowstride);
 438
 439                 radeon_bo_map(image->mt->bo, GL_FALSE);
 440
 441                 memcpy(dest,
 442                         image->mt->bo->ptr + srclvl->faces[face].offset,
 443                         dstlvl->size);
 444                 radeon_bo_unmap(image->mt->bo);
 445
 446                 radeon_miptree_unreference(&image->mt);
 447         } else if (image->base.Data) {
 448                 /* This condition should be removed, it's here to workaround
 449                  * a segfault when mapping textures during software fallbacks.
 450                  */
 451                 radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
 452                                 "%s Trying to map texture in sowftware fallback.\n",
 453                                 __func__);
 454                 const uint32_t srcrowstride = _mesa_format_row_stride(image->base.Base.TexFormat, image->base.Base.Width);
 455                 uint32_t rows = image->base.Base.Height * image->base.Base.Depth;
 456
 457                 if (_mesa_is_format_compressed(image->base.Base.TexFormat)) {
 458                         uint32_t blockWidth, blockHeight;
 459                         _mesa_get_format_block_size(image->base.Base.TexFormat, &blockWidth, &blockHeight);
 460                         rows = (rows + blockHeight - 1) / blockHeight;
 461                 }
 462
 463                 copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
 464                                   rows, srcrowstride);
 465
 466                 _mesa_align_free(image->base.Data);
 467                 image->base.Data = 0;
 468         }
 469
 470         radeon_bo_unmap(mt->bo);
 471
 472         radeon_miptree_reference(mt, &image->mt);
 473 }
 474
 475 /**
 476  * Filter matching miptrees, and select one with the most of data.
 477  * @param[in] texObj radeon texture object
 478  * @param[in] firstLevel first texture level to check
 479  * @param[in] lastLevel last texture level to check
 480  */
 481 static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
 482                                                                                                                  unsigned firstLevel,
 483                                                                                                                  unsigned lastLevel)
 484 {
 485         const unsigned numLevels = lastLevel - firstLevel + 1;
 486         unsigned *mtSizes = calloc(numLevels, sizeof(unsigned));
 487         radeon_mipmap_tree **mts = calloc(numLevels, sizeof(radeon_mipmap_tree *));
 488         unsigned mtCount = 0;
 489         unsigned maxMtIndex = 0;
 490         radeon_mipmap_tree *tmp;
 491         unsigned int level;
 492         int i;
 493
 494         for (level = firstLevel; level <= lastLevel; ++level) {
 495                 radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]);
 496                 unsigned found = 0;
 497                 // TODO: why this hack??
 498                 if (!img)
 499                         break;
 500
 501                 if (!img->mt)
 502                         continue;
 503
 504                 for (i = 0; i < mtCount; ++i) {
 505                         if (mts[i] == img->mt) {
 506                                 found = 1;
 507                                 mtSizes[i] += img->mt->levels[img->base.Base.Level].size;
 508                                 break;
 509                         }
 510                 }
 511
 512                 if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) {
 513                         mtSizes[mtCount] = img->mt->levels[img->base.Base.Level].size;
 514                         mts[mtCount] = img->mt;
 515                         mtCount++;
 516                 }
 517         }
 518
 519         if (mtCount == 0) {
 520                 free(mtSizes);
 521                 free(mts);
 522                 return NULL;
 523         }
 524
 525         for (i = 1; i < mtCount; ++i) {
 526                 if (mtSizes[i] > mtSizes[maxMtIndex]) {
 527                         maxMtIndex = i;
 528                 }
 529         }
 530
 531         tmp = mts[maxMtIndex];
 532         free(mtSizes);
 533         free(mts);
 534
 535         return tmp;
 536 }
 537
 538 /**
 539  * Validate texture mipmap tree.
 540  * If individual images are stored in different mipmap trees
 541  * use the mipmap tree that has the most of the correct data.
 542  */
 543 int radeon_validate_texture_miptree(struct gl_context * ctx, struct gl_texture_object *texObj)
 544 {
 545         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 546         radeonTexObj *t = radeon_tex_obj(texObj);
 547
 548         if (t->validated || t->image_override) {
 549                 return GL_TRUE;
 550         }
 551
 552         if (texObj->Image[0][texObj->BaseLevel]->Border > 0)
 553                 return GL_FALSE;
 554
 555         _mesa_test_texobj_completeness(rmesa->glCtx, texObj);
 556         if (!texObj->_Complete) {
 557                 return GL_FALSE;
 558         }
 559
 560         calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod);
 561
 562         radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 563                         "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
 564                         __FUNCTION__, texObj ,t->minLod, t->maxLod);
 565
 566         radeon_mipmap_tree *dst_miptree;
 567         dst_miptree = get_biggest_matching_miptree(t, t->base.BaseLevel, t->base.MaxLevel);
 568
 569         radeon_miptree_unreference(&t->mt);
 570         if (!dst_miptree) {
 571                 radeon_try_alloc_miptree(rmesa, t);
 572                 radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 573                         "%s: No matching miptree found, allocated new one %p\n",
 574                         __FUNCTION__, t->mt);
 575
 576         } else {
 577                 radeon_miptree_reference(dst_miptree, &t->mt);
 578                 radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 579                         "%s: Using miptree %p\n", __FUNCTION__, t->mt);
 580         }
 581
 582         const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1;
 583         unsigned face, level;
 584         radeon_texture_image *img;
 585         /* Validate only the levels that will actually be used during rendering */
 586         for (face = 0; face < faces; ++face) {
 587                 for (level = t->minLod; level <= t->maxLod; ++level) {
 588                         img = get_radeon_texture_image(texObj->Image[face][level]);
 589
 590                         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 591                                 "Checking image level %d, face %d, mt %p ... ",
 592                                 level, face, img->mt);
 593
 594                         if (img->mt != t->mt) {
 595                                 radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 596                                         "MIGRATING\n");
 597
 598                                 struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo;
 599                                 if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) {
 600                                         radeon_firevertices(rmesa);
 601                                 }
 602                                 migrate_image_to_miptree(t->mt, img, face, level);
 603                         } else
 604                                 radeon_print(RADEON_TEXTURE, RADEON_TRACE, "OK\n");
 605                 }
 606         }
 607
 608         t->validated = GL_TRUE;
 609
 610         return GL_TRUE;
 611 }
 612
 613 uint32_t get_base_teximage_offset(radeonTexObj *texObj)
 614 {
 615         if (!texObj->mt) {
 616                 return 0;
 617         } else {
 618                 return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod);
 619         }
 620 }