2 * Copyright (C) 2009 Maciej Cencora.
3 * Copyright (C) 2008 Nicolai Haehnle.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon_mipmap_tree.h"
34 #include "main/simple_list.h"
35 #include "main/teximage.h"
36 #include "main/texobj.h"
37 #include "radeon_texture.h"
39 static unsigned get_aligned_compressed_row_stride(
44 const unsigned blockBytes
= _mesa_get_format_bytes(format
);
45 unsigned blockWidth
, blockHeight
;
48 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
50 /* Count number of blocks required to store the given width.
51 * And then multiple it with bytes required to store a block.
53 stride
= (width
+ blockWidth
- 1) / blockWidth
* blockBytes
;
55 /* Round the given minimum stride to the next full blocksize.
56 * (minStride + blockBytes - 1) / blockBytes * blockBytes
58 if ( stride
< minStride
)
59 stride
= (minStride
+ blockBytes
- 1) / blockBytes
* blockBytes
;
64 static unsigned get_compressed_image_size(
69 unsigned blockWidth
, blockHeight
;
71 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
73 return rowStride
* ((height
+ blockHeight
- 1) / blockHeight
);
76 static int find_next_power_of_two(GLuint value
)
90 * Compute sizes and fill in offset and blit information for the given
91 * image (determined by \p face and \p level).
93 * \param curOffset points to the offset at which the image is to be stored
94 * and is updated by this function according to the size of the image.
96 static void compute_tex_image_offset(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
,
97 GLuint face
, GLuint level
, GLuint
* curOffset
)
99 radeon_mipmap_level
*lvl
= &mt
->levels
[level
];
103 height
= find_next_power_of_two(lvl
->height
);
105 /* Find image size in bytes */
106 if (_mesa_is_format_compressed(mt
->mesaFormat
)) {
107 lvl
->rowstride
= get_aligned_compressed_row_stride(mt
->mesaFormat
, lvl
->width
, rmesa
->texture_compressed_row_align
);
108 lvl
->size
= get_compressed_image_size(mt
->mesaFormat
, lvl
->rowstride
, height
);
109 } else if (mt
->target
== GL_TEXTURE_RECTANGLE_NV
) {
110 row_align
= rmesa
->texture_rect_row_align
- 1;
111 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
112 lvl
->size
= lvl
->rowstride
* height
;
113 } else if (mt
->tilebits
& RADEON_TXO_MICRO_TILE
) {
114 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
115 * though the actual offset may be different (if texture is less than
116 * 32 bytes width) to the untiled case */
117 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) * 2 + 31) & ~31;
118 lvl
->size
= lvl
->rowstride
* ((height
+ 1) / 2) * lvl
->depth
;
120 row_align
= rmesa
->texture_row_align
- 1;
121 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
122 lvl
->size
= lvl
->rowstride
* height
* lvl
->depth
;
124 assert(lvl
->size
> 0);
126 /* All images are aligned to a 32-byte offset */
127 *curOffset
= (*curOffset
+ 0x1f) & ~0x1f;
128 lvl
->faces
[face
].offset
= *curOffset
;
129 *curOffset
+= lvl
->size
;
131 if (RADEON_DEBUG
& RADEON_TEXTURE
)
133 "level %d, face %d: rs:%d %dx%d at %d\n",
134 level
, face
, lvl
->rowstride
, lvl
->width
, height
, lvl
->faces
[face
].offset
);
137 static GLuint
minify(GLuint size
, GLuint levels
)
139 size
= size
>> levels
;
146 static void calculate_miptree_layout_r100(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
148 GLuint curOffset
, i
, face
, level
;
150 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
153 for(face
= 0; face
< mt
->faces
; face
++) {
155 for(i
= 0, level
= mt
->baseLevel
; i
< mt
->numLevels
; i
++, level
++) {
156 mt
->levels
[level
].valid
= 1;
157 mt
->levels
[level
].width
= minify(mt
->width0
, i
);
158 mt
->levels
[level
].height
= minify(mt
->height0
, i
);
159 mt
->levels
[level
].depth
= minify(mt
->depth0
, i
);
160 compute_tex_image_offset(rmesa
, mt
, face
, level
, &curOffset
);
164 /* Note the required size in memory */
165 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
168 static void calculate_miptree_layout_r300(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
170 GLuint curOffset
, i
, level
;
172 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
175 for(i
= 0, level
= mt
->baseLevel
; i
< mt
->numLevels
; i
++, level
++) {
178 mt
->levels
[level
].valid
= 1;
179 mt
->levels
[level
].width
= minify(mt
->width0
, i
);
180 mt
->levels
[level
].height
= minify(mt
->height0
, i
);
181 mt
->levels
[level
].depth
= minify(mt
->depth0
, i
);
183 for(face
= 0; face
< mt
->faces
; face
++)
184 compute_tex_image_offset(rmesa
, mt
, face
, level
, &curOffset
);
185 /* r600 cube levels seems to be aligned to 8 faces but
186 * we have separate register for 1'st level offset so add
187 * 2 image alignment after 1'st mip level */
188 if(rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R600
&&
189 mt
->target
== GL_TEXTURE_CUBE_MAP
&& level
>= 1)
190 curOffset
+= 2 * mt
->levels
[level
].size
;
193 /* Note the required size in memory */
194 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
198 * Create a new mipmap tree, calculate its layout and allocate memory.
200 static radeon_mipmap_tree
* radeon_miptree_create(radeonContextPtr rmesa
,
201 GLenum target
, gl_format mesaFormat
, GLuint baseLevel
, GLuint numLevels
,
202 GLuint width0
, GLuint height0
, GLuint depth0
, GLuint tilebits
)
204 radeon_mipmap_tree
*mt
= CALLOC_STRUCT(_radeon_mipmap_tree
);
206 mt
->mesaFormat
= mesaFormat
;
209 mt
->faces
= (target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
210 mt
->baseLevel
= baseLevel
;
211 mt
->numLevels
= numLevels
;
213 mt
->height0
= height0
;
215 mt
->tilebits
= tilebits
;
217 if (rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R300
)
218 calculate_miptree_layout_r300(rmesa
, mt
);
220 calculate_miptree_layout_r100(rmesa
, mt
);
222 mt
->bo
= radeon_bo_open(rmesa
->radeonScreen
->bom
,
223 0, mt
->totalsize
, 1024,
224 RADEON_GEM_DOMAIN_VRAM
,
230 void radeon_miptree_reference(radeon_mipmap_tree
*mt
, radeon_mipmap_tree
**ptr
)
235 assert(mt
->refcount
> 0);
240 void radeon_miptree_unreference(radeon_mipmap_tree
**ptr
)
242 radeon_mipmap_tree
*mt
= *ptr
;
246 assert(mt
->refcount
> 0);
250 radeon_bo_unref(mt
->bo
);
258 * Calculate min and max LOD for the given texture object.
259 * @param[in] tObj texture object whose LOD values to calculate
260 * @param[out] pminLod minimal LOD
261 * @param[out] pmaxLod maximal LOD
263 static void calculate_min_max_lod(struct gl_texture_object
*tObj
,
264 unsigned *pminLod
, unsigned *pmaxLod
)
267 /* Yes, this looks overly complicated, but it's all needed.
269 switch (tObj
->Target
) {
273 case GL_TEXTURE_CUBE_MAP
:
274 if (tObj
->MinFilter
== GL_NEAREST
|| tObj
->MinFilter
== GL_LINEAR
) {
275 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
277 minLod
= maxLod
= tObj
->BaseLevel
;
279 minLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MinLod
);
280 minLod
= MAX2(minLod
, tObj
->BaseLevel
);
281 minLod
= MIN2(minLod
, tObj
->MaxLevel
);
282 maxLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MaxLod
+ 0.5);
283 maxLod
= MIN2(maxLod
, tObj
->MaxLevel
);
284 maxLod
= MIN2(maxLod
, tObj
->Image
[0][minLod
]->MaxLog2
+ minLod
);
285 maxLod
= MAX2(maxLod
, minLod
); /* need at least one level */
288 case GL_TEXTURE_RECTANGLE_NV
:
289 case GL_TEXTURE_4D_SGIS
:
296 /* save these values */
302 * Checks whether the given miptree can hold the given texture image at the
303 * given face and level.
305 GLboolean
radeon_miptree_matches_image(radeon_mipmap_tree
*mt
,
306 struct gl_texture_image
*texImage
, GLuint face
, GLuint level
)
308 radeon_mipmap_level
*lvl
;
310 if (face
>= mt
->faces
)
313 if (texImage
->TexFormat
!= mt
->mesaFormat
)
316 lvl
= &mt
->levels
[level
];
318 lvl
->width
!= texImage
->Width
||
319 lvl
->height
!= texImage
->Height
||
320 lvl
->depth
!= texImage
->Depth
)
327 * Checks whether the given miptree has the right format to store the given texture object.
329 static GLboolean
radeon_miptree_matches_texture(radeon_mipmap_tree
*mt
, struct gl_texture_object
*texObj
)
331 struct gl_texture_image
*firstImage
;
333 radeon_mipmap_level
*mtBaseLevel
;
335 if (texObj
->BaseLevel
< mt
->baseLevel
)
338 mtBaseLevel
= &mt
->levels
[texObj
->BaseLevel
- mt
->baseLevel
];
339 firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
340 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, firstImage
->MaxLog2
+ 1);
342 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
343 fprintf(stderr
, "Checking if miptree %p matches texObj %p\n", mt
, texObj
);
344 fprintf(stderr
, "target %d vs %d\n", mt
->target
, texObj
->Target
);
345 fprintf(stderr
, "format %d vs %d\n", mt
->mesaFormat
, firstImage
->TexFormat
);
346 fprintf(stderr
, "numLevels %d vs %d\n", mt
->numLevels
, numLevels
);
347 fprintf(stderr
, "width0 %d vs %d\n", mtBaseLevel
->width
, firstImage
->Width
);
348 fprintf(stderr
, "height0 %d vs %d\n", mtBaseLevel
->height
, firstImage
->Height
);
349 fprintf(stderr
, "depth0 %d vs %d\n", mtBaseLevel
->depth
, firstImage
->Depth
);
350 if (mt
->target
== texObj
->Target
&&
351 mt
->mesaFormat
== firstImage
->TexFormat
&&
352 mt
->numLevels
>= numLevels
&&
353 mtBaseLevel
->width
== firstImage
->Width
&&
354 mtBaseLevel
->height
== firstImage
->Height
&&
355 mtBaseLevel
->depth
== firstImage
->Depth
) {
356 fprintf(stderr
, "MATCHED\n");
358 fprintf(stderr
, "NOT MATCHED\n");
362 return (mt
->target
== texObj
->Target
&&
363 mt
->mesaFormat
== firstImage
->TexFormat
&&
364 mt
->numLevels
>= numLevels
&&
365 mtBaseLevel
->width
== firstImage
->Width
&&
366 mtBaseLevel
->height
== firstImage
->Height
&&
367 mtBaseLevel
->depth
== firstImage
->Depth
);
371 * Try to allocate a mipmap tree for the given texture object.
372 * @param[in] rmesa radeon context
373 * @param[in] t radeon texture object
375 void radeon_try_alloc_miptree(radeonContextPtr rmesa
, radeonTexObj
*t
)
377 struct gl_texture_object
*texObj
= &t
->base
;
378 struct gl_texture_image
*texImg
= texObj
->Image
[0][texObj
->BaseLevel
];
386 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, texImg
->MaxLog2
+ 1);
388 t
->mt
= radeon_miptree_create(rmesa
, t
->base
.Target
,
389 texImg
->TexFormat
, texObj
->BaseLevel
,
390 numLevels
, texImg
->Width
, texImg
->Height
,
391 texImg
->Depth
, t
->tile_bits
);
395 radeon_miptree_image_offset(radeon_mipmap_tree
*mt
,
396 GLuint face
, GLuint level
)
398 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARB
)
399 return (mt
->levels
[level
].faces
[face
].offset
);
401 return mt
->levels
[level
].faces
[0].offset
;
405 * Ensure that the given image is stored in the given miptree from now on.
407 static void migrate_image_to_miptree(radeon_mipmap_tree
*mt
,
408 radeon_texture_image
*image
,
411 radeon_mipmap_level
*dstlvl
= &mt
->levels
[level
];
414 assert(image
->mt
!= mt
);
415 assert(dstlvl
->valid
);
416 assert(dstlvl
->width
== image
->base
.Width
);
417 assert(dstlvl
->height
== image
->base
.Height
);
418 assert(dstlvl
->depth
== image
->base
.Depth
);
420 radeon_bo_map(mt
->bo
, GL_TRUE
);
421 dest
= mt
->bo
->ptr
+ dstlvl
->faces
[face
].offset
;
424 /* Format etc. should match, so we really just need a memcpy().
425 * In fact, that memcpy() could be done by the hardware in many
426 * cases, provided that we have a proper memory manager.
428 assert(mt
->mesaFormat
== image
->base
.TexFormat
);
430 radeon_mipmap_level
*srclvl
= &image
->mt
->levels
[image
->mtlevel
];
432 /* TODO: bring back these assertions once the FBOs are fixed */
434 assert(image
->mtlevel
== level
);
435 assert(srclvl
->size
== dstlvl
->size
);
436 assert(srclvl
->rowstride
== dstlvl
->rowstride
);
439 radeon_bo_map(image
->mt
->bo
, GL_FALSE
);
442 image
->mt
->bo
->ptr
+ srclvl
->faces
[face
].offset
,
444 radeon_bo_unmap(image
->mt
->bo
);
446 radeon_miptree_unreference(&image
->mt
);
447 } else if (image
->base
.Data
) {
448 /* This condition should be removed, it's here to workaround
449 * a segfault when mapping textures during software fallbacks.
451 const uint32_t srcrowstride
= _mesa_format_row_stride(image
->base
.TexFormat
, image
->base
.Width
);
452 uint32_t rows
= image
->base
.Height
* image
->base
.Depth
;
454 if (_mesa_is_format_compressed(image
->base
.TexFormat
)) {
455 uint32_t blockWidth
, blockHeight
;
456 _mesa_get_format_block_size(image
->base
.TexFormat
, &blockWidth
, &blockHeight
);
457 rows
= (rows
+ blockHeight
- 1) / blockHeight
;
460 copy_rows(dest
, dstlvl
->rowstride
, image
->base
.Data
, srcrowstride
,
463 _mesa_free_texmemory(image
->base
.Data
);
464 image
->base
.Data
= 0;
467 radeon_bo_unmap(mt
->bo
);
469 radeon_miptree_reference(mt
, &image
->mt
);
470 image
->mtface
= face
;
471 image
->mtlevel
= level
;
475 * Filter matching miptrees, and select one with the most of data.
476 * @param[in] texObj radeon texture object
477 * @param[in] firstLevel first texture level to check
478 * @param[in] lastLevel last texture level to check
480 static radeon_mipmap_tree
* get_biggest_matching_miptree(radeonTexObj
*texObj
,
484 const unsigned numLevels
= lastLevel
- firstLevel
+ 1;
485 unsigned *mtSizes
= calloc(numLevels
, sizeof(unsigned));
486 radeon_mipmap_tree
**mts
= calloc(numLevels
, sizeof(radeon_mipmap_tree
*));
487 unsigned mtCount
= 0;
488 unsigned maxMtIndex
= 0;
489 radeon_mipmap_tree
*tmp
;
491 for (unsigned level
= firstLevel
; level
<= lastLevel
; ++level
) {
492 radeon_texture_image
*img
= get_radeon_texture_image(texObj
->base
.Image
[0][level
]);
494 // TODO: why this hack??
501 for (int i
= 0; i
< mtCount
; ++i
) {
502 if (mts
[i
] == img
->mt
) {
504 mtSizes
[i
] += img
->mt
->levels
[img
->mtlevel
].size
;
509 if (!found
&& radeon_miptree_matches_texture(img
->mt
, &texObj
->base
)) {
510 mtSizes
[mtCount
] = img
->mt
->levels
[img
->mtlevel
].size
;
511 mts
[mtCount
] = img
->mt
;
520 for (int i
= 1; i
< mtCount
; ++i
) {
521 if (mtSizes
[i
] > mtSizes
[maxMtIndex
]) {
526 tmp
= mts
[maxMtIndex
];
534 * Validate texture mipmap tree.
535 * If individual images are stored in different mipmap trees
536 * use the mipmap tree that has the most of the correct data.
538 int radeon_validate_texture_miptree(GLcontext
* ctx
, struct gl_texture_object
*texObj
)
540 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
541 radeonTexObj
*t
= radeon_tex_obj(texObj
);
543 if (t
->validated
|| t
->image_override
) {
547 if (texObj
->Image
[0][texObj
->BaseLevel
]->Border
> 0)
550 _mesa_test_texobj_completeness(rmesa
->glCtx
, texObj
);
551 if (!texObj
->_Complete
) {
555 calculate_min_max_lod(&t
->base
, &t
->minLod
, &t
->maxLod
);
557 if (RADEON_DEBUG
& RADEON_TEXTURE
)
558 fprintf(stderr
, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
559 __FUNCTION__
, texObj
,t
->minLod
, t
->maxLod
);
561 radeon_mipmap_tree
*dst_miptree
;
562 dst_miptree
= get_biggest_matching_miptree(t
, t
->minLod
, t
->maxLod
);
565 radeon_miptree_unreference(&t
->mt
);
566 radeon_try_alloc_miptree(rmesa
, t
);
568 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
569 fprintf(stderr
, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__
, t
->mt
);
571 } else if (RADEON_DEBUG
& RADEON_TEXTURE
) {
572 fprintf(stderr
, "%s: Using miptree %p\n", __FUNCTION__
, t
->mt
);
575 const unsigned faces
= texObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 : 1;
576 unsigned face
, level
;
577 radeon_texture_image
*img
;
578 /* Validate only the levels that will actually be used during rendering */
579 for (face
= 0; face
< faces
; ++face
) {
580 for (level
= t
->minLod
; level
<= t
->maxLod
; ++level
) {
581 img
= get_radeon_texture_image(texObj
->Image
[face
][level
]);
583 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
584 fprintf(stderr
, "Checking image level %d, face %d, mt %p ... ", level
, face
, img
->mt
);
587 if (img
->mt
!= dst_miptree
) {
588 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
589 fprintf(stderr
, "MIGRATING\n");
591 struct radeon_bo
*src_bo
= (img
->mt
) ? img
->mt
->bo
: img
->bo
;
592 if (src_bo
&& radeon_bo_is_referenced_by_cs(src_bo
, rmesa
->cmdbuf
.cs
)) {
593 radeon_firevertices(rmesa
);
595 migrate_image_to_miptree(dst_miptree
, img
, face
, level
);
596 } else if (RADEON_DEBUG
& RADEON_TEXTURE
) {
597 fprintf(stderr
, "OK\n");
602 t
->validated
= GL_TRUE
;
607 uint32_t get_base_teximage_offset(radeonTexObj
*texObj
)
612 return radeon_miptree_image_offset(texObj
->mt
, 0, texObj
->minLod
);