r200/r300: swtcl fixups to use old dma buffers on top of BOs
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.c
1 /*
2 * Copyright (C) 2008 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "radeon_mipmap_tree.h"
29
30 #include <errno.h>
31 #include <unistd.h>
32
33 #include "main/simple_list.h"
34 #include "main/texcompress.h"
35 #include "main/texformat.h"
36
37 #include "radeon_buffer.h"
38
39 static GLuint radeon_compressed_texture_size(GLcontext *ctx,
40 GLsizei width, GLsizei height, GLsizei depth,
41 GLuint mesaFormat)
42 {
43 GLuint size = _mesa_compressed_texture_size(ctx, width, height, depth, mesaFormat);
44
45 if (mesaFormat == MESA_FORMAT_RGB_DXT1 ||
46 mesaFormat == MESA_FORMAT_RGBA_DXT1) {
47 if (width + 3 < 8) /* width one block */
48 size = size * 4;
49 else if (width + 3 < 16)
50 size = size * 2;
51 } else {
52 /* DXT3/5, 16 bytes per block */
53 // WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n");
54 if (width + 3 < 8)
55 size = size * 2;
56 }
57
58 return size;
59 }
60
61 /**
62 * Compute sizes and fill in offset and blit information for the given
63 * image (determined by \p face and \p level).
64 *
65 * \param curOffset points to the offset at which the image is to be stored
66 * and is updated by this function according to the size of the image.
67 */
68 static void compute_tex_image_offset(radeon_mipmap_tree *mt,
69 GLuint face, GLuint level, GLuint* curOffset)
70 {
71 radeon_mipmap_level *lvl = &mt->levels[level];
72
73 /* Find image size in bytes */
74 if (mt->compressed) {
75 /* TODO: Is this correct? Need test cases for compressed textures! */
76 GLuint align;
77
78 if (mt->target == GL_TEXTURE_RECTANGLE_NV)
79 align = 64 / mt->bpp;
80 else
81 align = 32 / mt->bpp;
82 lvl->rowstride = (lvl->width + align - 1) & ~(align - 1);
83 lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
84 lvl->width, lvl->height, lvl->depth, mt->compressed);
85 } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
86 lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
87 lvl->size = lvl->rowstride * lvl->height;
88 } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
89 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
90 * though the actual offset may be different (if texture is less than
91 * 32 bytes width) to the untiled case */
92 lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
93 lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
94 } else {
95 lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
96 lvl->size = lvl->rowstride * lvl->height * lvl->depth;
97 }
98 assert(lvl->size > 0);
99
100 /* All images are aligned to a 32-byte offset */
101 *curOffset = (*curOffset + 0x1f) & ~0x1f;
102 lvl->faces[face].offset = *curOffset;
103 *curOffset += lvl->size;
104 }
105
106 static GLuint minify(GLuint size, GLuint levels)
107 {
108 size = size >> levels;
109 if (size < 1)
110 size = 1;
111 return size;
112 }
113
114 static void calculate_miptree_layout(radeon_mipmap_tree *mt)
115 {
116 GLuint curOffset;
117 GLuint numLevels;
118 GLuint i;
119
120 numLevels = mt->lastLevel - mt->firstLevel + 1;
121 assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS);
122
123 curOffset = 0;
124 for(i = 0; i < numLevels; i++) {
125 GLuint face;
126
127 mt->levels[i].width = minify(mt->width0, i);
128 mt->levels[i].height = minify(mt->height0, i);
129 mt->levels[i].depth = minify(mt->depth0, i);
130
131 for(face = 0; face < mt->faces; face++)
132 compute_tex_image_offset(mt, face, i, &curOffset);
133 }
134
135 /* Note the required size in memory */
136 mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
137 }
138
139
140 /**
141 * Create a new mipmap tree, calculate its layout and allocate memory.
142 */
143 radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *t,
144 GLenum target, GLuint firstLevel, GLuint lastLevel,
145 GLuint width0, GLuint height0, GLuint depth0,
146 GLuint bpp, GLuint tilebits, GLuint compressed)
147 {
148 radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
149
150 mt->radeon = rmesa;
151 mt->refcount = 1;
152 mt->t = t;
153 mt->target = target;
154 mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
155 mt->firstLevel = firstLevel;
156 mt->lastLevel = lastLevel;
157 mt->width0 = width0;
158 mt->height0 = height0;
159 mt->depth0 = depth0;
160 mt->bpp = bpp;
161 mt->tilebits = tilebits;
162 mt->compressed = compressed;
163
164 calculate_miptree_layout(mt);
165
166 mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
167 0, mt->totalsize, 1024,
168 RADEON_GEM_DOMAIN_VRAM,
169 0);
170
171 return mt;
172 }
173
174 void radeon_miptree_reference(radeon_mipmap_tree *mt)
175 {
176 mt->refcount++;
177 assert(mt->refcount > 0);
178 }
179
180 void radeon_miptree_unreference(radeon_mipmap_tree *mt)
181 {
182 if (!mt)
183 return;
184
185 assert(mt->refcount > 0);
186 mt->refcount--;
187 if (!mt->refcount) {
188 radeon_bo_unref(mt->bo);
189 free(mt);
190 }
191 }
192
193
194 static void calculate_first_last_level(struct gl_texture_object *tObj,
195 GLuint *pfirstLevel, GLuint *plastLevel)
196 {
197 const struct gl_texture_image * const baseImage =
198 tObj->Image[0][tObj->BaseLevel];
199
200 /* These must be signed values. MinLod and MaxLod can be negative numbers,
201 * and having firstLevel and lastLevel as signed prevents the need for
202 * extra sign checks.
203 */
204 int firstLevel;
205 int lastLevel;
206
207 /* Yes, this looks overly complicated, but it's all needed.
208 */
209 switch (tObj->Target) {
210 case GL_TEXTURE_1D:
211 case GL_TEXTURE_2D:
212 case GL_TEXTURE_3D:
213 case GL_TEXTURE_CUBE_MAP:
214 if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
215 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
216 */
217 firstLevel = lastLevel = tObj->BaseLevel;
218 } else {
219 firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5);
220 firstLevel = MAX2(firstLevel, tObj->BaseLevel);
221 firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2);
222 lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
223 lastLevel = MAX2(lastLevel, tObj->BaseLevel);
224 lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
225 lastLevel = MIN2(lastLevel, tObj->MaxLevel);
226 lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
227 }
228 break;
229 case GL_TEXTURE_RECTANGLE_NV:
230 case GL_TEXTURE_4D_SGIS:
231 firstLevel = lastLevel = 0;
232 break;
233 default:
234 return;
235 }
236
237 /* save these values */
238 *pfirstLevel = firstLevel;
239 *plastLevel = lastLevel;
240 }
241
242
243 /**
244 * Checks whether the given miptree can hold the given texture image at the
245 * given face and level.
246 */
247 GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
248 struct gl_texture_image *texImage, GLuint face, GLuint level)
249 {
250 radeon_mipmap_level *lvl;
251
252 if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel)
253 return GL_FALSE;
254
255 if (texImage->TexFormat->TexelBytes != mt->bpp)
256 return GL_FALSE;
257
258 lvl = &mt->levels[level - mt->firstLevel];
259 if (lvl->width != texImage->Width ||
260 lvl->height != texImage->Height ||
261 lvl->depth != texImage->Depth)
262 return GL_FALSE;
263
264 return GL_TRUE;
265 }
266
267
268 /**
269 * Checks whether the given miptree has the right format to store the given texture object.
270 */
271 GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj)
272 {
273 struct gl_texture_image *firstImage;
274 GLuint compressed;
275 GLuint numfaces = 1;
276 GLuint firstLevel, lastLevel;
277
278 calculate_first_last_level(texObj, &firstLevel, &lastLevel);
279 if (texObj->Target == GL_TEXTURE_CUBE_MAP)
280 numfaces = 6;
281
282 firstImage = texObj->Image[0][firstLevel];
283 compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0;
284
285 return (mt->firstLevel == firstLevel &&
286 mt->lastLevel == lastLevel &&
287 mt->width0 == firstImage->Width &&
288 mt->height0 == firstImage->Height &&
289 mt->depth0 == firstImage->Depth &&
290 mt->bpp == firstImage->TexFormat->TexelBytes &&
291 mt->compressed == compressed);
292 }
293
294
295 /**
296 * Try to allocate a mipmap tree for the given texture that will fit the
297 * given image in the given position.
298 */
299 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
300 struct gl_texture_image *texImage, GLuint face, GLuint level)
301 {
302 GLuint compressed = texImage->IsCompressed ? texImage->TexFormat->MesaFormat : 0;
303 GLuint numfaces = 1;
304 GLuint firstLevel, lastLevel;
305
306 assert(!t->mt);
307
308 calculate_first_last_level(&t->base, &firstLevel, &lastLevel);
309 if (t->base.Target == GL_TEXTURE_CUBE_MAP)
310 numfaces = 6;
311
312 if (level != firstLevel || face >= numfaces)
313 return;
314
315 t->mt = radeon_miptree_create(rmesa, t, t->base.Target,
316 firstLevel, lastLevel,
317 texImage->Width, texImage->Height, texImage->Depth,
318 texImage->TexFormat->TexelBytes, t->tile_bits, compressed);
319 }