2 * Copyright (C) 2009 Maciej Cencora.
3 * Copyright (C) 2008 Nicolai Haehnle.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon_mipmap_tree.h"
34 #include "main/simple_list.h"
35 #include "main/teximage.h"
36 #include "main/texobj.h"
37 #include "main/enums.h"
38 #include "radeon_texture.h"
40 static unsigned get_aligned_compressed_row_stride(
45 const unsigned blockBytes
= _mesa_get_format_bytes(format
);
46 unsigned blockWidth
, blockHeight
;
49 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
51 /* Count number of blocks required to store the given width.
52 * And then multiple it with bytes required to store a block.
54 stride
= (width
+ blockWidth
- 1) / blockWidth
* blockBytes
;
56 /* Round the given minimum stride to the next full blocksize.
57 * (minStride + blockBytes - 1) / blockBytes * blockBytes
59 if ( stride
< minStride
)
60 stride
= (minStride
+ blockBytes
- 1) / blockBytes
* blockBytes
;
62 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
63 "%s width %u, minStride %u, block(bytes %u, width %u):"
65 __func__
, width
, minStride
,
66 blockBytes
, blockWidth
,
72 static unsigned get_compressed_image_size(
77 unsigned blockWidth
, blockHeight
;
79 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
81 return rowStride
* ((height
+ blockHeight
- 1) / blockHeight
);
85 * Compute sizes and fill in offset and blit information for the given
86 * image (determined by \p face and \p level).
88 * \param curOffset points to the offset at which the image is to be stored
89 * and is updated by this function according to the size of the image.
91 static void compute_tex_image_offset(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
,
92 GLuint face
, GLuint level
, GLuint
* curOffset
)
94 radeon_mipmap_level
*lvl
= &mt
->levels
[level
];
98 height
= _mesa_next_pow_two_32(lvl
->height
);
100 /* Find image size in bytes */
101 if (_mesa_is_format_compressed(mt
->mesaFormat
)) {
102 lvl
->rowstride
= get_aligned_compressed_row_stride(mt
->mesaFormat
, lvl
->width
, rmesa
->texture_compressed_row_align
);
103 lvl
->size
= get_compressed_image_size(mt
->mesaFormat
, lvl
->rowstride
, height
);
104 } else if (mt
->target
== GL_TEXTURE_RECTANGLE_NV
) {
105 row_align
= rmesa
->texture_rect_row_align
- 1;
106 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
107 lvl
->size
= lvl
->rowstride
* height
;
108 } else if (mt
->tilebits
& RADEON_TXO_MICRO_TILE
) {
109 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
110 * though the actual offset may be different (if texture is less than
111 * 32 bytes width) to the untiled case */
112 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) * 2 + 31) & ~31;
113 lvl
->size
= lvl
->rowstride
* ((height
+ 1) / 2) * lvl
->depth
;
115 row_align
= rmesa
->texture_row_align
- 1;
116 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
117 lvl
->size
= lvl
->rowstride
* height
* lvl
->depth
;
119 assert(lvl
->size
> 0);
121 /* All images are aligned to a 32-byte offset */
122 *curOffset
= (*curOffset
+ 0x1f) & ~0x1f;
123 lvl
->faces
[face
].offset
= *curOffset
;
124 *curOffset
+= lvl
->size
;
126 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
127 "%s(%p) level %d, face %d: rs:%d %dx%d at %d\n",
130 lvl
->rowstride
, lvl
->width
, height
, lvl
->faces
[face
].offset
);
133 static GLuint
minify(GLuint size
, GLuint levels
)
135 size
= size
>> levels
;
142 static void calculate_miptree_layout_r100(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
144 GLuint curOffset
, i
, face
, level
;
146 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
149 for(face
= 0; face
< mt
->faces
; face
++) {
151 for(i
= 0, level
= mt
->baseLevel
; i
< mt
->numLevels
; i
++, level
++) {
152 mt
->levels
[level
].valid
= 1;
153 mt
->levels
[level
].width
= minify(mt
->width0
, i
);
154 mt
->levels
[level
].height
= minify(mt
->height0
, i
);
155 mt
->levels
[level
].depth
= minify(mt
->depth0
, i
);
156 compute_tex_image_offset(rmesa
, mt
, face
, level
, &curOffset
);
160 /* Note the required size in memory */
161 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
163 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
164 "%s(%p, %p) total size %d\n",
165 __func__
, rmesa
, mt
, mt
->totalsize
);
168 static void calculate_miptree_layout_r300(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
170 GLuint curOffset
, i
, level
;
172 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
175 for(i
= 0, level
= mt
->baseLevel
; i
< mt
->numLevels
; i
++, level
++) {
178 mt
->levels
[level
].valid
= 1;
179 mt
->levels
[level
].width
= minify(mt
->width0
, i
);
180 mt
->levels
[level
].height
= minify(mt
->height0
, i
);
181 mt
->levels
[level
].depth
= minify(mt
->depth0
, i
);
183 for(face
= 0; face
< mt
->faces
; face
++)
184 compute_tex_image_offset(rmesa
, mt
, face
, level
, &curOffset
);
185 /* r600 cube levels seems to be aligned to 8 faces but
186 * we have separate register for 1'st level offset so add
187 * 2 image alignment after 1'st mip level */
188 if(rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R600
&&
189 mt
->target
== GL_TEXTURE_CUBE_MAP
&& level
>= 1)
190 curOffset
+= 2 * mt
->levels
[level
].size
;
193 /* Note the required size in memory */
194 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
196 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
197 "%s(%p, %p) total size %d\n",
198 __func__
, rmesa
, mt
, mt
->totalsize
);
202 * Create a new mipmap tree, calculate its layout and allocate memory.
204 static radeon_mipmap_tree
* radeon_miptree_create(radeonContextPtr rmesa
,
205 GLenum target
, gl_format mesaFormat
, GLuint baseLevel
, GLuint numLevels
,
206 GLuint width0
, GLuint height0
, GLuint depth0
, GLuint tilebits
)
208 radeon_mipmap_tree
*mt
= CALLOC_STRUCT(_radeon_mipmap_tree
);
210 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
211 "%s(%p) new tree is %p.\n",
212 __func__
, rmesa
, mt
);
214 mt
->mesaFormat
= mesaFormat
;
217 mt
->faces
= (target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
218 mt
->baseLevel
= baseLevel
;
219 mt
->numLevels
= numLevels
;
221 mt
->height0
= height0
;
223 mt
->tilebits
= tilebits
;
225 if (rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R300
)
226 calculate_miptree_layout_r300(rmesa
, mt
);
228 calculate_miptree_layout_r100(rmesa
, mt
);
230 mt
->bo
= radeon_bo_open(rmesa
->radeonScreen
->bom
,
231 0, mt
->totalsize
, 1024,
232 RADEON_GEM_DOMAIN_VRAM
,
238 void radeon_miptree_reference(radeon_mipmap_tree
*mt
, radeon_mipmap_tree
**ptr
)
243 assert(mt
->refcount
> 0);
248 void radeon_miptree_unreference(radeon_mipmap_tree
**ptr
)
250 radeon_mipmap_tree
*mt
= *ptr
;
254 assert(mt
->refcount
> 0);
258 radeon_bo_unref(mt
->bo
);
266 * Calculate min and max LOD for the given texture object.
267 * @param[in] tObj texture object whose LOD values to calculate
268 * @param[out] pminLod minimal LOD
269 * @param[out] pmaxLod maximal LOD
271 static void calculate_min_max_lod(struct gl_texture_object
*tObj
,
272 unsigned *pminLod
, unsigned *pmaxLod
)
275 /* Yes, this looks overly complicated, but it's all needed.
277 switch (tObj
->Target
) {
281 case GL_TEXTURE_CUBE_MAP
:
282 if (tObj
->MinFilter
== GL_NEAREST
|| tObj
->MinFilter
== GL_LINEAR
) {
283 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
285 minLod
= maxLod
= tObj
->BaseLevel
;
287 minLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MinLod
);
288 minLod
= MAX2(minLod
, tObj
->BaseLevel
);
289 minLod
= MIN2(minLod
, tObj
->MaxLevel
);
290 maxLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MaxLod
+ 0.5);
291 maxLod
= MIN2(maxLod
, tObj
->MaxLevel
);
292 maxLod
= MIN2(maxLod
, tObj
->Image
[0][minLod
]->MaxLog2
+ minLod
);
293 maxLod
= MAX2(maxLod
, minLod
); /* need at least one level */
296 case GL_TEXTURE_RECTANGLE_NV
:
297 case GL_TEXTURE_4D_SGIS
:
304 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
305 "%s(%p) target %s, min %d, max %d.\n",
307 _mesa_lookup_enum_by_nr(tObj
->Target
),
310 /* save these values */
316 * Checks whether the given miptree can hold the given texture image at the
317 * given face and level.
319 GLboolean
radeon_miptree_matches_image(radeon_mipmap_tree
*mt
,
320 struct gl_texture_image
*texImage
, GLuint face
, GLuint level
)
322 radeon_mipmap_level
*lvl
;
324 if (face
>= mt
->faces
)
327 if (texImage
->TexFormat
!= mt
->mesaFormat
)
330 lvl
= &mt
->levels
[level
];
332 lvl
->width
!= texImage
->Width
||
333 lvl
->height
!= texImage
->Height
||
334 lvl
->depth
!= texImage
->Depth
)
341 * Checks whether the given miptree has the right format to store the given texture object.
343 static GLboolean
radeon_miptree_matches_texture(radeon_mipmap_tree
*mt
, struct gl_texture_object
*texObj
)
345 struct gl_texture_image
*firstImage
;
347 radeon_mipmap_level
*mtBaseLevel
;
349 if (texObj
->BaseLevel
< mt
->baseLevel
)
352 mtBaseLevel
= &mt
->levels
[texObj
->BaseLevel
- mt
->baseLevel
];
353 firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
354 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, firstImage
->MaxLog2
+ 1);
356 if (radeon_is_debug_enabled(RADEON_TEXTURE
,RADEON_TRACE
)) {
357 fprintf(stderr
, "Checking if miptree %p matches texObj %p\n", mt
, texObj
);
358 fprintf(stderr
, "target %d vs %d\n", mt
->target
, texObj
->Target
);
359 fprintf(stderr
, "format %d vs %d\n", mt
->mesaFormat
, firstImage
->TexFormat
);
360 fprintf(stderr
, "numLevels %d vs %d\n", mt
->numLevels
, numLevels
);
361 fprintf(stderr
, "width0 %d vs %d\n", mtBaseLevel
->width
, firstImage
->Width
);
362 fprintf(stderr
, "height0 %d vs %d\n", mtBaseLevel
->height
, firstImage
->Height
);
363 fprintf(stderr
, "depth0 %d vs %d\n", mtBaseLevel
->depth
, firstImage
->Depth
);
364 if (mt
->target
== texObj
->Target
&&
365 mt
->mesaFormat
== firstImage
->TexFormat
&&
366 mt
->numLevels
>= numLevels
&&
367 mtBaseLevel
->width
== firstImage
->Width
&&
368 mtBaseLevel
->height
== firstImage
->Height
&&
369 mtBaseLevel
->depth
== firstImage
->Depth
) {
370 fprintf(stderr
, "MATCHED\n");
372 fprintf(stderr
, "NOT MATCHED\n");
376 return (mt
->target
== texObj
->Target
&&
377 mt
->mesaFormat
== firstImage
->TexFormat
&&
378 mt
->numLevels
>= numLevels
&&
379 mtBaseLevel
->width
== firstImage
->Width
&&
380 mtBaseLevel
->height
== firstImage
->Height
&&
381 mtBaseLevel
->depth
== firstImage
->Depth
);
385 * Try to allocate a mipmap tree for the given texture object.
386 * @param[in] rmesa radeon context
387 * @param[in] t radeon texture object
389 void radeon_try_alloc_miptree(radeonContextPtr rmesa
, radeonTexObj
*t
)
391 struct gl_texture_object
*texObj
= &t
->base
;
392 struct gl_texture_image
*texImg
= texObj
->Image
[0][texObj
->BaseLevel
];
398 radeon_warning("%s(%p) No image in given texture object(%p).\n",
404 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, texImg
->MaxLog2
+ 1);
406 t
->mt
= radeon_miptree_create(rmesa
, t
->base
.Target
,
407 texImg
->TexFormat
, texObj
->BaseLevel
,
408 numLevels
, texImg
->Width
, texImg
->Height
,
409 texImg
->Depth
, t
->tile_bits
);
413 radeon_miptree_image_offset(radeon_mipmap_tree
*mt
,
414 GLuint face
, GLuint level
)
416 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARB
)
417 return (mt
->levels
[level
].faces
[face
].offset
);
419 return mt
->levels
[level
].faces
[0].offset
;
423 * Ensure that the given image is stored in the given miptree from now on.
425 static void migrate_image_to_miptree(radeon_mipmap_tree
*mt
,
426 radeon_texture_image
*image
,
429 radeon_mipmap_level
*dstlvl
= &mt
->levels
[level
];
432 assert(image
->mt
!= mt
);
433 assert(dstlvl
->valid
);
434 assert(dstlvl
->width
== image
->base
.Width
);
435 assert(dstlvl
->height
== image
->base
.Height
);
436 assert(dstlvl
->depth
== image
->base
.Depth
);
438 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
439 "%s miptree %p, image %p, face %d, level %d.\n",
440 __func__
, mt
, image
, face
, level
);
442 radeon_bo_map(mt
->bo
, GL_TRUE
);
443 dest
= mt
->bo
->ptr
+ dstlvl
->faces
[face
].offset
;
446 /* Format etc. should match, so we really just need a memcpy().
447 * In fact, that memcpy() could be done by the hardware in many
448 * cases, provided that we have a proper memory manager.
450 assert(mt
->mesaFormat
== image
->base
.TexFormat
);
452 radeon_mipmap_level
*srclvl
= &image
->mt
->levels
[image
->mtlevel
];
454 /* TODO: bring back these assertions once the FBOs are fixed */
456 assert(image
->mtlevel
== level
);
457 assert(srclvl
->size
== dstlvl
->size
);
458 assert(srclvl
->rowstride
== dstlvl
->rowstride
);
461 radeon_bo_map(image
->mt
->bo
, GL_FALSE
);
464 image
->mt
->bo
->ptr
+ srclvl
->faces
[face
].offset
,
466 radeon_bo_unmap(image
->mt
->bo
);
468 radeon_miptree_unreference(&image
->mt
);
469 } else if (image
->base
.Data
) {
470 /* This condition should be removed, it's here to workaround
471 * a segfault when mapping textures during software fallbacks.
473 radeon_print(RADEON_FALLBACKS
, RADEON_IMPORTANT
,
474 "%s Trying to map texture in sowftware fallback.\n",
476 const uint32_t srcrowstride
= _mesa_format_row_stride(image
->base
.TexFormat
, image
->base
.Width
);
477 uint32_t rows
= image
->base
.Height
* image
->base
.Depth
;
479 if (_mesa_is_format_compressed(image
->base
.TexFormat
)) {
480 uint32_t blockWidth
, blockHeight
;
481 _mesa_get_format_block_size(image
->base
.TexFormat
, &blockWidth
, &blockHeight
);
482 rows
= (rows
+ blockHeight
- 1) / blockHeight
;
485 copy_rows(dest
, dstlvl
->rowstride
, image
->base
.Data
, srcrowstride
,
488 _mesa_free_texmemory(image
->base
.Data
);
489 image
->base
.Data
= 0;
492 radeon_bo_unmap(mt
->bo
);
494 radeon_miptree_reference(mt
, &image
->mt
);
495 image
->mtface
= face
;
496 image
->mtlevel
= level
;
500 * Filter matching miptrees, and select one with the most of data.
501 * @param[in] texObj radeon texture object
502 * @param[in] firstLevel first texture level to check
503 * @param[in] lastLevel last texture level to check
505 static radeon_mipmap_tree
* get_biggest_matching_miptree(radeonTexObj
*texObj
,
509 const unsigned numLevels
= lastLevel
- firstLevel
+ 1;
510 unsigned *mtSizes
= calloc(numLevels
, sizeof(unsigned));
511 radeon_mipmap_tree
**mts
= calloc(numLevels
, sizeof(radeon_mipmap_tree
*));
512 unsigned mtCount
= 0;
513 unsigned maxMtIndex
= 0;
514 radeon_mipmap_tree
*tmp
;
516 for (unsigned level
= firstLevel
; level
<= lastLevel
; ++level
) {
517 radeon_texture_image
*img
= get_radeon_texture_image(texObj
->base
.Image
[0][level
]);
519 // TODO: why this hack??
526 for (int i
= 0; i
< mtCount
; ++i
) {
527 if (mts
[i
] == img
->mt
) {
529 mtSizes
[i
] += img
->mt
->levels
[img
->mtlevel
].size
;
534 if (!found
&& radeon_miptree_matches_texture(img
->mt
, &texObj
->base
)) {
535 mtSizes
[mtCount
] = img
->mt
->levels
[img
->mtlevel
].size
;
536 mts
[mtCount
] = img
->mt
;
545 for (int i
= 1; i
< mtCount
; ++i
) {
546 if (mtSizes
[i
] > mtSizes
[maxMtIndex
]) {
551 tmp
= mts
[maxMtIndex
];
559 * Validate texture mipmap tree.
560 * If individual images are stored in different mipmap trees
561 * use the mipmap tree that has the most of the correct data.
563 int radeon_validate_texture_miptree(GLcontext
* ctx
, struct gl_texture_object
*texObj
)
565 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
566 radeonTexObj
*t
= radeon_tex_obj(texObj
);
568 if (t
->validated
|| t
->image_override
) {
572 if (texObj
->Image
[0][texObj
->BaseLevel
]->Border
> 0)
575 _mesa_test_texobj_completeness(rmesa
->glCtx
, texObj
);
576 if (!texObj
->_Complete
) {
580 calculate_min_max_lod(&t
->base
, &t
->minLod
, &t
->maxLod
);
582 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
583 "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
584 __FUNCTION__
, texObj
,t
->minLod
, t
->maxLod
);
586 radeon_mipmap_tree
*dst_miptree
;
587 dst_miptree
= get_biggest_matching_miptree(t
, t
->minLod
, t
->maxLod
);
590 radeon_miptree_unreference(&t
->mt
);
591 radeon_try_alloc_miptree(rmesa
, t
);
593 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
594 "%s: No matching miptree found, allocated new one %p\n",
595 __FUNCTION__
, t
->mt
);
598 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
599 "%s: Using miptree %p\n", __FUNCTION__
, t
->mt
);
602 const unsigned faces
= texObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 : 1;
603 unsigned face
, level
;
604 radeon_texture_image
*img
;
605 /* Validate only the levels that will actually be used during rendering */
606 for (face
= 0; face
< faces
; ++face
) {
607 for (level
= t
->minLod
; level
<= t
->maxLod
; ++level
) {
608 img
= get_radeon_texture_image(texObj
->Image
[face
][level
]);
610 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
611 "Checking image level %d, face %d, mt %p ... ",
612 level
, face
, img
->mt
);
614 if (img
->mt
!= dst_miptree
) {
615 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
618 struct radeon_bo
*src_bo
= (img
->mt
) ? img
->mt
->bo
: img
->bo
;
619 if (src_bo
&& radeon_bo_is_referenced_by_cs(src_bo
, rmesa
->cmdbuf
.cs
)) {
620 radeon_firevertices(rmesa
);
622 migrate_image_to_miptree(dst_miptree
, img
, face
, level
);
624 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
, "OK\n");
628 t
->validated
= GL_TRUE
;
633 uint32_t get_base_teximage_offset(radeonTexObj
*texObj
)
638 return radeon_miptree_image_offset(texObj
->mt
, 0, texObj
->minLod
);