1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
5 Tungsten Graphics Inc, Cedar Park, TX.
9 Permission is hereby granted, free of charge, to any person obtaining a
10 copy of this software and associated documentation files (the "Software"),
11 to deal in the Software without restriction, including without limitation
12 on the rights to use, copy, modify, merge, publish, distribute, sub
13 license, and/or sell copies of the Software, and to permit persons to whom
14 the Software is furnished to do so, subject to the following conditions:
16 The above copyright notice and this permission notice (including the next
17 paragraph) shall be included in all copies or substantial portions of the
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
26 USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "radeon_context.h"
40 #include "radeon_ioctl.h"
41 #include "radeon_sanity.h"
43 /* Set this '1' to get more verbiage.
45 #define MORE_VERBOSE 1
48 #define VERBOSE (RADEON_DEBUG & DEBUG_VERBOSE)
52 #define NORMAL (RADEON_DEBUG & DEBUG_VERBOSE)
56 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
57 * 1.3 cmdbuffers allow all previous state to be updated as well as
58 * the tcl scalar and vector areas.
64 } packet
[RADEON_MAX_STATE_PACKETS
] = {
65 { RADEON_PP_MISC
,7,"RADEON_PP_MISC" },
66 { RADEON_PP_CNTL
,3,"RADEON_PP_CNTL" },
67 { RADEON_RB3D_COLORPITCH
,1,"RADEON_RB3D_COLORPITCH" },
68 { RADEON_RE_LINE_PATTERN
,2,"RADEON_RE_LINE_PATTERN" },
69 { RADEON_SE_LINE_WIDTH
,1,"RADEON_SE_LINE_WIDTH" },
70 { RADEON_PP_LUM_MATRIX
,1,"RADEON_PP_LUM_MATRIX" },
71 { RADEON_PP_ROT_MATRIX_0
,2,"RADEON_PP_ROT_MATRIX_0" },
72 { RADEON_RB3D_STENCILREFMASK
,3,"RADEON_RB3D_STENCILREFMASK" },
73 { RADEON_SE_VPORT_XSCALE
,6,"RADEON_SE_VPORT_XSCALE" },
74 { RADEON_SE_CNTL
,2,"RADEON_SE_CNTL" },
75 { RADEON_SE_CNTL_STATUS
,1,"RADEON_SE_CNTL_STATUS" },
76 { RADEON_RE_MISC
,1,"RADEON_RE_MISC" },
77 { RADEON_PP_TXFILTER_0
,6,"RADEON_PP_TXFILTER_0" },
78 { RADEON_PP_BORDER_COLOR_0
,1,"RADEON_PP_BORDER_COLOR_0" },
79 { RADEON_PP_TXFILTER_1
,6,"RADEON_PP_TXFILTER_1" },
80 { RADEON_PP_BORDER_COLOR_1
,1,"RADEON_PP_BORDER_COLOR_1" },
81 { RADEON_PP_TXFILTER_2
,6,"RADEON_PP_TXFILTER_2" },
82 { RADEON_PP_BORDER_COLOR_2
,1,"RADEON_PP_BORDER_COLOR_2" },
83 { RADEON_SE_ZBIAS_FACTOR
,2,"RADEON_SE_ZBIAS_FACTOR" },
84 { RADEON_SE_TCL_OUTPUT_VTX_FMT
,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
85 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
86 { 0, 4, "R200_PP_TXCBLEND_0" },
87 { 0, 4, "R200_PP_TXCBLEND_1" },
88 { 0, 4, "R200_PP_TXCBLEND_2" },
89 { 0, 4, "R200_PP_TXCBLEND_3" },
90 { 0, 4, "R200_PP_TXCBLEND_4" },
91 { 0, 4, "R200_PP_TXCBLEND_5" },
92 { 0, 4, "R200_PP_TXCBLEND_6" },
93 { 0, 4, "R200_PP_TXCBLEND_7" },
94 { 0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
95 { 0, 6, "R200_PP_TFACTOR_0" },
96 { 0, 4, "R200_SE_VTX_FMT_0" },
97 { 0, 1, "R200_SE_VAP_CNTL" },
98 { 0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
99 { 0, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
100 { 0, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
101 { 0, 6, "R200_PP_TXFILTER_0" },
102 { 0, 6, "R200_PP_TXFILTER_1" },
103 { 0, 6, "R200_PP_TXFILTER_2" },
104 { 0, 6, "R200_PP_TXFILTER_3" },
105 { 0, 6, "R200_PP_TXFILTER_4" },
106 { 0, 6, "R200_PP_TXFILTER_5" },
107 { 0, 1, "R200_PP_TXOFFSET_0" },
108 { 0, 1, "R200_PP_TXOFFSET_1" },
109 { 0, 1, "R200_PP_TXOFFSET_2" },
110 { 0, 1, "R200_PP_TXOFFSET_3" },
111 { 0, 1, "R200_PP_TXOFFSET_4" },
112 { 0, 1, "R200_PP_TXOFFSET_5" },
113 { 0, 1, "R200_SE_VTE_CNTL" },
114 { 0, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
115 { 0, 1, "R200_PP_TAM_DEBUG3" },
116 { 0, 1, "R200_PP_CNTL_X" },
117 { 0, 1, "R200_RB3D_DEPTHXY_OFFSET" },
118 { 0, 1, "R200_RE_AUX_SCISSOR_CNTL" },
119 { 0, 2, "R200_RE_SCISSOR_TL_0" },
120 { 0, 2, "R200_RE_SCISSOR_TL_1" },
121 { 0, 2, "R200_RE_SCISSOR_TL_2" },
122 { 0, 1, "R200_SE_VAP_CNTL_STATUS" },
123 { 0, 1, "R200_SE_VTX_STATE_CNTL" },
124 { 0, 1, "R200_RE_POINTSIZE" },
125 { 0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
126 { 0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
127 { 0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
128 { 0, 1, "R200_PP_CUBIC_FACES_1" },
129 { 0, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
130 { 0, 1, "R200_PP_CUBIC_FACES_2" },
131 { 0, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
132 { 0, 1, "R200_PP_CUBIC_FACES_3" },
133 { 0, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
134 { 0, 1, "R200_PP_CUBIC_FACES_4" },
135 { 0, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
136 { 0, 1, "R200_PP_CUBIC_FACES_5" },
137 { 0, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
138 { RADEON_PP_TEX_SIZE_0
, 2, "RADEON_PP_TEX_SIZE_0" },
139 { RADEON_PP_TEX_SIZE_1
, 2, "RADEON_PP_TEX_SIZE_1" },
140 { RADEON_PP_TEX_SIZE_2
, 2, "RADEON_PP_TEX_SIZE_2" },
141 { 0, 3, "R200_RB3D_BLENDCOLOR" },
142 { 0, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
143 { RADEON_PP_CUBIC_FACES_0
, 1, "RADEON_PP_CUBIC_FACES_0" },
144 { RADEON_PP_CUBIC_OFFSET_T0_0
, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
145 { RADEON_PP_CUBIC_FACES_1
, 1, "RADEON_PP_CUBIC_FACES_1" },
146 { RADEON_PP_CUBIC_OFFSET_T1_0
, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
147 { RADEON_PP_CUBIC_FACES_2
, 1, "RADEON_PP_CUBIC_FACES_2" },
148 { RADEON_PP_CUBIC_OFFSET_T2_0
, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
149 { 0, 2, "R200_PP_TRI_PERF" },
150 { 0, 32, "R200_PP_AFS_0"}, /* 85 */
151 { 0, 32, "R200_PP_AFS_1"},
152 { 0, 8, "R200_ATF_TFACTOR"},
153 { 0, 8, "R200_PP_TXCTLALL_0"},
154 { 0, 8, "R200_PP_TXCTLALL_1"},
155 { 0, 8, "R200_PP_TXCTLALL_2"},
156 { 0, 8, "R200_PP_TXCTLALL_3"},
157 { 0, 8, "R200_PP_TXCTLALL_4"},
158 { 0, 8, "R200_PP_TXCTLALL_5"},
166 static struct reg_names reg_names
[] = {
167 { RADEON_PP_MISC
, "RADEON_PP_MISC" },
168 { RADEON_PP_FOG_COLOR
, "RADEON_PP_FOG_COLOR" },
169 { RADEON_RE_SOLID_COLOR
, "RADEON_RE_SOLID_COLOR" },
170 { RADEON_RB3D_BLENDCNTL
, "RADEON_RB3D_BLENDCNTL" },
171 { RADEON_RB3D_DEPTHOFFSET
, "RADEON_RB3D_DEPTHOFFSET" },
172 { RADEON_RB3D_DEPTHPITCH
, "RADEON_RB3D_DEPTHPITCH" },
173 { RADEON_RB3D_ZSTENCILCNTL
, "RADEON_RB3D_ZSTENCILCNTL" },
174 { RADEON_PP_CNTL
, "RADEON_PP_CNTL" },
175 { RADEON_RB3D_CNTL
, "RADEON_RB3D_CNTL" },
176 { RADEON_RB3D_COLOROFFSET
, "RADEON_RB3D_COLOROFFSET" },
177 { RADEON_RB3D_COLORPITCH
, "RADEON_RB3D_COLORPITCH" },
178 { RADEON_SE_CNTL
, "RADEON_SE_CNTL" },
179 { RADEON_SE_COORD_FMT
, "RADEON_SE_COORDFMT" },
180 { RADEON_SE_CNTL_STATUS
, "RADEON_SE_CNTL_STATUS" },
181 { RADEON_RE_LINE_PATTERN
, "RADEON_RE_LINE_PATTERN" },
182 { RADEON_RE_LINE_STATE
, "RADEON_RE_LINE_STATE" },
183 { RADEON_SE_LINE_WIDTH
, "RADEON_SE_LINE_WIDTH" },
184 { RADEON_RB3D_STENCILREFMASK
, "RADEON_RB3D_STENCILREFMASK" },
185 { RADEON_RB3D_ROPCNTL
, "RADEON_RB3D_ROPCNTL" },
186 { RADEON_RB3D_PLANEMASK
, "RADEON_RB3D_PLANEMASK" },
187 { RADEON_SE_VPORT_XSCALE
, "RADEON_SE_VPORT_XSCALE" },
188 { RADEON_SE_VPORT_XOFFSET
, "RADEON_SE_VPORT_XOFFSET" },
189 { RADEON_SE_VPORT_YSCALE
, "RADEON_SE_VPORT_YSCALE" },
190 { RADEON_SE_VPORT_YOFFSET
, "RADEON_SE_VPORT_YOFFSET" },
191 { RADEON_SE_VPORT_ZSCALE
, "RADEON_SE_VPORT_ZSCALE" },
192 { RADEON_SE_VPORT_ZOFFSET
, "RADEON_SE_VPORT_ZOFFSET" },
193 { RADEON_RE_MISC
, "RADEON_RE_MISC" },
194 { RADEON_PP_TXFILTER_0
, "RADEON_PP_TXFILTER_0" },
195 { RADEON_PP_TXFILTER_1
, "RADEON_PP_TXFILTER_1" },
196 { RADEON_PP_TXFILTER_2
, "RADEON_PP_TXFILTER_2" },
197 { RADEON_PP_TXFORMAT_0
, "RADEON_PP_TXFORMAT_0" },
198 { RADEON_PP_TXFORMAT_1
, "RADEON_PP_TXFORMAT_1" },
199 { RADEON_PP_TXFORMAT_2
, "RADEON_PP_TXFORMAT_2" },
200 { RADEON_PP_TXOFFSET_0
, "RADEON_PP_TXOFFSET_0" },
201 { RADEON_PP_TXOFFSET_1
, "RADEON_PP_TXOFFSET_1" },
202 { RADEON_PP_TXOFFSET_2
, "RADEON_PP_TXOFFSET_2" },
203 { RADEON_PP_TXCBLEND_0
, "RADEON_PP_TXCBLEND_0" },
204 { RADEON_PP_TXCBLEND_1
, "RADEON_PP_TXCBLEND_1" },
205 { RADEON_PP_TXCBLEND_2
, "RADEON_PP_TXCBLEND_2" },
206 { RADEON_PP_TXABLEND_0
, "RADEON_PP_TXABLEND_0" },
207 { RADEON_PP_TXABLEND_1
, "RADEON_PP_TXABLEND_1" },
208 { RADEON_PP_TXABLEND_2
, "RADEON_PP_TXABLEND_2" },
209 { RADEON_PP_TFACTOR_0
, "RADEON_PP_TFACTOR_0" },
210 { RADEON_PP_TFACTOR_1
, "RADEON_PP_TFACTOR_1" },
211 { RADEON_PP_TFACTOR_2
, "RADEON_PP_TFACTOR_2" },
212 { RADEON_PP_BORDER_COLOR_0
, "RADEON_PP_BORDER_COLOR_0" },
213 { RADEON_PP_BORDER_COLOR_1
, "RADEON_PP_BORDER_COLOR_1" },
214 { RADEON_PP_BORDER_COLOR_2
, "RADEON_PP_BORDER_COLOR_2" },
215 { RADEON_SE_ZBIAS_FACTOR
, "RADEON_SE_ZBIAS_FACTOR" },
216 { RADEON_SE_ZBIAS_CONSTANT
, "RADEON_SE_ZBIAS_CONSTANT" },
217 { RADEON_SE_TCL_OUTPUT_VTX_FMT
, "RADEON_SE_TCL_OUTPUT_VTXFMT" },
218 { RADEON_SE_TCL_OUTPUT_VTX_SEL
, "RADEON_SE_TCL_OUTPUT_VTXSEL" },
219 { RADEON_SE_TCL_MATRIX_SELECT_0
, "RADEON_SE_TCL_MATRIX_SELECT_0" },
220 { RADEON_SE_TCL_MATRIX_SELECT_1
, "RADEON_SE_TCL_MATRIX_SELECT_1" },
221 { RADEON_SE_TCL_UCP_VERT_BLEND_CTL
, "RADEON_SE_TCL_UCP_VERT_BLEND_CTL" },
222 { RADEON_SE_TCL_TEXTURE_PROC_CTL
, "RADEON_SE_TCL_TEXTURE_PROC_CTL" },
223 { RADEON_SE_TCL_LIGHT_MODEL_CTL
, "RADEON_SE_TCL_LIGHT_MODEL_CTL" },
224 { RADEON_SE_TCL_PER_LIGHT_CTL_0
, "RADEON_SE_TCL_PER_LIGHT_CTL_0" },
225 { RADEON_SE_TCL_PER_LIGHT_CTL_1
, "RADEON_SE_TCL_PER_LIGHT_CTL_1" },
226 { RADEON_SE_TCL_PER_LIGHT_CTL_2
, "RADEON_SE_TCL_PER_LIGHT_CTL_2" },
227 { RADEON_SE_TCL_PER_LIGHT_CTL_3
, "RADEON_SE_TCL_PER_LIGHT_CTL_3" },
228 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
, "RADEON_SE_TCL_EMMISSIVE_RED" },
229 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN
, "RADEON_SE_TCL_EMMISSIVE_GREEN" },
230 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE
, "RADEON_SE_TCL_EMMISSIVE_BLUE" },
231 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA
, "RADEON_SE_TCL_EMMISSIVE_ALPHA" },
232 { RADEON_SE_TCL_MATERIAL_AMBIENT_RED
, "RADEON_SE_TCL_AMBIENT_RED" },
233 { RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN
, "RADEON_SE_TCL_AMBIENT_GREEN" },
234 { RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE
, "RADEON_SE_TCL_AMBIENT_BLUE" },
235 { RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA
, "RADEON_SE_TCL_AMBIENT_ALPHA" },
236 { RADEON_SE_TCL_MATERIAL_DIFFUSE_RED
, "RADEON_SE_TCL_DIFFUSE_RED" },
237 { RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN
, "RADEON_SE_TCL_DIFFUSE_GREEN" },
238 { RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE
, "RADEON_SE_TCL_DIFFUSE_BLUE" },
239 { RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA
, "RADEON_SE_TCL_DIFFUSE_ALPHA" },
240 { RADEON_SE_TCL_MATERIAL_SPECULAR_RED
, "RADEON_SE_TCL_SPECULAR_RED" },
241 { RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN
, "RADEON_SE_TCL_SPECULAR_GREEN" },
242 { RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE
, "RADEON_SE_TCL_SPECULAR_BLUE" },
243 { RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA
, "RADEON_SE_TCL_SPECULAR_ALPHA" },
244 { RADEON_SE_TCL_SHININESS
, "RADEON_SE_TCL_SHININESS" },
245 { RADEON_SE_COORD_FMT
, "RADEON_SE_COORD_FMT" },
246 { RADEON_PP_TEX_SIZE_0
, "RADEON_PP_TEX_SIZE_0" },
247 { RADEON_PP_TEX_SIZE_1
, "RADEON_PP_TEX_SIZE_1" },
248 { RADEON_PP_TEX_SIZE_2
, "RADEON_PP_TEX_SIZE_2" },
249 { RADEON_PP_TEX_SIZE_0
+4, "RADEON_PP_TEX_PITCH_0" },
250 { RADEON_PP_TEX_SIZE_1
+4, "RADEON_PP_TEX_PITCH_1" },
251 { RADEON_PP_TEX_SIZE_2
+4, "RADEON_PP_TEX_PITCH_2" },
252 { RADEON_PP_CUBIC_FACES_0
, "RADEON_PP_CUBIC_FACES_0" },
253 { RADEON_PP_CUBIC_FACES_1
, "RADEON_PP_CUBIC_FACES_1" },
254 { RADEON_PP_CUBIC_FACES_2
, "RADEON_PP_CUBIC_FACES_2" },
255 { RADEON_PP_CUBIC_OFFSET_T0_0
, "RADEON_PP_CUBIC_OFFSET_T0_0" },
256 { RADEON_PP_CUBIC_OFFSET_T0_1
, "RADEON_PP_CUBIC_OFFSET_T0_1" },
257 { RADEON_PP_CUBIC_OFFSET_T0_2
, "RADEON_PP_CUBIC_OFFSET_T0_2" },
258 { RADEON_PP_CUBIC_OFFSET_T0_3
, "RADEON_PP_CUBIC_OFFSET_T0_3" },
259 { RADEON_PP_CUBIC_OFFSET_T0_4
, "RADEON_PP_CUBIC_OFFSET_T0_4" },
260 { RADEON_PP_CUBIC_OFFSET_T1_0
, "RADEON_PP_CUBIC_OFFSET_T1_0" },
261 { RADEON_PP_CUBIC_OFFSET_T1_1
, "RADEON_PP_CUBIC_OFFSET_T1_1" },
262 { RADEON_PP_CUBIC_OFFSET_T1_2
, "RADEON_PP_CUBIC_OFFSET_T1_2" },
263 { RADEON_PP_CUBIC_OFFSET_T1_3
, "RADEON_PP_CUBIC_OFFSET_T1_3" },
264 { RADEON_PP_CUBIC_OFFSET_T1_4
, "RADEON_PP_CUBIC_OFFSET_T1_4" },
265 { RADEON_PP_CUBIC_OFFSET_T2_0
, "RADEON_PP_CUBIC_OFFSET_T2_0" },
266 { RADEON_PP_CUBIC_OFFSET_T2_1
, "RADEON_PP_CUBIC_OFFSET_T2_1" },
267 { RADEON_PP_CUBIC_OFFSET_T2_2
, "RADEON_PP_CUBIC_OFFSET_T2_2" },
268 { RADEON_PP_CUBIC_OFFSET_T2_3
, "RADEON_PP_CUBIC_OFFSET_T2_3" },
269 { RADEON_PP_CUBIC_OFFSET_T2_4
, "RADEON_PP_CUBIC_OFFSET_T2_4" },
272 static struct reg_names scalar_names
[] = {
273 { RADEON_SS_LIGHT_DCD_ADDR
, "LIGHT_DCD" },
274 { RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR
, "LIGHT_SPOT_EXPONENT" },
275 { RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR
, "LIGHT_SPOT_CUTOFF" },
276 { RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR
, "LIGHT_SPECULAR_THRESH" },
277 { RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR
, "LIGHT_RANGE_CUTOFF" },
278 { RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR
, "VERT_GUARD_CLIP" },
279 { RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR
, "VERT_GUARD_DISCARD" },
280 { RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR
, "HORZ_GUARD_CLIP" },
281 { RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR
, "HORZ_GUARD_DISCARD" },
282 { RADEON_SS_SHININESS
, "SHININESS" },
286 /* Puff these out to make them look like normal (dword) registers.
288 static struct reg_names vector_names
[] = {
289 { RADEON_VS_MATRIX_0_ADDR
* 4, "MATRIX_0" },
290 { RADEON_VS_MATRIX_1_ADDR
* 4, "MATRIX_1" },
291 { RADEON_VS_MATRIX_2_ADDR
* 4, "MATRIX_2" },
292 { RADEON_VS_MATRIX_3_ADDR
* 4, "MATRIX_3" },
293 { RADEON_VS_MATRIX_4_ADDR
* 4, "MATRIX_4" },
294 { RADEON_VS_MATRIX_5_ADDR
* 4, "MATRIX_5" },
295 { RADEON_VS_MATRIX_6_ADDR
* 4, "MATRIX_6" },
296 { RADEON_VS_MATRIX_7_ADDR
* 4, "MATRIX_7" },
297 { RADEON_VS_MATRIX_8_ADDR
* 4, "MATRIX_8" },
298 { RADEON_VS_MATRIX_9_ADDR
* 4, "MATRIX_9" },
299 { RADEON_VS_MATRIX_10_ADDR
* 4, "MATRIX_10" },
300 { RADEON_VS_MATRIX_11_ADDR
* 4, "MATRIX_11" },
301 { RADEON_VS_MATRIX_12_ADDR
* 4, "MATRIX_12" },
302 { RADEON_VS_MATRIX_13_ADDR
* 4, "MATRIX_13" },
303 { RADEON_VS_MATRIX_14_ADDR
* 4, "MATRIX_14" },
304 { RADEON_VS_MATRIX_15_ADDR
* 4, "MATRIX_15" },
305 { RADEON_VS_LIGHT_AMBIENT_ADDR
* 4, "LIGHT_AMBIENT" },
306 { RADEON_VS_LIGHT_DIFFUSE_ADDR
* 4, "LIGHT_DIFFUSE" },
307 { RADEON_VS_LIGHT_SPECULAR_ADDR
* 4, "LIGHT_SPECULAR" },
308 { RADEON_VS_LIGHT_DIRPOS_ADDR
* 4, "LIGHT_DIRPOS" },
309 { RADEON_VS_LIGHT_HWVSPOT_ADDR
* 4, "LIGHT_HWVSPOT" },
310 { RADEON_VS_LIGHT_ATTENUATION_ADDR
* 4, "LIGHT_ATTENUATION" },
311 { RADEON_VS_MATRIX_EYE2CLIP_ADDR
* 4, "MATRIX_EYE2CLIP" },
312 { RADEON_VS_UCP_ADDR
* 4, "UCP" },
313 { RADEON_VS_GLOBAL_AMBIENT_ADDR
* 4, "GLOBAL_AMBIENT" },
314 { RADEON_VS_FOG_PARAM_ADDR
* 4, "FOG_PARAM" },
315 { RADEON_VS_EYE_VECTOR_ADDR
* 4, "EYE_VECTOR" },
319 union fi
{ float f
; int i
; };
327 struct reg_names
*closest
;
337 static struct reg regs
[Elements(reg_names
)+1];
338 static struct reg scalars
[512+1];
339 static struct reg vectors
[512*4+1];
341 static int total
, total_changed
, bufs
;
343 static void init_regs( void )
345 struct reg_names
*tmp
;
348 for (i
= 0 ; i
< Elements(regs
) ; i
++) {
349 regs
[i
].idx
= reg_names
[i
].idx
;
350 regs
[i
].closest
= ®_names
[i
];
354 for (i
= 0, tmp
= scalar_names
; i
< Elements(scalars
) ; i
++) {
355 if (tmp
[1].idx
== i
) tmp
++;
357 scalars
[i
].closest
= tmp
;
358 scalars
[i
].flags
= ISFLOAT
;
361 for (i
= 0, tmp
= vector_names
; i
< Elements(vectors
) ; i
++) {
362 if (tmp
[1].idx
*4 == i
) tmp
++;
364 vectors
[i
].closest
= tmp
;
365 vectors
[i
].flags
= ISFLOAT
|ISVEC
;
368 regs
[Elements(regs
)-1].idx
= -1;
369 scalars
[Elements(scalars
)-1].idx
= -1;
370 vectors
[Elements(vectors
)-1].idx
= -1;
373 static int find_or_add_value( struct reg
*reg
, int val
)
377 for ( j
= 0 ; j
< reg
->nvalues
; j
++)
378 if ( val
== reg
->values
[j
].i
)
381 if (j
== reg
->nalloc
) {
384 reg
->values
= (union fi
*) realloc( reg
->values
,
385 reg
->nalloc
* sizeof(union fi
) );
388 reg
->values
[reg
->nvalues
++].i
= val
;
392 static struct reg
*lookup_reg( struct reg
*tab
, int reg
)
396 for (i
= 0 ; tab
[i
].idx
!= -1 ; i
++) {
397 if (tab
[i
].idx
== reg
)
401 fprintf(stderr
, "*** unknown reg 0x%x\n", reg
);
406 static const char *get_reg_name( struct reg
*reg
)
410 if (reg
->idx
== reg
->closest
->idx
)
411 return reg
->closest
->name
;
414 if (reg
->flags
& ISVEC
) {
415 if (reg
->idx
/4 != reg
->closest
->idx
)
416 sprintf(tmp
, "%s+%d[%d]",
418 (reg
->idx
/4) - reg
->closest
->idx
,
421 sprintf(tmp
, "%s[%d]", reg
->closest
->name
, reg
->idx
%4);
424 if (reg
->idx
!= reg
->closest
->idx
)
425 sprintf(tmp
, "%s+%d", reg
->closest
->name
, reg
->idx
- reg
->closest
->idx
);
427 sprintf(tmp
, "%s", reg
->closest
->name
);
433 static int print_int_reg_assignment( struct reg
*reg
, int data
)
435 int changed
= (reg
->current
.i
!= data
);
436 int ever_seen
= find_or_add_value( reg
, data
);
438 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
439 fprintf(stderr
, " %s <-- 0x%x", get_reg_name(reg
), data
);
443 fprintf(stderr
, " *** BRAND NEW VALUE");
445 fprintf(stderr
, " *** CHANGED");
448 reg
->current
.i
= data
;
450 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
451 fprintf(stderr
, "\n");
457 static int print_float_reg_assignment( struct reg
*reg
, float data
)
459 int changed
= (reg
->current
.f
!= data
);
460 int newmin
= (data
< reg
->vmin
);
461 int newmax
= (data
> reg
->vmax
);
463 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
464 fprintf(stderr
, " %s <-- %.3f", get_reg_name(reg
), data
);
468 fprintf(stderr
, " *** NEW MIN (prev %.3f)", reg
->vmin
);
472 fprintf(stderr
, " *** NEW MAX (prev %.3f)", reg
->vmax
);
476 fprintf(stderr
, " *** CHANGED");
480 reg
->current
.f
= data
;
482 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
483 fprintf(stderr
, "\n");
488 static int print_reg_assignment( struct reg
*reg
, int data
)
490 reg
->flags
|= TOUCHED
;
491 if (reg
->flags
& ISFLOAT
)
492 return print_float_reg_assignment( reg
, *(float *)&data
);
494 return print_int_reg_assignment( reg
, data
);
497 static void print_reg( struct reg
*reg
)
499 if (reg
->flags
& TOUCHED
) {
500 if (reg
->flags
& ISFLOAT
) {
501 fprintf(stderr
, " %s == %f\n", get_reg_name(reg
), reg
->current
.f
);
503 fprintf(stderr
, " %s == 0x%x\n", get_reg_name(reg
), reg
->current
.i
);
509 static void dump_state( void )
513 for (i
= 0 ; i
< Elements(regs
) ; i
++)
514 print_reg( ®s
[i
] );
516 for (i
= 0 ; i
< Elements(scalars
) ; i
++)
517 print_reg( &scalars
[i
] );
519 for (i
= 0 ; i
< Elements(vectors
) ; i
++)
520 print_reg( &vectors
[i
] );
525 static int radeon_emit_packets(
526 drm_radeon_cmd_header_t header
,
527 drm_radeon_cmd_buffer_t
*cmdbuf
)
529 int id
= (int)header
.packet
.packet_id
;
530 int sz
= packet
[id
].len
;
531 int *data
= (int *)cmdbuf
->buf
;
534 if (sz
* sizeof(int) > cmdbuf
->bufsz
) {
535 fprintf(stderr
, "Packet overflows cmdbuf\n");
539 if (!packet
[id
].name
) {
540 fprintf(stderr
, "*** Unknown packet 0 nr %d\n", id
);
546 fprintf(stderr
, "Packet 0 reg %s nr %d\n", packet
[id
].name
, sz
);
548 for ( i
= 0 ; i
< sz
; i
++) {
549 struct reg
*reg
= lookup_reg( regs
, packet
[id
].start
+ i
*4 );
550 if (print_reg_assignment( reg
, data
[i
] ))
555 cmdbuf
->buf
+= sz
* sizeof(int);
556 cmdbuf
->bufsz
-= sz
* sizeof(int);
561 static int radeon_emit_scalars(
562 drm_radeon_cmd_header_t header
,
563 drm_radeon_cmd_buffer_t
*cmdbuf
)
565 int sz
= header
.scalars
.count
;
566 int *data
= (int *)cmdbuf
->buf
;
567 int start
= header
.scalars
.offset
;
568 int stride
= header
.scalars
.stride
;
572 fprintf(stderr
, "emit scalars, start %d stride %d nr %d (end %d)\n",
573 start
, stride
, sz
, start
+ stride
* sz
);
576 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
577 struct reg
*reg
= lookup_reg( scalars
, start
);
578 if (print_reg_assignment( reg
, data
[i
] ))
583 cmdbuf
->buf
+= sz
* sizeof(int);
584 cmdbuf
->bufsz
-= sz
* sizeof(int);
589 static int radeon_emit_scalars2(
590 drm_radeon_cmd_header_t header
,
591 drm_radeon_cmd_buffer_t
*cmdbuf
)
593 int sz
= header
.scalars
.count
;
594 int *data
= (int *)cmdbuf
->buf
;
595 int start
= header
.scalars
.offset
+ 0x100;
596 int stride
= header
.scalars
.stride
;
600 fprintf(stderr
, "emit scalars2, start %d stride %d nr %d (end %d)\n",
601 start
, stride
, sz
, start
+ stride
* sz
);
603 if (start
+ stride
* sz
> 257) {
604 fprintf(stderr
, "emit scalars OVERFLOW %d/%d/%d\n", start
, stride
, sz
);
608 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
609 struct reg
*reg
= lookup_reg( scalars
, start
);
610 if (print_reg_assignment( reg
, data
[i
] ))
615 cmdbuf
->buf
+= sz
* sizeof(int);
616 cmdbuf
->bufsz
-= sz
* sizeof(int);
620 /* Check: inf/nan/extreme-size?
621 * Check: table start, end, nr, etc.
623 static int radeon_emit_vectors(
624 drm_radeon_cmd_header_t header
,
625 drm_radeon_cmd_buffer_t
*cmdbuf
)
627 int sz
= header
.vectors
.count
;
628 int *data
= (int *)cmdbuf
->buf
;
629 int start
= header
.vectors
.offset
;
630 int stride
= header
.vectors
.stride
;
634 fprintf(stderr
, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
635 start
, stride
, sz
, start
+ stride
* sz
, header
.i
);
637 /* if (start + stride * (sz/4) > 128) { */
638 /* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
642 for (i
= 0 ; i
< sz
; start
+= stride
) {
644 for (j
= 0 ; j
< 4 ; i
++,j
++) {
645 struct reg
*reg
= lookup_reg( vectors
, start
*4+j
);
646 if (print_reg_assignment( reg
, data
[i
] ))
655 cmdbuf
->buf
+= sz
* sizeof(int);
656 cmdbuf
->bufsz
-= sz
* sizeof(int);
661 static int print_vertex_format( int vfmt
)
664 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
668 (vfmt
& RADEON_CP_VC_FRMT_Z
) ? "z," : "",
669 (vfmt
& RADEON_CP_VC_FRMT_W0
) ? "w0," : "",
670 (vfmt
& RADEON_CP_VC_FRMT_FPCOLOR
) ? "fpcolor," : "",
671 (vfmt
& RADEON_CP_VC_FRMT_FPALPHA
) ? "fpalpha," : "",
672 (vfmt
& RADEON_CP_VC_FRMT_PKCOLOR
) ? "pkcolor," : "",
673 (vfmt
& RADEON_CP_VC_FRMT_FPSPEC
) ? "fpspec," : "",
674 (vfmt
& RADEON_CP_VC_FRMT_FPFOG
) ? "fpfog," : "",
675 (vfmt
& RADEON_CP_VC_FRMT_PKSPEC
) ? "pkspec," : "",
676 (vfmt
& RADEON_CP_VC_FRMT_ST0
) ? "st0," : "",
677 (vfmt
& RADEON_CP_VC_FRMT_ST1
) ? "st1," : "",
678 (vfmt
& RADEON_CP_VC_FRMT_Q1
) ? "q1," : "",
679 (vfmt
& RADEON_CP_VC_FRMT_ST2
) ? "st2," : "",
680 (vfmt
& RADEON_CP_VC_FRMT_Q2
) ? "q2," : "",
681 (vfmt
& RADEON_CP_VC_FRMT_ST3
) ? "st3," : "",
682 (vfmt
& RADEON_CP_VC_FRMT_Q3
) ? "q3," : "",
683 (vfmt
& RADEON_CP_VC_FRMT_Q0
) ? "q0," : "",
684 (vfmt
& RADEON_CP_VC_FRMT_N0
) ? "n0," : "",
685 (vfmt
& RADEON_CP_VC_FRMT_XY1
) ? "xy1," : "",
686 (vfmt
& RADEON_CP_VC_FRMT_Z1
) ? "z1," : "",
687 (vfmt
& RADEON_CP_VC_FRMT_W1
) ? "w1," : "",
688 (vfmt
& RADEON_CP_VC_FRMT_N1
) ? "n1," : "");
691 /* if (!find_or_add_value( &others[V_VTXFMT], vfmt )) */
692 /* fprintf(stderr, " *** NEW VALUE"); */
694 fprintf(stderr
, "\n");
700 static char *primname
[0xf] = {
714 static int print_prim_and_flags( int prim
)
719 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s%s\n",
722 ((prim
& 0x30) == RADEON_CP_VC_CNTL_PRIM_WALK_IND
) ? "IND," : "",
723 ((prim
& 0x30) == RADEON_CP_VC_CNTL_PRIM_WALK_LIST
) ? "LIST," : "",
724 ((prim
& 0x30) == RADEON_CP_VC_CNTL_PRIM_WALK_RING
) ? "RING," : "",
725 (prim
& RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
) ? "RGBA," : "BGRA, ",
726 (prim
& RADEON_CP_VC_CNTL_MAOS_ENABLE
) ? "MAOS," : "",
727 (prim
& RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
) ? "RADEON," : "",
728 (prim
& RADEON_CP_VC_CNTL_TCL_ENABLE
) ? "TCL," : "");
730 if ((prim
& 0xf) > RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST
) {
731 fprintf(stderr
, " *** Bad primitive: %x\n", prim
& 0xf);
738 fprintf(stderr
, " prim: %s numverts %d\n", primname
[prim
&0xf], numverts
);
740 switch (prim
& 0xf) {
741 case RADEON_CP_VC_CNTL_PRIM_TYPE_NONE
:
742 case RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
:
744 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
748 case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
:
749 if ((numverts
& 1) || numverts
== 0) {
750 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
754 case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
:
756 fprintf(stderr
, "Bad nr verts for line_strip %d\n", numverts
);
760 case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
:
761 case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST
:
762 case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST
:
763 case RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
:
764 if (numverts
% 3 || numverts
== 0) {
765 fprintf(stderr
, "Bad nr verts for tri %d\n", numverts
);
769 case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
:
770 case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
:
772 fprintf(stderr
, "Bad nr verts for strip/fan %d\n", numverts
);
777 fprintf(stderr
, "Bad primitive\n");
783 /* build in knowledge about each packet type
785 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t
*cmdbuf
)
788 int *cmd
= (int *)cmdbuf
->buf
;
790 int i
, stride
, size
, start
;
792 cmdsz
= 2 + ((cmd
[0] & RADEON_CP_PACKET_COUNT_MASK
) >> 16);
794 if ((cmd
[0] & RADEON_CP_PACKET_MASK
) != RADEON_CP_PACKET3
||
795 cmdsz
* 4 > cmdbuf
->bufsz
||
796 cmdsz
> RADEON_CP_PACKET_MAX_DWORDS
) {
797 fprintf(stderr
, "Bad packet\n");
801 switch( cmd
[0] & ~RADEON_CP_PACKET_COUNT_MASK
) {
802 case RADEON_CP_PACKET3_NOP
:
804 fprintf(stderr
, "PACKET3_NOP, %d dwords\n", cmdsz
);
806 case RADEON_CP_PACKET3_NEXT_CHAR
:
808 fprintf(stderr
, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz
);
810 case RADEON_CP_PACKET3_PLY_NEXTSCAN
:
812 fprintf(stderr
, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz
);
814 case RADEON_CP_PACKET3_SET_SCISSORS
:
816 fprintf(stderr
, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz
);
818 case RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM
:
820 fprintf(stderr
, "PACKET3_3D_RNDR_GEN_INDX_PRIM, %d dwords\n",
823 case RADEON_CP_PACKET3_LOAD_MICROCODE
:
825 fprintf(stderr
, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz
);
827 case RADEON_CP_PACKET3_WAIT_FOR_IDLE
:
829 fprintf(stderr
, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz
);
832 case RADEON_CP_PACKET3_3D_DRAW_VBUF
:
834 fprintf(stderr
, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz
);
835 print_vertex_format(cmd
[1]);
836 print_prim_and_flags(cmd
[2]);
839 case RADEON_CP_PACKET3_3D_DRAW_IMMD
:
841 fprintf(stderr
, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz
);
843 case RADEON_CP_PACKET3_3D_DRAW_INDX
: {
846 fprintf(stderr
, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz
);
847 print_vertex_format(cmd
[1]);
848 print_prim_and_flags(cmd
[2]);
849 neltdwords
= cmd
[2]>>16;
850 neltdwords
+= neltdwords
& 1;
852 if (neltdwords
+ 3 != cmdsz
)
853 fprintf(stderr
, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
857 case RADEON_CP_PACKET3_LOAD_PALETTE
:
859 fprintf(stderr
, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz
);
861 case RADEON_CP_PACKET3_3D_LOAD_VBPNTR
:
863 fprintf(stderr
, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz
);
864 fprintf(stderr
, " nr arrays: %d\n", cmd
[1]);
867 if (cmd
[1]/2 + cmd
[1]%2 != cmdsz
- 3) {
868 fprintf(stderr
, " ****** MISMATCH %d/%d *******\n",
869 cmd
[1]/2 + cmd
[1]%2 + 3, cmdsz
);
875 for (i
= 0 ; i
< cmd
[1] ; i
++) {
877 stride
= (tmp
[0]>>24) & 0xff;
878 size
= (tmp
[0]>>16) & 0xff;
883 stride
= (tmp
[0]>>8) & 0xff;
884 size
= (tmp
[0]) & 0xff;
887 fprintf(stderr
, " array %d: start 0x%x vsize %d vstride %d\n",
888 i
, start
, size
, stride
);
892 case RADEON_CP_PACKET3_CNTL_PAINT
:
894 fprintf(stderr
, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz
);
896 case RADEON_CP_PACKET3_CNTL_BITBLT
:
898 fprintf(stderr
, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz
);
900 case RADEON_CP_PACKET3_CNTL_SMALLTEXT
:
902 fprintf(stderr
, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz
);
904 case RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT
:
906 fprintf(stderr
, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
909 case RADEON_CP_PACKET3_CNTL_POLYLINE
:
911 fprintf(stderr
, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz
);
913 case RADEON_CP_PACKET3_CNTL_POLYSCANLINES
:
915 fprintf(stderr
, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
918 case RADEON_CP_PACKET3_CNTL_PAINT_MULTI
:
920 fprintf(stderr
, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
923 case RADEON_CP_PACKET3_CNTL_BITBLT_MULTI
:
925 fprintf(stderr
, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
928 case RADEON_CP_PACKET3_CNTL_TRANS_BITBLT
:
930 fprintf(stderr
, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
934 fprintf(stderr
, "UNKNOWN PACKET, %d dwords\n", cmdsz
);
938 cmdbuf
->buf
+= cmdsz
* 4;
939 cmdbuf
->bufsz
-= cmdsz
* 4;
944 /* Check cliprects for bounds, then pass on to above:
946 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t
*cmdbuf
)
948 drm_clip_rect_t
*boxes
= cmdbuf
->boxes
;
951 if (VERBOSE
&& total_changed
) {
955 else fprintf(stderr
, "total_changed zero\n");
959 if ( i
< cmdbuf
->nbox
) {
960 fprintf(stderr
, "Emit box %d/%d %d,%d %d,%d\n",
962 boxes
[i
].x1
, boxes
[i
].y1
, boxes
[i
].x2
, boxes
[i
].y2
);
964 } while ( ++i
< cmdbuf
->nbox
);
967 if (cmdbuf
->nbox
== 1)
970 return radeon_emit_packet3( cmdbuf
);
974 int radeonSanityCmdBuffer( radeonContextPtr rmesa
,
976 drm_clip_rect_t
*boxes
)
979 drm_radeon_cmd_buffer_t cmdbuf
;
980 drm_radeon_cmd_header_t header
;
981 static int inited
= 0;
988 cmdbuf
.buf
= rmesa
->store
.cmd_buf
;
989 cmdbuf
.bufsz
= rmesa
->store
.cmd_used
;
990 cmdbuf
.boxes
= boxes
;
993 while ( cmdbuf
.bufsz
>= sizeof(header
) ) {
995 header
.i
= *(int *)cmdbuf
.buf
;
996 cmdbuf
.buf
+= sizeof(header
);
997 cmdbuf
.bufsz
-= sizeof(header
);
999 switch (header
.header
.cmd_type
) {
1000 case RADEON_CMD_PACKET
:
1001 if (radeon_emit_packets( header
, &cmdbuf
)) {
1002 fprintf(stderr
,"radeon_emit_packets failed\n");
1007 case RADEON_CMD_SCALARS
:
1008 if (radeon_emit_scalars( header
, &cmdbuf
)) {
1009 fprintf(stderr
,"radeon_emit_scalars failed\n");
1014 case RADEON_CMD_SCALARS2
:
1015 if (radeon_emit_scalars2( header
, &cmdbuf
)) {
1016 fprintf(stderr
,"radeon_emit_scalars failed\n");
1021 case RADEON_CMD_VECTORS
:
1022 if (radeon_emit_vectors( header
, &cmdbuf
)) {
1023 fprintf(stderr
,"radeon_emit_vectors failed\n");
1028 case RADEON_CMD_DMA_DISCARD
:
1029 idx
= header
.dma
.buf_idx
;
1031 fprintf(stderr
, "RADEON_CMD_DMA_DISCARD buf %d\n", idx
);
1035 case RADEON_CMD_PACKET3
:
1036 if (radeon_emit_packet3( &cmdbuf
)) {
1037 fprintf(stderr
,"radeon_emit_packet3 failed\n");
1042 case RADEON_CMD_PACKET3_CLIP
:
1043 if (radeon_emit_packet3_cliprect( &cmdbuf
)) {
1044 fprintf(stderr
,"radeon_emit_packet3_clip failed\n");
1049 case RADEON_CMD_WAIT
:
1053 fprintf(stderr
,"bad cmd_type %d at %p\n",
1054 header
.header
.cmd_type
,
1055 cmdbuf
.buf
- sizeof(header
));
1065 fprintf(stderr
, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1067 total
, total_changed
,
1068 ((float)total_changed
/(float)total
*100.0));
1069 fprintf(stderr
, "Total emitted per buf: %.2f\n",
1070 (float)total
/(float)bufs
);
1071 fprintf(stderr
, "Real changes per buf: %.2f\n",
1072 (float)total_changed
/(float)bufs
);
1074 bufs
= n
= total
= total_changed
= 0;